KR950000852B1 - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor device Download PDFInfo
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- KR950000852B1 KR950000852B1 KR1019910016000A KR910016000A KR950000852B1 KR 950000852 B1 KR950000852 B1 KR 950000852B1 KR 1019910016000 A KR1019910016000 A KR 1019910016000A KR 910016000 A KR910016000 A KR 910016000A KR 950000852 B1 KR950000852 B1 KR 950000852B1
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- Prior art keywords
- bit line
- forming
- oxide film
- polysilicon
- layer
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
제 1 도는 본 발명 반도체소자의 공정단면도.1 is a process sectional view of a semiconductor device of the present invention.
제 2 도는 일반적인 반도체소자의 레이아웃도.2 is a layout diagram of a general semiconductor device.
제 3 도는 제 2 도의 A-A′선상 단면도.3 is a cross-sectional view along the line A-A 'of FIG.
제 4 도는 종래의 공정에 따른 비트라인 구조 사시도.4 is a perspective view of a bit line structure according to a conventional process.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 필드산화막1 substrate 2 field oxide film
3 : 게이트 4 : 캡산화막3: gate 4: cap oxide film
5 : 측벽산화막 6 : 더미 폴리실리콘5: sidewall oxide film 6: dummy polysilicon
7A∼7C: 산화막 8 : 폴리실리콘7 A to 7 C : oxide film 8: polysilicon
9 : 실리사이드9: silicide
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 비트라인 폴리실리콘 아래부분을 평탄화하여 이후 공정을 용이하게 하며 기생 캐패시턴스를 줄일 수 있도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a lower portion of a bit line polysilicon is planarized to facilitate subsequent processes and to reduce parasitic capacitance.
종래의 반도체소자의 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional method for manufacturing a semiconductor device is as follows.
제 2 도는 일반적인 반도체소자의 레이아웃도이고, 제 3 도는 제 2 도의 A-A′선상 단면도이며, 제 4 도는 종래의 공정에 따른 비트라인구조 사시도이다.2 is a layout diagram of a general semiconductor device, FIG. 3 is a cross-sectional view taken along line A-A 'of FIG. 2, and FIG. 4 is a perspective view of a bit line structure according to a conventional process.
종래의 쉴드 비트라인(Shielded Bit Line)형성 기술은 게이트 라인형성 후 그 위에 비트라인용 폴리실리콘을 증착하고 에치백(Etch Back)으로 폴리실리콘을 평탄화하며 실리사이드를 증착하여 비트라인을 형성하는 기술을 이용하였다.Conventional shielded bit line forming technology is a technique for depositing polysilicon for bit line on the gate line after forming the gate line, planarizing polysilicon with etch back, and depositing silicide to form a bit line. Was used.
즉, 기판(1)상에 일방향으로 일정간격을 갖고 복수개의 워드라인(W/L)이 형성되고, 상기 워드라인(W/L)과 수직방향으로 일정간격을 갖고 복수개의 비트라인(B/L)이 형성되고, 비트라인(B/L) 사이에 갈매기 형상으로 이웃하는 2개의 워드라인(W/L)에 걸쳐 활성영역(A/R)이 형성되고, 상기 워드라인(W/L)양측의 활성영역(A/R)에 커패시터 콘택(C/C)이 형성되고, 워드라인(W/L) 사이의 활성영역(A/R)에 비트라인 콘택(B/C)이 형성되는 구조로 되어 있다.That is, a plurality of word lines W / L are formed on the substrate 1 at predetermined intervals in one direction, and a plurality of bit lines B / have a predetermined interval in the vertical direction with the word lines W / L. L) is formed, and an active region A / R is formed over two word lines W / L neighboring in a chevron shape between bit lines B / L, and the word lines W / L. Capacitor contacts C / C are formed in the active regions A / R on both sides, and bit line contacts B / C are formed in the active regions A / R between the word lines W / L. It is.
이와같은 종래 반도체소자의 제조방법은 다음과 같다.The manufacturing method of such a conventional semiconductor device is as follows.
제 3 도에서 실리콘기판(1)에 활성영역을 정의하여 필드영역에 필드산화막(2)을 형성하고 전면에 게이트 절연막(도면에는 도시되지 않음)을 형성한 다음, 제 2 도와 같이 일방향으로 캡산화막(4)과 게이트(3) 전극(워드라인)을 형성한다.In FIG. 3, the active region is defined in the silicon substrate 1 to form the field oxide film 2 in the field region, the gate insulating film (not shown) is formed on the front surface, and the cap oxide film is oriented in one direction as shown in FIG. (4) and gate (3) electrodes (word lines) are formed.
그리고 게이트 전극을 마스크로 활성영역에 고농도 불순물 이온주입하여 소오스 및 드레인영역(n+)을 형성한 다음, 게이트 전극 측면에 측벽산화막(5)을 형성하고 전면에 절연막(도면에는 도시되지 않음)을 증착한 후, 비트라인 콘택홀을 형성하고 폴리실리콘(8)을 평탄하게 형성한다.The source and drain regions (n + ) are formed by implanting a high concentration of impurity ions into the active region using a gate electrode as a mask, and then a sidewall oxide film 5 is formed on the side of the gate electrode, and an insulating film (not shown) is formed on the entire surface of the gate electrode. After deposition, bit line contact holes are formed and the polysilicon 8 is formed flat.
상기 폴리실리콘(8)위에 실리사이드(9)를 형성하고 비트라인영역을 정의하여 비트라인을 제외한 영역의 실리사이드(9)와 폴리실리콘(8)을 제거하여 비트라인(B/L)을 형성한다.The silicide 9 is formed on the polysilicon 8 and the bit line region is defined to remove the silicide 9 and the polysilicon 8 except for the bit line to form the bit line B / L.
이때, 제 3 도에서 보는 바와같이 게이트 전극 상부의 폴리실리콘(8)의 두께(c)와 게이트 전극 사이의 폴리실리콘(8)의 두께(d)차가 있으므로 비트라인(B/L) 형성시 폴리실리콘(8)이 충분히 제거되도록 오버에치를 해야 한다.At this time, as shown in FIG. 3, there is a difference between the thickness c of the polysilicon 8 on the gate electrode and the thickness d of the polysilicon 8 between the gate electrode. Overetch should be made to ensure that the silicon 8 is sufficiently removed.
그러나 이와같은 종래의 반도체소자의 제조방법에 있어서는 다음과 같은 문제점이 있었다.However, such a conventional method of manufacturing a semiconductor device has the following problems.
즉, 비트라인(B/L)의 길이를 직선으로 하여 저항값을 작게하고 비트라인의 평탄화로 이후 공정이 수월하지만 집적도가 증가하게 되면 비트라인 사이의 간격이 좁아지게 되고, 이에 따라 이웃하는 비트라인의 워드라인(W/L)과 워드라인(W/L)사이 부분 두께(제 2 도의 a, b부분)가 두꺼워져서 인접 비트라인의 상호작용에 따른 기생 캐패시턴스(Coupling Capacitance)가 커진다. 뿐만아니라 비트라인의 높이 차이가 심하여 골에서 비트라인의 언더컬(Undercut)에 어려움이 있으며, 골에서의 비트라인을 충분히 정의하기 위하여 오버에치를 하여야만 하였고, 이로 인하여 비트라인의 하부층이 상부층보다 폭이 더 좁아지게 되는 단점이 있었다.In other words, if the length of the bit line (B / L) is a straight line, the resistance value is reduced and the bit line is flattened to facilitate the subsequent process, but when the degree of integration increases, the spacing between the bit lines becomes narrower. The portion thickness (a and b portions in FIG. 2) between the word line W / L and the word line W / L of the line is thickened to increase the parasitic capacitance due to the interaction of adjacent bit lines. In addition, the bit line height difference is difficult to undercut the bit line in the goal, and overetching has to be made in order to fully define the bit line in the goal, so that the lower layer of the bit line is wider than the upper layer. There was a drawback to this being narrower.
본 발명은 이와같은 종래의 결점을 감안하여 안출한 것으로 비트라인 폴리실리콘 아래 부분을 평탄화하여 비트라인의 두께를 줄임과 동시에 두께를 균일하게 하고 그에따른 기생 캐패시턴스를 줄임으로써 양질의 반도체소자를 제조하는데 그 목적이 있다.The present invention has been made in view of the above-mentioned drawbacks in the manufacture of high-quality semiconductor devices by planarizing the lower portion of the bit line polysilicon to reduce the thickness of the bit line and at the same time make the thickness uniform and reduce the parasitic capacitance. The purpose is.
이하에서 이와같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings.
제 1 도는 본 발명 반도체소자의 공정단면도이고 이의 레이아웃도는 제 2 도와 같다.FIG. 1 is a process cross-sectional view of a semiconductor device of the present invention and the layout thereof is the same as that of FIG.
본 발명의 반도체소자 제조방법은 제 1 도(a)와 같이 기판(1)상에 활성영역을 정의하여 필드영역에 선택적으로 필드산화막(2)을 형성한다.In the semiconductor device manufacturing method of the present invention, as shown in FIG. 1A, an active region is defined on a substrate 1 to selectively form a field oxide film 2 in a field region.
그리고 제 2 도에 나타낸 바와 같이 게이트(3)와 캡산화막(4)을 증착하고 식각하여일정방향으로 일정간격을 갖는 워드라인(W/L)을 형성한 후, 워드라인을 마스크로 이용하여 활성영역에 불순물 이온주입으로 소오스 및 드레인영역을 형성한다. 그리고 전면에 산화막을 증착하고 에치백(Etch Back)하여 워드라인 측벽에 측벽산화막(5)을 형성한 다음, 전면에 더미 폴리실리콘(6)을 평탄하게 형성한다.As shown in FIG. 2, the gate 3 and the cap oxide film 4 are deposited and etched to form word lines (W / L) having a predetermined interval in a predetermined direction, and then active using the word lines as a mask. Source and drain regions are formed by implanting impurity ions into the regions. Then, an oxide film is deposited on the entire surface and etched back to form a sidewall oxide film 5 on the sidewall of the word line, and then the dummy polysilicon 6 is formed flat on the front surface.
이때, 게이트(3)와 캡산화막(4)사이에 산화막과 식각 선택비가 큰 물질로 에치스토퍼(Etch Stopper)를 형성하여 공정을 진행하여도 무방하다.In this case, an etching stopper may be formed between the gate 3 and the cap oxide layer 4 by using a material having a large etching rate and an etch selectivity.
제 1 도(b)와 같이 상기 더미 폴리실리콘(6)상에 산화막(7A)을 증착하고 제 1 도(c)와 같이 마스킹 및 에칭공정으로 비트라인 콘택영역의 더미 폴리실리콘(6)과 산화막(7A)의 일부를 제거하여 비트라인 콘택홀을 형성한다.FIG. 1 (b) and said dummy polysilicon (6) onto the oxide film (7 A) deposition, and FIG. 1 (c) and masking and etching process on the bit line contact area of the pile of polysilicon (6), such as A portion of the oxide film 7A is removed to form a bit line contact hole.
제 1 도(d)와 같이 전면에 산화막(7B)을 증착하고, 제 1 도(e)와 같이 상기 산화막(7B)을 에치백하여 비트라인 콘택홀 측벽에 산화막 측벽(7C)을 형성한다.FIG. 1 (d) an oxide film (7 B) the oxide film (7 B) the oxide film side walls (7 C) to the bit line contact hole side wall and etched back, such as vapor deposition, and FIG. 1 (e) in front, such as the Form.
그리고 제 1 도(f)와 같이 전면에 비트라인 폴리실리콘(8) 및 실리사이드(9)를 증착하고 비트라인을 정의하여 사진 식각 공정으로 실리사이드(9) 및 폴리실리콘(8)을 선택적으로 제거하여 비트라인(B/L)을 형성한다.Then, as shown in FIG. 1 (f), the bit line polysilicon 8 and the silicide 9 are deposited on the front surface, and the bit line is defined to selectively remove the silicide 9 and the polysilicon 8 by a photolithography process. The bit line B / L is formed.
이상에서 설명한 바와같은 본 발명의 반도체소자 제조방법은 비트라인의 두께를 줄이기 위하여 비트라인 콘택홀을 제외한 부분에 더미 폴리실리콘(6)을 채우고 절연막으로 절연시킨 후 비트라인을 형성하기 때문에 비트라인 에칭시 발생되는 비트라인 하부쪽의 폭이 줄어드는 현상을 방지할 수 있으며, 비트라인 아랫부분이 평탄하므로 이후 공정이 용이하게 이루어질 수 있다. 뿐만아니라 비트라인 두께가 감소하므로 인접한 비트라인간의 기생 커패시턴스를 감소시키는 등의 효과가 있다.As described above, the semiconductor device manufacturing method of the present invention fills the dummy polysilicon 6 in portions other than the bit line contact holes to reduce the thickness of the bit line, and insulates the insulating layer with an insulating film, thereby forming bit lines. When the width of the lower side of the bit line generated during the reduction can be prevented, and the lower part of the bit line is flat, the subsequent process can be easily performed. In addition, since the bit line thickness is reduced, there is an effect of reducing the parasitic capacitance between adjacent bit lines.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910016000A KR950000852B1 (en) | 1991-09-13 | 1991-09-13 | Fabricating method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910016000A KR950000852B1 (en) | 1991-09-13 | 1991-09-13 | Fabricating method of semiconductor device |
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| Publication Number | Publication Date |
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| KR930006827A KR930006827A (en) | 1993-04-22 |
| KR950000852B1 true KR950000852B1 (en) | 1995-02-02 |
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| KR1019910016000A KR950000852B1 (en) | 1991-09-13 | 1991-09-13 | Fabricating method of semiconductor device |
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| KR (1) | KR950000852B1 (en) |
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