Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/62—Fin field-effect transistors [FinFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0135—Manufacturing their gate conductors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Definitions

• the present invention relates generally to CMOS processing.
• CMOS complementary metal-oxide-semiconductor
• FinFETs Fin Field Effect Transistors
• MesaFETs structurally includes, among other things, a gate that extends over and along a portion of each sidewall of a thin, vertical, silicon "fin.”
• a spacer is required for blocking implants at the gate edge and preventing suicide shorts to the gate.
• Conventional planar CMOS spacer processing presents a number of problems relative to the fin. In particular, conventional processing to form the spacer for the gate results in application to the fin. If conventional spacer processes are used, fin erosion during spacer etch is a potential problem.
• any additional etching can prevent attainment of the desired fin size.
• Another challenge is formation of a spacer along the gate without formation on the fin sidewalls and the top of the fin such that the part the part of the fin not adjacent to the gate can be exposed to implantation.
• a spacer formed on the gate also forms on the sidewalls of the fin due to the three-dimensional nature of the FinFET. In some cases, such as during sidewall implantation or source drain extension, this sidewall spacer is undesirable. Attempts to remove the fin sidewall spacer result in removing the spacer on the gate where a spacer is needed. Similar problems exist relative to other CMOS devices such as MesaFETs.
• the invention relates to methods for forming a spacer for a first structure, such as a gate structure of a FinFET, and at most a portion of a second structure, such as a region of the fin adjacent to the gate, without detrimentally altering (e.g., eroding or forming a spacer thereon) the second structure.
• the methods generate a first structure (gate structure) having a top portion that overhangs a lower portion and a spacer under the overhang.
• the overhang may be removed after spacer processing.
• the overhang protects the first structure and may protect parts of the second structure if the first structure overlaps the second structure.
• FIG. 1 An example of this is a fin region adjacent and under the gate structure in a FinFET protected by a spacer, where the sidewalls of the fin are exposed to other processing such as selective silicon growth and implantation.
• the methods allow sizing of the second structure and construction of the first structure and spacer without detrimentally altering the second structure during spacer processing.
• the invention also relates to a FinFET including a gate structure and spacer formed by the methods.
• Figure 1 shows a perspective view of a precursor structure of a FinFET including a fin without a gate material.
• Figures 2-A-B show cross-sectional views of a first and second step of the methods.
• Figures 3A-B show cross-sectional views of a third step of the methods.
• Figures 4A-B show cross-sectional views of a fourth step according to a first embodiment of the methods.
• Figures 5A-B show cross-sectional views of a fourth step according to a second embodiment of the methods.
• Figures 6A-B show cross-sectional views of a fifth step of the methods.
• Figures 7A-B show cross-sectional views of a sixth step of the methods and the resulting gate structure and associated spacer.
• first structure such as a gate structure and an associated spacer without detrimentally altering a second structure
• the gate structure is the "first structure”
• the fin is the "second structure.”
• a spacer is formed' for the gate and on a portion of the fin adjacent the gate because the fin goes through the gate.
• the methods described can be used for any device in which it is desired to form a spacer for a first stiiicture and form a spacer for at most a portion
• the methods would enable formation of a spacer on one structure without forming a spacer on the other structure at all.
• the two structures may both be gates and a spacer may be desired on one of the gates but not at all on the other gate. Accordingly, the first and second structure terms may be applicable to a variety of different CMOS formations.
• FIG. 1 is a perspective view of a precursor structure 10 of a FinFET after gate etch.
• structure 10 includes a substrate 12 upon which is formed a fin 14 of mono-crystalline silicon.
• the gate structure (not shown) will eventually be constructed over fin 14.
• a hardmask 16 is also provided to protect fin 14 during processing.
• Hardmask 16 may be, for example, silicon dioxide (oxide) or silicon nitride.
• Actual processing to establish this precursor structure 10 may include deposition of a hardmask 16, etching hardmask 16 and the underlying silicon to generate fin 14, conducting a sacrificial oxidation and gate oxidation of the silicon to generate structure oxide 18.
• FIGS. 2-7 illustrate methods for forming a spacer for a gate and a spacer for at most a portion of a fin during the spacer processing.
• those figures labeled 'A' show a cross-sectional view A-A across fin 14 as shown in FIG. 1, and those labeled 'B' show a cross-sectional view B-B as shown in FIG. 1 (through the gate structure once formed).
• FIGS. 2A-B In a first step, shown in FIGS. 2A-B, a first material 20 for generation of a gate structure is deposited over fin 14.
• FIGS. 2A-B also show a second step in which a second material 22, 122 is formed over first material 20.
• second material 22, 122 includes the dual designation because the material may be provided in two different forms, as will be described in more detail below.
• second material 22, 122 is different than first material 20.
• FIGS. 3A-3B show the next step in which a gate structure 24 is formed in first material 20 and second material 22, 122.
• Forming may include applying and patterning (e.g., with lithography) a hardmask 26, e.g., oxide (TEOS), over first material and second material 22, 122, and etching the materials to form gate structure 24. As shown in FIG. 3B, these steps are also applied to eventual source and drain regions 28 of fin 14. Subsequently, hardmask 26 is removed in a known fashion.
• a hardmask 26 e.g., oxide
• FIGS. 4A-B and 5A-B illustrate two embodiments of the next step in which second material 22, 122 is made to overhang first material 20. As noted above, second material 22, 122 is different than first material 20.
• FIGS. 4A-B show a first embodiment in which second material 22 is formed
• second material 22 may be a portion of first material 20 that is implanted with a dopant in a known fashion.
• the dopant may be any material that causes polysilicon second material 22 to oxidize at a faster rate than non-doped polysilicon.
• the dopant may be, for example, Arsenic (As) (preferred), Germanium (Ge), Cesium (Cs), Argon (Ar) or Flourine (F) or a combination thereof.
• second material 22 that has a faster oxidation rate than first material 20 may be deposited on the first material, e.g., as polycrystalline silicon-germanium alloy.
• First material 20 may be, for example, non-doped polysilicon.
• second material 22 is made to overhang first material 20 by conducting an oxidation, e.g., at 800 to 950°C. The differential oxidation rate between materials generates a thicker oxide from second material 22 of gate structure 24 relative to fin 14 and first material 20. The result is generation of an overhang 40 of fin 14 adjacent to first material 20.
• FIGS. 4A-B show the resulting structure in which second material 22 forms a top portion 30 of gate structure 24 that overhangs an electrically conductive lower portion 32 thereof.
• the oxidation process may also cause thin oxide layers 34 (e.g., approximately ten times thinner than second material 22) to form on the sides of first material 20 (i.e., lower portion 32) and the sides of fin 14 outside of gate structure 24.
• Oxide layer 34 allows for preservation of fin 14 width without oxidizing the fin away.
• FIGS. 5A-B show a second, alternative embodiment for making second material 122 overhang first material 20.
• second material 122 is provided (in the step shown in FIGS. 2A-B) as any material having different thermal reflow properties than first material 20.
• first material 20 is provided as polysilicon or a metal such as cobalt-silicide or tungsten
• second material 122 is provided as a glass such as boro-phospho-silicate glass (BPSG) or phospho-silicate glass (PSG).
• the step of making second material 122 overhang first material 20 then includes conducting a thermal process to cause material 122 to reflow and form an overhang 140.
• the thermal process may include, for example, heating at least the second material at approximately 850°C for approximately ten minutes in a non-oxidizing ambient.
• FIGS. 5A-B show the resulting structure in which second material 122 forms a top portion 130 of a gate structure 124 that overhangs an electrically conductive lower portion 132 thereof.
• second materials 22, 122 may vary depending on the embodiment used and the specific processing provided. Accordingly, while the figures illustrate a bulbous or umbrella-like shape for materials 20, 22, 122, other shapes that provide the overhang may be possible.
• the next step includes forming a spacer under overhang 40, 140.
• the spacer may be formed on the structure of either embodiment above. However, FIGS. 6A-B and 7A- B show only the embodiment of FIGS. 4A-B for brevity sake.
• a spacer material 42 is conformally deposited, as shown in FIGS. 6A-B. Spacer material may be, for example, silicon nitride, silicon oxide or a combination thereof.
• spacer material 42 is etched using a directional reactive ion etching process which removes material everywhere except under overhang 40, 140 to form a spacer 44.
• Finishing processing may follow. This processing may include, for example, removal of oxide 34 from the sides of fin 14 (oxide remains as top portion 30 if doped polysilicon used) or removal of top portion 130, i.e., the glass, from gate structure 124 (if used).
• final processing may include, for example, implanting to set threshold voltage (Nt), doping the source/drain regions 28 of fin 14, selective silicon growth to widen the source/drain regions 28 on fin 14, removing remaining oxide and forming cobalt-silicide (CoSi), conventional contact processing, finishing with appropriate metal levels, etc.
• Nt threshold voltage
• CoSi cobalt-silicide
• the resulting FinFET 100 includes, among other things, a gate structure 24, 124 including an electrically conductive lower portion 32, 132 and an overhanging top portion 30, 130, a fin 14 extending through the lower portion, and a spacer 44 positioned under top portion 30, 130 of gate structure 24, 124 adjacent to conducting lower portion 32, 132.
• Top portion 30, 130 is made of a material (e.g., oxide or glass) that is different than the material (e.g., polysilicon) of lower portion 32, 132 as described above.
• "gate structure" 24, 124 has been described as including a top portion 30, 130 and a lower portion 32, 132.
• top portion 30, 130 may not ultimately form an operative or active part of the actual gate used. For instance, at least a part of top portion 30, 130 and/or overhang 40, 140 may be removed to allow for contacts to be made to lower portion 32, 132 of gate structure 24, 124.
• the invention is useful for forming a spacer for a gate of a FinFET, and at most a portion of a fin without detrimentally altering the fin.

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• 2002
  • 2002-12-19 AU AU2002364088A patent/AU2002364088A1/en not_active Abandoned
  • 2002-12-19 JP JP2004563141A patent/JP4410685B2/en not_active Expired - Fee Related
  • 2002-12-19 WO PCT/US2002/040869 patent/WO2004059727A1/en not_active Ceased
  • 2002-12-19 EP EP02798557A patent/EP1573804A4/en not_active Withdrawn
  • 2002-12-19 CN CNB028300432A patent/CN1320641C/en not_active Expired - Fee Related

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