AU2002364088A1 - Methods of forming structure and spacer and related finfet - Google Patents

Methods of forming structure and spacer and related finfet

Info

Publication number
AU2002364088A1
AU2002364088A1 AU2002364088A AU2002364088A AU2002364088A1 AU 2002364088 A1 AU2002364088 A1 AU 2002364088A1 AU 2002364088 A AU2002364088 A AU 2002364088A AU 2002364088 A AU2002364088 A AU 2002364088A AU 2002364088 A1 AU2002364088 A1 AU 2002364088A1
Authority
AU
Australia
Prior art keywords
finfet
spacer
methods
related
forming structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002364088A
Inventor
David M. Fried
Edward J. Nowak
Bethann Rainey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to PCT/US2002/040869 priority Critical patent/WO2004059727A1/en
Publication of AU2002364088A1 publication Critical patent/AU2002364088A1/en
Application status is Abandoned legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
AU2002364088A 2002-12-19 2002-12-19 Methods of forming structure and spacer and related finfet Abandoned AU2002364088A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2002/040869 WO2004059727A1 (en) 2002-12-19 2002-12-19 Methods of forming structure and spacer and related finfet

Publications (1)

Publication Number Publication Date
AU2002364088A1 true AU2002364088A1 (en) 2004-07-22

Family

ID=32679934

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002364088A Abandoned AU2002364088A1 (en) 2002-12-19 2002-12-19 Methods of forming structure and spacer and related finfet

Country Status (5)

Country Link
EP (1) EP1573804A4 (en)
JP (1) JP4410685B2 (en)
CN (1) CN1320641C (en)
AU (1) AU2002364088A1 (en)
WO (1) WO2004059727A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6951783B2 (en) * 2003-10-28 2005-10-04 Freescale Semiconductor, Inc. Confined spacers for double gate transistor semiconductor fabrication process
US7473593B2 (en) 2006-01-11 2009-01-06 International Business Machines Corporation Semiconductor transistors with expanded top portions of gates
US7341902B2 (en) 2006-04-21 2008-03-11 International Business Machines Corporation Finfet/trigate stress-memorization method
KR100838378B1 (en) 2006-09-29 2008-06-13 주식회사 하이닉스반도체 Method for fabricating fin transistor
KR100801315B1 (en) 2006-09-29 2008-02-05 주식회사 하이닉스반도체 Method of fabricating semiconductor device with the finfet transistor
US8889495B2 (en) * 2012-10-04 2014-11-18 International Business Machines Corporation Semiconductor alloy fin field effect transistor
KR102030329B1 (en) * 2013-05-30 2019-11-08 삼성전자 주식회사 Semiconductor device and method for fabricating the same
JP6604596B2 (en) * 2014-09-26 2019-11-13 インテル・コーポレーション Selective gate spacers for semiconductor devices.
US9564370B1 (en) 2015-10-20 2017-02-07 International Business Machines Corporation Effective device formation for advanced technology nodes with aggressive fin-pitch scaling

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3393286B2 (en) * 1995-09-08 2003-04-07 ソニー株式会社 Pattern forming method of
US5567639A (en) * 1996-01-04 1996-10-22 Utron Technology Inc. Method of forming a stack capacitor of fin structure for DRAM cell
DE19717363C2 (en) * 1997-04-24 2001-09-06 Siemens Ag Method of manufacturing a platinum metal structure by means of a lift-off process and use of the production process
JP3519589B2 (en) * 1997-12-24 2004-04-19 株式会社ルネサステクノロジ Manufacturing method of semiconductor integrated circuit
US5994192A (en) * 1998-05-29 1999-11-30 Vanguard International Semiconductor Corporation Compensation of the channel region critical dimension, after polycide gate, lightly doped source and drain oxidation procedure
DE10012112C2 (en) * 2000-03-13 2002-01-10 Infineon Technologies Ag Fin field effect transistor and method for fabricating a fin field effect transistor
US6562665B1 (en) * 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US6475890B1 (en) * 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US6475869B1 (en) * 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6492212B1 (en) * 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication

Also Published As

Publication number Publication date
WO2004059727A1 (en) 2004-07-15
JP4410685B2 (en) 2010-02-03
CN1320641C (en) 2007-06-06
CN1714441A (en) 2005-12-28
EP1573804A4 (en) 2006-03-08
EP1573804A1 (en) 2005-09-14
JP2006511092A (en) 2006-03-30

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase