DE102006062381B4 - EEPROM und Verfahren zum Betreiben und Herstellen desselben - Google Patents

EEPROM und Verfahren zum Betreiben und Herstellen desselben Download PDF

Info

Publication number
DE102006062381B4
DE102006062381B4 DE102006062381A DE102006062381A DE102006062381B4 DE 102006062381 B4 DE102006062381 B4 DE 102006062381B4 DE 102006062381 A DE102006062381 A DE 102006062381A DE 102006062381 A DE102006062381 A DE 102006062381A DE 102006062381 B4 DE102006062381 B4 DE 102006062381B4
Authority
DE
Germany
Prior art keywords
well
active
supplying
area
floating gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE102006062381A
Other languages
German (de)
English (en)
Other versions
DE102006062381A1 (de
Inventor
Geun-sook Suwon Park
Sang-Bae Yi
Soo-Cheol Lee
Ho-Ik Hwang
Tae-jung Yongin Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102006062381A1 publication Critical patent/DE102006062381A1/de
Application granted granted Critical
Publication of DE102006062381B4 publication Critical patent/DE102006062381B4/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
DE102006062381A 2005-12-22 2006-12-22 EEPROM und Verfahren zum Betreiben und Herstellen desselben Expired - Fee Related DE102006062381B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2005-0127770 2005-12-22
KR1020050127770A KR100660901B1 (ko) 2005-12-22 2005-12-22 단일 게이트 구조를 갖는 이이피롬, 상기 이이피롬의동작방법 및 상기 이이피롬의 제조방법

Publications (2)

Publication Number Publication Date
DE102006062381A1 DE102006062381A1 (de) 2007-08-09
DE102006062381B4 true DE102006062381B4 (de) 2009-10-22

Family

ID=37815403

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102006062381A Expired - Fee Related DE102006062381B4 (de) 2005-12-22 2006-12-22 EEPROM und Verfahren zum Betreiben und Herstellen desselben

Country Status (5)

Country Link
US (2) US7593261B2 (https=)
JP (1) JP5259081B2 (https=)
KR (1) KR100660901B1 (https=)
CN (1) CN101013701A (https=)
DE (1) DE102006062381B4 (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005002739B4 (de) 2005-01-20 2010-11-25 Infineon Technologies Ag Verfahren zum Herstellen eines Feldeffekttransistors, Tunnel-Feldeffekttransistor und integrierte Schaltungsanordnung mit mindestens einem Feldeffekttransistor
KR100660901B1 (ko) * 2005-12-22 2006-12-26 삼성전자주식회사 단일 게이트 구조를 갖는 이이피롬, 상기 이이피롬의동작방법 및 상기 이이피롬의 제조방법
US8472251B2 (en) * 2008-02-11 2013-06-25 Aplus Flash Technology, Inc. Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device
US7989875B2 (en) * 2008-11-24 2011-08-02 Nxp B.V. BiCMOS integration of multiple-times-programmable non-volatile memories
KR20100072979A (ko) * 2008-12-22 2010-07-01 주식회사 동부하이텍 싱글 게이트 구조의 반도체 메모리 소자
JP5467809B2 (ja) * 2009-07-16 2014-04-09 ルネサスエレクトロニクス株式会社 半導体装置
JP2011176163A (ja) * 2010-02-25 2011-09-08 Panasonic Corp 不揮発性半導体記憶装置
US8199578B2 (en) * 2010-06-03 2012-06-12 Ememory Technology Inc. Single polysilicon layer non-volatile memory and operating method thereof
KR101291750B1 (ko) 2011-10-14 2013-07-31 주식회사 동부하이텍 이이피롬과 그 제조 방법
JP5690873B2 (ja) * 2013-06-07 2015-03-25 イーメモリー テクノロジー インコーポレイテッド 消去可能プログラム可能単一ポリ不揮発性メモリ
US9450052B1 (en) * 2015-07-01 2016-09-20 Chengdu Monolithic Power Systems Co., Ltd. EEPROM memory cell with a coupler region and method of making the same
JP6954854B2 (ja) * 2017-03-31 2021-10-27 旭化成エレクトロニクス株式会社 不揮発性記憶素子および基準電圧生成回路
US10896979B2 (en) * 2017-09-28 2021-01-19 International Business Machines Corporation Compact vertical injection punch through floating gate analog memory and a manufacture thereof
US10685716B1 (en) * 2019-04-11 2020-06-16 Yield Microelectronics Corp. Method of fast erasing low-current EEPROM array
KR102950732B1 (ko) * 2021-02-22 2026-04-08 삼성전자주식회사 전압 레벨 쉬프터 셀 및 이를 포함하는 집적 회로
IT202100008075A1 (it) * 2021-03-31 2022-10-01 St Microelectronics Srl Memoria non volatile a singolo poly, porta flottante, programmabile poche volte e relativo metodo di polarizzazone
US11984165B2 (en) * 2022-05-24 2024-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device with reduced area

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5587945A (en) * 1995-11-06 1996-12-24 Advanced Micro Devices, Inc. CMOS EEPROM cell with tunneling window in the read path
US5615150A (en) * 1995-11-02 1997-03-25 Advanced Micro Devices, Inc. Control gate-addressed CMOS non-volatile cell that programs through gates of CMOS transistors
US5640346A (en) * 1992-03-03 1997-06-17 Harris Corporation Electrically programmable memory cell
US5646901A (en) * 1996-03-26 1997-07-08 Advanced Micro Devices, Inc. CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors
US5969992A (en) * 1998-12-21 1999-10-19 Vantis Corporation EEPROM cell using P-well for tunneling across a channel
US6326663B1 (en) * 1999-03-26 2001-12-04 Vantis Corporation Avalanche injection EEPROM memory cell with P-type control gate

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5523964A (en) * 1994-04-07 1996-06-04 Symetrix Corporation Ferroelectric non-volatile memory unit
JP2596695B2 (ja) * 1993-05-07 1997-04-02 インターナショナル・ビジネス・マシーンズ・コーポレイション Ｅｅｐｒｏｍ
US6005270A (en) * 1997-11-10 1999-12-21 Sony Corporation Semiconductor nonvolatile memory device and method of production of same
US5886920A (en) * 1997-12-01 1999-03-23 Motorola, Inc. Variable conducting element and method of programming
US6198652B1 (en) * 1998-04-13 2001-03-06 Kabushiki Kaisha Toshiba Non-volatile semiconductor integrated memory device
JP4212178B2 (ja) * 1999-03-12 2009-01-21 株式会社東芝 半導体集積回路の製造方法
JP3377762B2 (ja) * 1999-05-19 2003-02-17 株式会社半導体理工学研究センター 強誘電体不揮発性メモリ
JP2001085660A (ja) * 1999-09-10 2001-03-30 Toshiba Corp 固体撮像装置及びその制御方法
JP2001185633A (ja) * 1999-12-15 2001-07-06 Texas Instr Inc <Ti> Ｅｅｐｒｏｍデバイス
JP3762658B2 (ja) * 2001-05-17 2006-04-05 シャープ株式会社 不揮発性半導体記憶装置の駆動方法
JP4859292B2 (ja) * 2001-07-02 2012-01-25 富士通セミコンダクター株式会社 半導体集積回路装置およびｎａｎｄ型不揮発性半導体装置
JP2005353984A (ja) * 2004-06-14 2005-12-22 Seiko Epson Corp 不揮発性記憶装置
US7098499B2 (en) * 2004-08-16 2006-08-29 Chih-Hsin Wang Electrically alterable non-volatile memory cell
KR100660901B1 (ko) * 2005-12-22 2006-12-26 삼성전자주식회사 단일 게이트 구조를 갖는 이이피롬, 상기 이이피롬의동작방법 및 상기 이이피롬의 제조방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640346A (en) * 1992-03-03 1997-06-17 Harris Corporation Electrically programmable memory cell
US5615150A (en) * 1995-11-02 1997-03-25 Advanced Micro Devices, Inc. Control gate-addressed CMOS non-volatile cell that programs through gates of CMOS transistors
US5587945A (en) * 1995-11-06 1996-12-24 Advanced Micro Devices, Inc. CMOS EEPROM cell with tunneling window in the read path
US5646901A (en) * 1996-03-26 1997-07-08 Advanced Micro Devices, Inc. CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors
US5969992A (en) * 1998-12-21 1999-10-19 Vantis Corporation EEPROM cell using P-well for tunneling across a channel
US6326663B1 (en) * 1999-03-26 2001-12-04 Vantis Corporation Avalanche injection EEPROM memory cell with P-type control gate

Also Published As

Publication number Publication date
JP5259081B2 (ja) 2013-08-07
KR100660901B1 (ko) 2006-12-26
CN101013701A (zh) 2007-08-08
US8050091B2 (en) 2011-11-01
JP2007173834A (ja) 2007-07-05
DE102006062381A1 (de) 2007-08-09
US7593261B2 (en) 2009-09-22
US20070145459A1 (en) 2007-06-28
US20090310427A1 (en) 2009-12-17

Similar Documents

Publication Publication Date Title
DE68924849T2 (de) Nichtflüchtiger halbleiterspeicher und verfahren zur herstellung.
DE102006062381B4 (de) EEPROM und Verfahren zum Betreiben und Herstellen desselben
DE69527388T2 (de) EEPROM-Zelle mit Isolationstransistor und Betriebs- und Herstellungsverfahren
DE4233790C2 (de) EEPROM, Verfahren zu dessen Herstellung und Verfahren zu dessen Betreiben
DE4219854C2 (de) Elektrisch löschbare und programmierbare Halbleiterspeichereinrichtung und ein Verfahren zur Herstellung derselben
DE69231356T2 (de) Nichtflüchtige Speicherzelle und Anordnungsarchitektur
DE69636178T2 (de) Verfahren zum Löschen einer Flash EEPROM Speicherzelle
EP0783180B1 (de) Elektrisch programmierbare Speicherzellenanordnung und Verfahren zu deren Herstellung
DE102005045863B4 (de) Nichtflüchtiges Speicherbauelement und Verfahren zu seiner Herstellung
DE4329304C2 (de) Flash-EEPROM und Herstellungsverfahren dafür
DE69618302T2 (de) Halbleiterspeicheranordnung und Verfahren zur Steuerung
DE68909350T2 (de) Hochintegrierte EPROM-Speicheranordnung mit einer quadratischen Gitterorganisation und mit einem verbesserten Kopplungsfaktor.
DE3203516A1 (de) Nicht fluechtige, elektrisch umprogrammierbare floating-gate-speicheranordnung
DE102006062403B4 (de) Integriertes Schaltkreisbauelement sowie Herstellungs- und Betriebsverfahren
DE19533709A1 (de) Nicht-flüchtige Halbleiterspeichervorrichtung und Herstellungsverfahren derselben
DE69305986T2 (de) Schaltungsstruktur für Speichermatrix und entsprechende Herstellungsverfahren
DE10324612B4 (de) Halbleiterspeicher mit Charge-Trapping-Speicherzellen und Virtual-Ground-Architektur
DE69732618T2 (de) Eine asymmetrische Zelle für eine Halbleiterspeichermatrix und deren Herstellungsmethode
DE19807010B4 (de) Verfahren zur Herstellung einer nichtflüchtigen Speichereinrichtung
DE19807009B4 (de) Verfahren zur Herstellung einer nichtflüchtigen Speichereinrichtung mit Programmierleitungen
DE102004047610B4 (de) Integrierte Speicher-Schaltungsanordnung mit Tunnel-Feldeffekttransistor als Ansteuertransistor
DE3002492A1 (de) Nicht selbstloeschende speichereinrichtung und verfahren zum betrieb dieser einrichtung
DE19748495C2 (de) EEPROM-Zellstruktur und Verfahren zum Programmieren bzw. Löschen ausgewählter EEPROM-Zellstrukturen sowie EEPROM-Zellenfeld
DE69329088T2 (de) Verfahren zum Herstellen einer AMG-EPROM mit schneller Zugriffszeit
DE10220922B4 (de) Flash-Speicherzelle, Anordnung von Flash-Speicherzellen und Verfahren zur Herstellung von Flash-Speicherzellen

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee