CN1992079A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN1992079A CN1992079A CNA2006101265772A CN200610126577A CN1992079A CN 1992079 A CN1992079 A CN 1992079A CN A2006101265772 A CNA2006101265772 A CN A2006101265772A CN 200610126577 A CN200610126577 A CN 200610126577A CN 1992079 A CN1992079 A CN 1992079A
- Authority
- CN
- China
- Prior art keywords
- mentioned
- amplifier
- signal
- read
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1027—Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
- G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
Abstract
Description
Claims (11)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP378490/2005 | 2005-12-28 | ||
JP2005378490A JP5400262B2 (ja) | 2005-12-28 | 2005-12-28 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1992079A true CN1992079A (zh) | 2007-07-04 |
Family
ID=38193534
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA2006101265772A Pending CN1992079A (zh) | 2005-12-28 | 2006-08-28 | 半导体器件 |
Country Status (5)
Country | Link |
---|---|
US (3) | US7304910B1 (zh) |
JP (1) | JP5400262B2 (zh) |
KR (1) | KR101247383B1 (zh) |
CN (1) | CN1992079A (zh) |
TW (1) | TW200725619A (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102637453A (zh) * | 2012-02-17 | 2012-08-15 | 北京时代全芯科技有限公司 | 一种包括串行输入输出接口的相变存储器 |
CN101770807B (zh) * | 2009-12-29 | 2013-03-27 | 中国科学院上海微系统与信息技术研究所 | 相变存储器的写优化电路及其写优化方法 |
CN104820197A (zh) * | 2015-05-01 | 2015-08-05 | 武汉中科波谱技术有限公司 | 一种用于核磁共振波谱仪或成像仪的前置放大系统 |
CN111627474A (zh) * | 2020-05-29 | 2020-09-04 | 西安紫光国芯半导体有限公司 | 传输数据总线驱动电路以及方法、电子设备 |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7352649B2 (en) * | 2005-07-21 | 2008-04-01 | Micron Technology, Inc. | High speed array pipeline architecture |
KR100656452B1 (ko) * | 2005-11-29 | 2006-12-11 | 주식회사 하이닉스반도체 | 프리차지 장치 |
JP5400262B2 (ja) * | 2005-12-28 | 2014-01-29 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
KR100846392B1 (ko) * | 2006-08-31 | 2008-07-15 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
JP5228332B2 (ja) * | 2007-02-14 | 2013-07-03 | 富士通株式会社 | 半導体集積回路 |
US7613057B2 (en) * | 2007-04-03 | 2009-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuit and method for a sense amplifier |
KR101311455B1 (ko) * | 2007-08-31 | 2013-09-25 | 삼성전자주식회사 | 반도체 메모리 장치 및 배치 방법 |
KR100897280B1 (ko) * | 2007-09-04 | 2009-05-14 | 주식회사 하이닉스반도체 | 리시버 회로 |
JP5190719B2 (ja) * | 2007-11-08 | 2013-04-24 | 日本電気株式会社 | Mramの読み出し方法 |
KR100900135B1 (ko) * | 2007-12-21 | 2009-06-01 | 주식회사 하이닉스반도체 | 상 변화 메모리 장치 |
JP5574570B2 (ja) * | 2008-02-12 | 2014-08-20 | ピーエスフォー ルクスコ エスエイアールエル | 伝送制御回路及びそれを備えた半導体記憶装置 |
US7924637B2 (en) * | 2008-03-31 | 2011-04-12 | Advanced Micro Devices, Inc. | Method for training dynamic random access memory (DRAM) controller timing delays |
US7961533B2 (en) * | 2008-05-27 | 2011-06-14 | Advanced Micro Devices, Inc. | Method and apparatus for implementing write levelization in memory subsystems |
KR20100091640A (ko) * | 2009-02-11 | 2010-08-19 | 삼성전자주식회사 | 메모리 장치, 이를 포함하는 메모리 시스템, 및 이들의 데이터 처리 방법 |
JP2010257552A (ja) * | 2009-04-28 | 2010-11-11 | Elpida Memory Inc | 半導体記憶装置 |
KR101096261B1 (ko) * | 2009-11-30 | 2011-12-22 | 주식회사 하이닉스반도체 | 내부커맨드생성회로 |
TWI511159B (zh) * | 2009-12-21 | 2015-12-01 | Advanced Risc Mach Ltd | 預充電記憶體裝置中資料線之所需峰值電流的降低 |
JP2011170918A (ja) * | 2010-02-18 | 2011-09-01 | Elpida Memory Inc | 半導体記憶装置 |
US8675420B2 (en) * | 2011-05-26 | 2014-03-18 | Micron Technology, Inc. | Devices and systems including enabling circuits |
US8681576B2 (en) * | 2011-05-31 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pre-charge and equalization devices |
WO2013015893A1 (en) | 2011-07-27 | 2013-01-31 | Rambus Inc. | Memory with deferred fractional row activation |
JP2013205872A (ja) * | 2012-03-27 | 2013-10-07 | Sony Corp | 記憶制御装置、記憶装置、情報処理システム、および、それらにおける処理方法 |
JP5976392B2 (ja) | 2012-05-16 | 2016-08-23 | ルネサスエレクトロニクス株式会社 | 半導体集積回路およびその動作方法 |
JP2014149884A (ja) * | 2013-01-31 | 2014-08-21 | Micron Technology Inc | 半導体装置 |
US9042198B2 (en) | 2013-03-21 | 2015-05-26 | Yutaka Shirai | Nonvolatile random access memory |
US9087579B1 (en) * | 2014-01-06 | 2015-07-21 | Qualcomm Incorporated | Sense amplifiers employing control circuitry for decoupling resistive memory sense inputs during state sensing to prevent current back injection, and related methods and systems |
US10762961B2 (en) | 2015-07-29 | 2020-09-01 | Nantero, Inc. | Resistive change element arrays using a reference line |
US9613685B1 (en) * | 2015-11-13 | 2017-04-04 | Texas Instruments Incorporated | Burst mode read controllable SRAM |
US9905276B2 (en) | 2015-12-21 | 2018-02-27 | Micron Technology, Inc. | Control of sensing components in association with performing operations |
KR20170097261A (ko) * | 2016-02-17 | 2017-08-28 | 에스케이하이닉스 주식회사 | 리페어 회로, 이를 이용하는 메모리 장치 및 이의 동작 방법 |
US9804793B2 (en) | 2016-03-04 | 2017-10-31 | Intel Corporation | Techniques for a write zero operation |
JP2018049672A (ja) | 2016-09-20 | 2018-03-29 | 東芝メモリ株式会社 | メモリシステムおよびプロセッサシステム |
GB2555481B (en) * | 2016-11-01 | 2019-07-17 | Evonetix Ltd | Resistance measurement |
US10249351B2 (en) | 2016-11-06 | 2019-04-02 | Intel Corporation | Memory device with flexible internal data write control circuitry |
KR20180058478A (ko) * | 2016-11-24 | 2018-06-01 | 에스케이하이닉스 주식회사 | 반도체 장치, 이를 포함하는 반도체 시스템 및 반도체 장치의 리드 및 라이트 동작 방법 |
US10490239B2 (en) | 2016-12-27 | 2019-11-26 | Intel Corporation | Programmable data pattern for repeated writes to memory |
US10326002B1 (en) | 2018-06-11 | 2019-06-18 | Globalfoundries Inc. | Self-aligned gate contact and cross-coupling contact formation |
US10922465B2 (en) * | 2018-09-27 | 2021-02-16 | Arm Limited | Multi-input logic circuitry |
US11114155B2 (en) * | 2019-01-24 | 2021-09-07 | Marvell Asia Pte, Ltd. | High-density high-bandwidth static random access memory (SRAM) with phase shifted sequential read |
CN110867203B (zh) * | 2019-11-19 | 2021-12-14 | 上海华力微电子有限公司 | 存储器读取速度调节电路 |
EP3971897A4 (en) * | 2020-06-19 | 2022-10-19 | Changxin Memory Technologies, Inc. | MEMORY AND SEMI-CONDUCTOR INTEGRATED CIRCUIT |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CH520444A (de) * | 1970-08-04 | 1972-03-15 | Bbc Brown Boveri & Cie | Differenzverstärker |
US4999519A (en) * | 1987-12-04 | 1991-03-12 | Hitachi Vlsi Engineering Corporation | Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier |
JP2527050B2 (ja) * | 1989-10-27 | 1996-08-21 | 日本電気株式会社 | 半導体メモリ用センスアンプ回路 |
JPH06168594A (ja) * | 1992-11-30 | 1994-06-14 | Fujitsu Ltd | 半導体記憶装置 |
JPH09198873A (ja) * | 1996-01-19 | 1997-07-31 | Sharp Corp | 半導体記憶装置 |
JPH1116361A (ja) * | 1997-06-27 | 1999-01-22 | Toshiba Corp | 半導体記憶装置 |
JP4684394B2 (ja) | 2000-07-05 | 2011-05-18 | エルピーダメモリ株式会社 | 半導体集積回路装置 |
JP2003115190A (ja) * | 2001-08-03 | 2003-04-18 | Fujitsu Ltd | 半導体メモリ |
US6690232B2 (en) * | 2001-09-27 | 2004-02-10 | Kabushiki Kaisha Toshiba | Variable gain amplifier |
KR100451762B1 (ko) * | 2001-11-05 | 2004-10-08 | 주식회사 하이닉스반도체 | 불휘발성 강유전체 메모리 장치 및 그 구동방법 |
JP2004014054A (ja) * | 2002-06-10 | 2004-01-15 | Renesas Technology Corp | 半導体集積回路装置 |
JP2004042821A (ja) | 2002-07-12 | 2004-02-12 | Toyota Central Res & Dev Lab Inc | 最大路面摩擦係数推定装置 |
JPWO2004042821A1 (ja) | 2002-11-08 | 2006-03-09 | 株式会社日立製作所 | 半導体記憶装置 |
JP4370507B2 (ja) * | 2003-11-27 | 2009-11-25 | エルピーダメモリ株式会社 | 半導体集積回路装置 |
KR100535047B1 (ko) * | 2004-04-20 | 2005-12-07 | 주식회사 하이닉스반도체 | 불휘발성 강유전체 메모리 장치 |
KR100783492B1 (ko) * | 2004-07-31 | 2007-12-11 | 인티그런트 테크놀로지즈(주) | 차동증폭회로 및 이를 포함한 믹서회로 |
JP5400262B2 (ja) * | 2005-12-28 | 2014-01-29 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
-
2005
- 2005-12-28 JP JP2005378490A patent/JP5400262B2/ja not_active Expired - Fee Related
-
2006
- 2006-08-08 TW TW095129069A patent/TW200725619A/zh unknown
- 2006-08-28 KR KR1020060081849A patent/KR101247383B1/ko not_active IP Right Cessation
- 2006-08-28 CN CNA2006101265772A patent/CN1992079A/zh active Pending
- 2006-08-28 US US11/467,793 patent/US7304910B1/en not_active Expired - Fee Related
-
2007
- 2007-10-25 US US11/924,353 patent/US7489588B2/en not_active Expired - Fee Related
-
2009
- 2009-01-04 US US12/348,306 patent/US20090116309A1/en not_active Abandoned
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101770807B (zh) * | 2009-12-29 | 2013-03-27 | 中国科学院上海微系统与信息技术研究所 | 相变存储器的写优化电路及其写优化方法 |
CN102637453A (zh) * | 2012-02-17 | 2012-08-15 | 北京时代全芯科技有限公司 | 一种包括串行输入输出接口的相变存储器 |
CN102637453B (zh) * | 2012-02-17 | 2015-05-06 | 北京时代全芯科技有限公司 | 一种包括串行输入输出接口的相变存储器 |
CN104820197A (zh) * | 2015-05-01 | 2015-08-05 | 武汉中科波谱技术有限公司 | 一种用于核磁共振波谱仪或成像仪的前置放大系统 |
CN111627474A (zh) * | 2020-05-29 | 2020-09-04 | 西安紫光国芯半导体有限公司 | 传输数据总线驱动电路以及方法、电子设备 |
CN111627474B (zh) * | 2020-05-29 | 2022-06-10 | 西安紫光国芯半导体有限公司 | 传输数据总线驱动电路以及方法、电子设备 |
Also Published As
Publication number | Publication date |
---|---|
JP5400262B2 (ja) | 2014-01-29 |
KR101247383B1 (ko) | 2013-03-25 |
US7304910B1 (en) | 2007-12-04 |
US7489588B2 (en) | 2009-02-10 |
KR20070070038A (ko) | 2007-07-03 |
JP2007179681A (ja) | 2007-07-12 |
US20070147160A1 (en) | 2007-06-28 |
TW200725619A (en) | 2007-07-01 |
US20090116309A1 (en) | 2009-05-07 |
US20080094922A1 (en) | 2008-04-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1992079A (zh) | 半导体器件 | |
TWI620189B (zh) | 適用於低外部電源供應電壓之電壓產生器 | |
CN1202530C (zh) | 在低电源电压下高速动作的静态型半导体存储装置 | |
CN1140903C (zh) | 半导体存储装置 | |
CN109935257B (zh) | 半导体器件 | |
JP2004253038A (ja) | 半導体記憶装置 | |
CN1677564A (zh) | 半导体存储器件 | |
CN1941166A (zh) | 半导体存储装置 | |
CN1695249A (zh) | 半导体存储装置 | |
JP2012104196A (ja) | 半導体装置 | |
JP2008016169A (ja) | 半導体メモリ素子及びその駆動方法 | |
US6525979B2 (en) | Semiconductor memory device and method for reading information of therefrom | |
US11270746B2 (en) | Word line driver circuitry, and associated methods, devices, and systems | |
CN1197087C (zh) | 同步型半导体存储器 | |
US8107308B2 (en) | Semiconductor memory device | |
US20100315888A1 (en) | Semiconductor device | |
JP2011154754A (ja) | 半導体記憶装置 | |
CN1595531A (zh) | 半导体器件 | |
JP3327250B2 (ja) | 半導体記憶装置 | |
JP4143287B2 (ja) | 半導体記憶装置とそのデータ読み出し制御方法 | |
US9076503B2 (en) | Semiconductor device | |
JPH11273346A (ja) | 半導体装置 | |
JP2010267304A (ja) | 半導体メモリおよびシステム | |
CN1156887A (zh) | 能适应高频系统时钟信号的同步半导体存储器 | |
KR100838364B1 (ko) | 반도체 메모리 장치의 감지증폭 인에이블 신호 생성회로 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: ELPIDA MEMORY INC. Free format text: FORMER OWNER: HITACHI,LTD. Effective date: 20100908 Free format text: FORMER OWNER: ELPIDA MEMORY INC. |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20100908 Address after: Tokyo, Japan, Japan Applicant after: Elpida Memory Inc. Address before: Tokyo, Japan, Japan Applicant before: Hitachi Ltd. Co-applicant before: Elpida Memory Inc. |
|
C12 | Rejection of a patent application after its publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20070704 |