TW200725619A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
TW200725619A
TW200725619A TW095129069A TW95129069A TW200725619A TW 200725619 A TW200725619 A TW 200725619A TW 095129069 A TW095129069 A TW 095129069A TW 95129069 A TW95129069 A TW 95129069A TW 200725619 A TW200725619 A TW 200725619A
Authority
TW
Taiwan
Prior art keywords
control circuit
current
read
current control
signals
Prior art date
Application number
TW095129069A
Other languages
English (en)
Inventor
Satoru Hanzawa
Tomonori Sekiguchi
Riichiro Takemura
Satoru Akiyama
Kazuhiko Kajigaya
Original Assignee
Hitachi Ltd
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Elpida Memory Inc filed Critical Hitachi Ltd
Publication of TW200725619A publication Critical patent/TW200725619A/zh

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1027Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4091Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4093Input/output [I/O] data interface arrangements, e.g. data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4094Bit-line management or control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048Data bus control circuits, e.g. precharging, presetting, equalising
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066Output synchronization
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069I/O lines read out arrangements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096Write circuits, e.g. I/O line write drivers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002Isolation gates, i.e. gates coupling bit lines to the sense amplifier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
TW095129069A 2005-12-28 2006-08-08 Semiconductor device TW200725619A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005378490A JP5400262B2 (ja) 2005-12-28 2005-12-28 半導体装置

Publications (1)

Publication Number Publication Date
TW200725619A true TW200725619A (en) 2007-07-01

Family

ID=38193534

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095129069A TW200725619A (en) 2005-12-28 2006-08-08 Semiconductor device

Country Status (5)

Country Link
US (3) US7304910B1 (zh)
JP (1) JP5400262B2 (zh)
KR (1) KR101247383B1 (zh)
CN (1) CN1992079A (zh)
TW (1) TW200725619A (zh)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7352649B2 (en) * 2005-07-21 2008-04-01 Micron Technology, Inc. High speed array pipeline architecture
KR100656452B1 (ko) * 2005-11-29 2006-12-11 주식회사 하이닉스반도체 프리차지 장치
JP5400262B2 (ja) * 2005-12-28 2014-01-29 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
KR100846392B1 (ko) * 2006-08-31 2008-07-15 주식회사 하이닉스반도체 반도체 메모리 장치
JP5228332B2 (ja) * 2007-02-14 2013-07-03 富士通株式会社 半導体集積回路
US7613057B2 (en) * 2007-04-03 2009-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit and method for a sense amplifier
KR101311455B1 (ko) * 2007-08-31 2013-09-25 삼성전자주식회사 반도체 메모리 장치 및 배치 방법
KR100897280B1 (ko) * 2007-09-04 2009-05-14 주식회사 하이닉스반도체 리시버 회로
US8284595B2 (en) * 2007-11-08 2012-10-09 Nec Corporation Magnetic random access memory and operating method of the same
KR100900135B1 (ko) * 2007-12-21 2009-06-01 주식회사 하이닉스반도체 상 변화 메모리 장치
JP5574570B2 (ja) * 2008-02-12 2014-08-20 ピーエスフォー ルクスコ エスエイアールエル 伝送制御回路及びそれを備えた半導体記憶装置
US7924637B2 (en) * 2008-03-31 2011-04-12 Advanced Micro Devices, Inc. Method for training dynamic random access memory (DRAM) controller timing delays
US7961533B2 (en) * 2008-05-27 2011-06-14 Advanced Micro Devices, Inc. Method and apparatus for implementing write levelization in memory subsystems
KR20100091640A (ko) * 2009-02-11 2010-08-19 삼성전자주식회사 메모리 장치, 이를 포함하는 메모리 시스템, 및 이들의 데이터 처리 방법
JP2010257552A (ja) * 2009-04-28 2010-11-11 Elpida Memory Inc 半導体記憶装置
KR101096261B1 (ko) * 2009-11-30 2011-12-22 주식회사 하이닉스반도체 내부커맨드생성회로
TWI511159B (zh) * 2009-12-21 2015-12-01 Advanced Risc Mach Ltd 預充電記憶體裝置中資料線之所需峰值電流的降低
CN101770807B (zh) * 2009-12-29 2013-03-27 中国科学院上海微系统与信息技术研究所 相变存储器的写优化电路及其写优化方法
JP2011170918A (ja) * 2010-02-18 2011-09-01 Elpida Memory Inc 半導体記憶装置
US8675420B2 (en) * 2011-05-26 2014-03-18 Micron Technology, Inc. Devices and systems including enabling circuits
US8681576B2 (en) * 2011-05-31 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Pre-charge and equalization devices
US9330735B2 (en) * 2011-07-27 2016-05-03 Rambus Inc. Memory with deferred fractional row activation
CN102637453B (zh) * 2012-02-17 2015-05-06 北京时代全芯科技有限公司 一种包括串行输入输出接口的相变存储器
JP2013205872A (ja) * 2012-03-27 2013-10-07 Sony Corp 記憶制御装置、記憶装置、情報処理システム、および、それらにおける処理方法
JP5976392B2 (ja) 2012-05-16 2016-08-23 ルネサスエレクトロニクス株式会社 半導体集積回路およびその動作方法
JP2014149884A (ja) 2013-01-31 2014-08-21 Micron Technology Inc 半導体装置
US9042198B2 (en) 2013-03-21 2015-05-26 Yutaka Shirai Nonvolatile random access memory
US9087579B1 (en) 2014-01-06 2015-07-21 Qualcomm Incorporated Sense amplifiers employing control circuitry for decoupling resistive memory sense inputs during state sensing to prevent current back injection, and related methods and systems
CN104820197A (zh) * 2015-05-01 2015-08-05 武汉中科波谱技术有限公司 一种用于核磁共振波谱仪或成像仪的前置放大系统
US10762961B2 (en) 2015-07-29 2020-09-01 Nantero, Inc. Resistive change element arrays using a reference line
US9613685B1 (en) * 2015-11-13 2017-04-04 Texas Instruments Incorporated Burst mode read controllable SRAM
US9905276B2 (en) * 2015-12-21 2018-02-27 Micron Technology, Inc. Control of sensing components in association with performing operations
KR20170097261A (ko) * 2016-02-17 2017-08-28 에스케이하이닉스 주식회사 리페어 회로, 이를 이용하는 메모리 장치 및 이의 동작 방법
US9804793B2 (en) 2016-03-04 2017-10-31 Intel Corporation Techniques for a write zero operation
JP2018049672A (ja) 2016-09-20 2018-03-29 東芝メモリ株式会社 メモリシステムおよびプロセッサシステム
GB2555527B (en) * 2016-11-01 2019-06-05 Evonetix Ltd Current Control
US10249351B2 (en) 2016-11-06 2019-04-02 Intel Corporation Memory device with flexible internal data write control circuitry
KR20180058478A (ko) * 2016-11-24 2018-06-01 에스케이하이닉스 주식회사 반도체 장치, 이를 포함하는 반도체 시스템 및 반도체 장치의 리드 및 라이트 동작 방법
US10490239B2 (en) 2016-12-27 2019-11-26 Intel Corporation Programmable data pattern for repeated writes to memory
US10326002B1 (en) 2018-06-11 2019-06-18 Globalfoundries Inc. Self-aligned gate contact and cross-coupling contact formation
US10922465B2 (en) * 2018-09-27 2021-02-16 Arm Limited Multi-input logic circuitry
US11114155B2 (en) * 2019-01-24 2021-09-07 Marvell Asia Pte, Ltd. High-density high-bandwidth static random access memory (SRAM) with phase shifted sequential read
CN110867203B (zh) * 2019-11-19 2021-12-14 上海华力微电子有限公司 存储器读取速度调节电路
CN111627474B (zh) * 2020-05-29 2022-06-10 西安紫光国芯半导体有限公司 传输数据总线驱动电路以及方法、电子设备
EP3971897A4 (en) * 2020-06-19 2022-10-19 Changxin Memory Technologies, Inc. MEMORY AND SEMI-CONDUCTOR INTEGRATED CIRCUIT

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH520444A (de) * 1970-08-04 1972-03-15 Bbc Brown Boveri & Cie Differenzverstärker
US4999519A (en) * 1987-12-04 1991-03-12 Hitachi Vlsi Engineering Corporation Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier
JP2527050B2 (ja) * 1989-10-27 1996-08-21 日本電気株式会社 半導体メモリ用センスアンプ回路
JPH06168594A (ja) * 1992-11-30 1994-06-14 Fujitsu Ltd 半導体記憶装置
JPH09198873A (ja) * 1996-01-19 1997-07-31 Sharp Corp 半導体記憶装置
JPH1116361A (ja) * 1997-06-27 1999-01-22 Toshiba Corp 半導体記憶装置
JP4684394B2 (ja) 2000-07-05 2011-05-18 エルピーダメモリ株式会社 半導体集積回路装置
JP2003115190A (ja) * 2001-08-03 2003-04-18 Fujitsu Ltd 半導体メモリ
US6690232B2 (en) * 2001-09-27 2004-02-10 Kabushiki Kaisha Toshiba Variable gain amplifier
KR100451762B1 (ko) * 2001-11-05 2004-10-08 주식회사 하이닉스반도체 불휘발성 강유전체 메모리 장치 및 그 구동방법
JP2004014054A (ja) * 2002-06-10 2004-01-15 Renesas Technology Corp 半導体集積回路装置
JP2004042821A (ja) 2002-07-12 2004-02-12 Toyota Central Res & Dev Lab Inc 最大路面摩擦係数推定装置
JPWO2004042821A1 (ja) 2002-11-08 2006-03-09 株式会社日立製作所 半導体記憶装置
JP4370507B2 (ja) * 2003-11-27 2009-11-25 エルピーダメモリ株式会社 半導体集積回路装置
KR100535047B1 (ko) * 2004-04-20 2005-12-07 주식회사 하이닉스반도체 불휘발성 강유전체 메모리 장치
KR100783492B1 (ko) * 2004-07-31 2007-12-11 인티그런트 테크놀로지즈(주) 차동증폭회로 및 이를 포함한 믹서회로
JP5400262B2 (ja) * 2005-12-28 2014-01-29 ピーエスフォー ルクスコ エスエイアールエル 半導体装置

Also Published As

Publication number Publication date
US20090116309A1 (en) 2009-05-07
JP5400262B2 (ja) 2014-01-29
JP2007179681A (ja) 2007-07-12
CN1992079A (zh) 2007-07-04
KR101247383B1 (ko) 2013-03-25
US20070147160A1 (en) 2007-06-28
US7489588B2 (en) 2009-02-10
KR20070070038A (ko) 2007-07-03
US20080094922A1 (en) 2008-04-24
US7304910B1 (en) 2007-12-04

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