JP5574570B2 - 伝送制御回路及びそれを備えた半導体記憶装置 - Google Patents
伝送制御回路及びそれを備えた半導体記憶装置 Download PDFInfo
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- JP5574570B2 JP5574570B2 JP2008031103A JP2008031103A JP5574570B2 JP 5574570 B2 JP5574570 B2 JP 5574570B2 JP 2008031103 A JP2008031103 A JP 2008031103A JP 2008031103 A JP2008031103 A JP 2008031103A JP 5574570 B2 JP5574570 B2 JP 5574570B2
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- 230000005540 biological transmission Effects 0.000 title claims description 47
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000001514 detection method Methods 0.000 claims description 27
- 230000007704 transition Effects 0.000 claims description 19
- 230000004913 activation Effects 0.000 claims description 18
- 239000000872 buffer Substances 0.000 claims description 15
- 230000008054 signal transmission Effects 0.000 claims description 14
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 11
- 230000004044 response Effects 0.000 claims description 4
- 230000008439 repair process Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 13
- 230000008859 change Effects 0.000 description 9
- 230000007547 defect Effects 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0409—Online test
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Information Transfer Systems (AREA)
Description
本実施形態及びその変形例に示した構成は、本発明の伝送制御回路を適用可能な応用例であって、これ以外の構成において、所定の信号を信号バスに伝送させる際に出力タイミングを適切に制御する場合、広く本発明を適用することができる。
11…メインアンプ
12、13…ディレイ制御回路
14…バス制御部
15…レンテンシ制御部
16…DQ出力回路
20…データバス回路
21、31…ドライバ
22、32…出力バッファ
23…入力回路
30…レプリカ回路
33…レプリカ信号生成回路
34…検知回路
41…インバータ
42、44…トライステートインバータ
43、45…ラッチ回路
50…シュミットトリガインバータ
51、52、53…遅延素子
54…フリップフロップ
60…救済回路
61…YSプリデコーダ
62…レプリカ救済回路
63…検知回路
64…YS制御部
T1、T2…トランスファーゲート
Q1、Q2、Q3、Q4…MOSトランジスタ
G1、G10…NORゲート
G2、G11…NANDゲート
G12…EXORゲート
I10…インバータ
DB…データバス
RB…レプリカデータバス
SC…リード制御信号
YS…カラム選択信号
SM…メインアンプ起動信号
SB…出力制御信号
SF…フィードバック信号
D1…リードデータ
D2…レプリカデータ
Bs…信号バス
Br…レプリカ信号バス
S1…救済ヒット信号
S2…レプリカ救済ヒット信号
Claims (8)
- 第1の制御信号に同期して入力された所定の信号を信号バスに伝送させ、第2の制御信号に同期して出力する信号伝送回路と、
前記信号伝送回路に前記第2の制御信号を供給し、前記信号バスから前記所定の信号が出力される出力タイミングを制御する出力制御回路と、
前記第1の制御信号に基づく前記所定の信号の入力タイミングに連動してレベルが遷移するレプリカ信号を、前記信号バスと同一の伝送特性を有するレプリカ信号バスに伝送させて出力するレプリカ回路と、
前記レプリカ回路から出力された前記レプリカ信号におけるハイレベルとローレベルの遷移を検知し、検知結果を示すフィードバック信号を前記出力制御回路に供給する検知回路と、
を備え、前記出力制御回路の前記出力タイミングは、前記フィードバック信号において前記レプリカ信号の遷移が検知されるタイミングに応じて制御されることを特徴とする伝送制御回路。 - 前記第1の制御信号に基づき、前記所定の信号の入力タイミングに連動してレベルが遷移する前記レプリカ信号を生成し、生成された前記レプリカ信号を前記レプリカ回路に出力するレプリカ信号生成回路をさらに備えることを特徴とする請求項1に記載の伝送制御回路。
- 前記信号伝送回路は、入力された前記所定の信号により前記信号バスを駆動する駆動回路と、前記信号バスを伝送された前記所定の信号を保持して前記第2の制御信号に応じて出力する出力バッファとを含み、
前記レプリカ回路は、前記駆動回路及び前記出力バッファにそれぞれ対応する回路を含むことを特徴とする請求項1に記載の伝送制御回路。 - 前記検知回路は、前記レプリカ回路から出力された前記レプリカ信号が入力されるシュミットトリガインバータと、当該シュミットトリガインバータの出力レベルが反転するタイミングでパルスを発生する論理回路とを含むことを特徴とする請求項1に記載の伝送制御回路。
- 前記出力制御回路は、前記フィードバック信号によりリセットされるフリップフロップを含むことを特徴とする請求項1に記載の伝送制御回路。
- 請求項1に記載の伝送制御回路を備える半導体記憶装置。
- 前記所定の信号は、データを記憶するメモリアレイから読み出されたリードデータであることを特徴とする請求項6に記載の半導体記憶装置。
- 前記リードデータを増幅するメインアンプをさらに備え、前記第1の制御信号としてのメインアンプ起動信号に応じて、前記メインアンプが前記信号伝送回路に前記リードデータを出力することを特徴とする請求項7に記載の半導体記憶装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008031103A JP5574570B2 (ja) | 2008-02-12 | 2008-02-12 | 伝送制御回路及びそれを備えた半導体記憶装置 |
US12/367,986 US7869289B2 (en) | 2008-02-12 | 2009-02-09 | Semiconductor device having transmission control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2008031103A JP5574570B2 (ja) | 2008-02-12 | 2008-02-12 | 伝送制御回路及びそれを備えた半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
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JP2009193173A JP2009193173A (ja) | 2009-08-27 |
JP5574570B2 true JP5574570B2 (ja) | 2014-08-20 |
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JP2008031103A Expired - Fee Related JP5574570B2 (ja) | 2008-02-12 | 2008-02-12 | 伝送制御回路及びそれを備えた半導体記憶装置 |
Country Status (2)
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US (1) | US7869289B2 (ja) |
JP (1) | JP5574570B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20110001397A (ko) * | 2009-06-30 | 2011-01-06 | 삼성전자주식회사 | 전력 소모를 줄일 수 있는 반도체 메모리 장치 |
US10699755B2 (en) * | 2018-09-18 | 2020-06-30 | Micron Technology, Inc. | Apparatuses and methods for plate coupled sense amplifiers |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4443728B2 (ja) * | 2000-06-09 | 2010-03-31 | 株式会社ルネサステクノロジ | クロック発生回路 |
JP4446568B2 (ja) * | 2000-07-21 | 2010-04-07 | 富士通マイクロエレクトロニクス株式会社 | Pll周波数シンセサイザ回路 |
JP2003283318A (ja) * | 2002-03-25 | 2003-10-03 | Toshiba Corp | パワーオンリセット回路 |
JP3942537B2 (ja) * | 2002-12-06 | 2007-07-11 | エルピーダメモリ株式会社 | 半導体集積回路装置 |
JP4387250B2 (ja) | 2004-06-23 | 2009-12-16 | パナソニック株式会社 | 半導体記憶装置 |
JP4873182B2 (ja) * | 2005-02-03 | 2012-02-08 | 日本電気株式会社 | 半導体記憶装置及びその駆動方法 |
JP5400262B2 (ja) * | 2005-12-28 | 2014-01-29 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
JP4100455B1 (ja) * | 2007-01-22 | 2008-06-11 | オンキヨー株式会社 | パルス幅変調回路及びそれを用いたスイッチングアンプ |
JP5124019B2 (ja) * | 2008-06-09 | 2013-01-23 | 株式会社アドバンテスト | 試験装置 |
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2008
- 2008-02-12 JP JP2008031103A patent/JP5574570B2/ja not_active Expired - Fee Related
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2009
- 2009-02-09 US US12/367,986 patent/US7869289B2/en not_active Expired - Fee Related
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Publication number | Publication date |
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JP2009193173A (ja) | 2009-08-27 |
US7869289B2 (en) | 2011-01-11 |
US20090201754A1 (en) | 2009-08-13 |
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