CN1954439A - 在先进CMOS技术中应变Ge的集成 - Google Patents

在先进CMOS技术中应变Ge的集成 Download PDF

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CN1954439A
CN1954439A CNA2005800155904A CN200580015590A CN1954439A CN 1954439 A CN1954439 A CN 1954439A CN A2005800155904 A CNA2005800155904 A CN A2005800155904A CN 200580015590 A CN200580015590 A CN 200580015590A CN 1954439 A CN1954439 A CN 1954439A
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CN100481490C (zh
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尚慧玲
M·艾昂
J·O·舒
K·W·古亚里尼
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

本发明公开了一种在压缩应变Ge层(100)中制造PFET器件的结构和方法。该器件的制造方法与标准CMOS技术兼容，并且完全可升级。该方法包括选择性外延沉积Ge含量大于50％的缓冲层(101)、纯Ge层(100)和SiGe顶层(120)。制造的在压缩应变Ge层中寄宿的掩埋沟道PMOS器件相对于类似的Si器件显示出较好的器件特性。

Description

在先进CMOS技术中应变Ge的集成
技术领域
本发明涉及半导体技术，更具体地说，涉及在应变Ge中寄宿的PMOS器件。该器件以这种方式制造，其能够有效缩小并且集成到基于CMOS技术的高性能硅中。
背景技术
今天的集成电路包括大量的器件。较小的器件是增强性能和提高可靠性的关键。随着MOSFET(金属氧化物半导体场效应晶体管，名称的历史内涵通常意指隔离栅极场效应晶体管)器件正在缩小尺寸，技术变得越来越复杂，并且需要新的方法以保持器件从一代到下一代的期望性能增强。
潜在器件性能最重要的指示之一是载流子迁移率。在深亚微米代保持器件中的高载流子迁移率具有很大的困难。为了较好的载流子迁移率，一种有希望的途径是改进作为器件制造原材料的半导体。公知并近期还在研究的是，拉伸或压缩应变半导体具有引起兴趣的载流子特性。特别是，在应变硅(Si)沟道NMOS中获得电子迁移率90～95％的改进，详细描述见J.O.Chu的美国专利No.6,649,492 B2，题为“Strained Si Based LayerMade By UHV-CVD，and Device Therein”，这里通过参考引入其内容。类似的对于空穴增强，压缩应变掩埋锗(Ge)MODFET已经产生高空穴迁移率，详细描述见S.J.Koester等人的“Extremely high transconductanceGe/Si0.4Ge0.6 p-MODFET’s grown by UHV-CVD”，IEEE Elect.Dev.Lett.21，110(2000)。在相同晶片中结合拉伸和压缩应变SiGe区域，详细描述见J.O.Chu的PCT专利申请“Dual Strain-State SiGe Layer forMicroelectronics”，No.PCT/US2004/005481，于09/30/2004公开为WO2004084264。
由于增强的空穴迁移率，针对高性能CMOS逻辑电路，在基于Ge的MOSFET器件中具有更新技术的注意。特别是，采用氮氧化物(GeON)作为栅极绝缘体的表面沟道Ge MOSFET器件，已经被H.Shang等人论证，IEDM，p.441，2002。或者，采用高-K作为栅极绝缘体的Ge PMOS在以下文献中详细描述：C.Chui等人，IEDM，p.437，2002，C.H.Huang等人，VLSI symp.p.119，2003，还有A.Ritenour等人，IEDM，p.433，2003，以上三篇文献在这里通过参考引入其内容。
掩埋沟道应变Ge PMOS也已经报道具有空穴迁移率增强，详细描述见以下文献，M.Lee等人，IEDM，p.429 2003和H.Shang等人，VLSI symp.2004，两篇文献在这里通过参考引入其内容。虽然如此，报道的Ge器件使用简单器件结构，例如环型栅极结构布图来简化集成，并且通常具有相对大的尺寸。这样的特征不适合集成在先进高性能CMOS技术中。
为了在PMOS器件中结合应变Ge结构来增强空穴迁移率，与标准CMOS技术兼容的工艺不可获得。
发明内容
本发明描述了一种先进CMOS技术的集成方案，其结合了高迁移率应变Ge掩埋沟道结构，导致PMOS器件改进。该方案随着尺寸减小易于升级。
公开了一种叠层结构，包括SiGe籽晶层，其中SiGe籽晶层是单晶，并且Ge浓度大约在50％到90％之间，以及压缩应变Ge层，覆盖SiGe籽晶层，其中压缩应变Ge层是单晶，并且与SiGe籽晶层有外延关系。
还公开了一种CMOS电路，包括寄宿在压缩应变Ge层中的PMOS器件，其中压缩应变Ge层以外延关系覆盖SiGe籽晶层，其中SiGe籽晶层是单晶，并且Ge浓度大约在50％到90％之间。
还公开了一种制造PMOS器件的方法，包括以下步骤：在Ge浓度大约高达50％的驰豫SiGe层上外延沉积Ge浓度大约在50％到90％之间的单晶SiGe籽晶层；在SiGe籽晶层上外延沉积压缩应变Ge层；以及在压缩应变Ge层中寄宿所述PMOS器件。
还公开了一种制造CMOS电路的方法，包括以下步骤：提供SGOI晶片，具有Ge浓度大约高达50％的驰豫SiGe层；采用浅沟槽，或者其它，隔离技术在SGOI晶片上限定NMOS和PMOS区域；用介质材料覆盖所述NMOS区域；以选择性方式在驰豫SiGe层上外延沉积Ge浓度大约在50％到90％之间的单晶SiGe籽晶层；以选择性方式在SiGe籽晶层上外延沉积压缩应变Ge层；以及在压缩应变Ge层中寄宿PMOS器件。还公开了制造CMOS电路的方法还包括在压缩应变Ge层上选择性外延沉积SiGe顶层的步骤，其中SiGe顶层的Ge浓度选择为大约高达10％。
附图说明
通过下面的详细说明和附图本发明上述和其它特征将显而易见，其中：
图1示出了用于制造器件的叠层结构的示意截面图；
图2示出了隔离和NMOS和PMOS区域的示意顶视图；
图3示出了寄宿在压缩应变Ge层中的掩埋沟道PMOS器件的示意截面图；
图4示出了寄宿在压缩应变Ge层中的掩埋沟道PMOS器件的测量迁移率值的曲线图；
图5示出了寄宿在压缩应变Ge层中的掩埋沟道PMOS器件的测量跨导值的曲线图；以及
图6示出了寄宿在压缩应变Ge层中的掩埋沟道PMOS器件的测量导电性的曲线图。
具体实施方式
在先进CMOS技术中应变Ge的集成中，优选保持尽可能可行的主要Si CMOS的全部标准制造工艺。本发明在这种工艺中集成压缩应变Ge，在典型先进Si CMOS工艺的百余步骤上只改变/增加了很少步骤。在一个示例性实施例中，CMOS制造的全部工艺流程，包括应变Ge寄宿PMOS，将参照以下步骤：以绝缘体上硅(SOI)或绝缘体上硅锗(SGOI)晶片开始；通过标准浅沟槽隔离(STI)工艺，如本领域的技术人员所公知；用掩模覆盖NMOS区域；仅在PMOS区域中打开Si或SiGe岛；在暴露的Si或SiGe表面顶部选择性生长Ge；在NFET区域上剥离掩模覆盖；继续标准CMOS制造，如本领域的技术人员所公知。本发明还教导了CMOS制造工艺构架以外新颖的步骤和结构。
图1示出了用于制造器件的叠层结构的示意截面图。图2示出了隔离和NMOS和PMOS区域的示意顶视图。在代表性实施例中，开始点是SOI或SGOI晶片。衬底151，通常是Si，具有所谓的掩埋氧化物(BOX)150在其上覆盖，如本领域的技术人员所公知。在BOX顶部，具有驰豫单晶SiGe层130，典型Ge浓度大约高达50％，具有基本上是纯硅的可能性。开始的时候，驰豫SiGe是在BOX150顶部的覆盖层，但是图1示出了已经施加隔离介质140并且SiGe层130成为片断的工艺状态。在示例性实施例中的隔离是所谓的浅沟槽隔离(STI)，但是也可以是其它不同种类，如本领域的技术人员所公知。隔离140从用于NMOS器件220的区域分开或限定了用于PMOS器件210的区域。在本发明中引入的应变Ge层优选用于PMOS区域210中的PMOS器件。NMOS区域可能以本领域的技术人员所公知的方式处理，在驰豫SiGe130上具有材料层190。仅象征性示出在NMOS区域中的层或叠层190，因为层190在工艺的此状态中可能甚至不存在，或者可能从未使用。本发明采用在NFET区域和器件的工艺中本领域的技术人员所公知的的方法。在此状态中，如图所示，NMOS区域被掩模160覆盖。掩模160优选是介质，例如SiO2，或者氮化物，或者如本领域的技术人员所公知的其它物质。
引入多层用于Ge空穴传导型器件，例如PMOS，或者P-MODFET，开始于在驰豫SiGe层130上外延沉积Ge浓度大约在50％到90％之间的单晶SiGe籽晶层101。SiGe籽晶层101的外延生长优选以选择性方式进行，并且Ge浓度大约在70％左右。沉积选择性是相对于介质材料，例如STI介质140，或者NMOS掩模160。在SiGe籽晶层101中的Ge浓度没有必要均匀，可以依据特定实施例需要具有不同Ge浓度梯度。非均匀浓度通常用于提高材料质量。SiGe籽晶层101的优选厚度范围大约在0.3nm到3nm之间。SiGe籽晶层101的一些优先选择是提高SGOI晶片的驰豫SiGe 130的表面质量。SiGe籽晶层的相对高Ge浓度对于压缩应变器件质量Ge层100的引入是有利方面。
压缩应变单晶Ge层100在SiGe籽晶层101上外延沉积。压缩应变Ge层100的外延生长优选以选择性方式进行。沉积选择性是相对于介质材料，例如STI介质140，或者NMOS掩模160。压缩应变Ge层100的优选厚度范围大约在5nm到20nm之间。Ge层100是压缩应变的，因为Ge的驰豫晶格常数比SiGe的大，并且通过多层的外延关系促使Ge层100的晶格与下面的层一致，所有这些层的驰豫晶格常数都比Ge的小。压缩应变Ge层用来寄宿空穴传导型器件，例如PMOS。术语在特定材料或层中寄宿(host)器件，意味着器件的关键部分，即主要对载流子性质敏感的部分，举例来说，MOS器件的沟道，存在于特定材料或层中、由特定材料或层组成、或位于特定材料或层中。
如果需要表面沟道PMOS器件，材料沉积可以利用压缩应变Ge层100停止。为了具有掩埋沟道PMOS，也为了优选提高p-沟道的界面质量，外延沉积单晶SiGe顶层120，覆盖压缩应变Ge层100。SiGe顶层120的Ge浓度大约高达10％。在一个示例性实施例中，SiGe顶层基本上是纯硅，其中优选厚度大约在0.3nm到10nm之间。SiGe顶层120的外延生长优选以选择性方式进行。沉积选择性是相对于介质材料，例如STI介质140，或者NMOS掩模160。或者SiGe顶层120，或者压缩应变Ge层100是沉积的最后一层，这种叠层结构具有限定好的顶表面121。优选简单的是表面121与隔离介质的顶表面141共面的工艺。然而，缺乏这样的共面性并不是限制因素。
在PMOS区域的选择区域中局部形成或生长掩埋Ge沟道异质结构必需采用选择性CVD生长工艺，其中器件层的生长对于已知介质材料SiO2、Si3N4、SiON等具有选择性。典型的或可用的针对Si、SiGe或Ge薄膜的选择性生长工艺可以在不同的生长技术中找到，例如RT-CVD、UHV-CVD、LP-CVD、AP-CVD等，如本领域的技术人员所公知。在超高真空化学气相沉淀(UHV-CVD)的优选选择性生长工艺中，针对SiGe籽晶层101和压缩应变Ge层的生长温度范围是250～350℃。
关于针对生长外延层的UHV-CVD技术的详细介绍，参照S.Akbar等人的美国专利No.5,259,918“Heteroepitaxial Growth of Germanium onSilicon by UHV/CVD”，公开日11/09/1993，转让给这里的受让人并且通过参考引入其内容。更多关于UHV-CVD生长技术的讨论见J.O.Chu等人的美国专利No.US6,350,993 B1“High Speed Composite p-Channel Si/SiGeHeterostructure for Field Effect Devices”，公开日02/26/2003，转让给这里的受让人并且通过参考引入其内容。SiGe籽晶层101、压缩应变Ge层100和SiGe顶层120的叠层结构的外延沉积以超高真空完整性进行：在外延沉积之前约10-9Torr的范围内。特别是，使用热墙等温CVD设备，其中在进行优选生长工艺的选择温度和压力情况下，在少于1秒的停留时间期间，基板上没有硅和/或锗前体例如硅烷(SiH4)或锗烷(GeH4)源气体的均匀气相热解发生。通常，将一批预构图的SGOI晶片加载到UHV-CVD反应室中，然后在300℃到480℃的范围内加热。典型生长压力在1～5毫托的范围。在代表性实施例中，在SGOI区域上生长SiGe籽晶层101，采用SiH4 25 sccm和GeH4 95 sccm的流量组合。为了生长压缩应变Ge层100，降低生长温度接近300℃，然后GeH4以50 sccm的流量开始。层100完成后，生长温度升到较高，并且SiH4以30 sccm的流量开始和GeH4以0到15 secm的流量开始，以在压缩应变Ge层100上形成薄SiGe顶层120。在代表性实施例中，薄SiGe顶层120基本上是纯硅。
典型地，但不是必要地，如本领域的技术人员所公知，选择性CVD生长技术优选另外采用基于氯的前体或气体源，例如HCl、Cl2、SiCl4、SiHCl3、SiH2Cl2，以通过除去在标准掩模材料上的任何薄膜生长促使选择性生长。
图3示出了寄宿在压缩应变Ge层100中的掩埋沟道PMOS器件的示意截面图。在形成图1的叠层结构后，器件制造进行如本领域的技术人员所公知的步骤。在一刻，形成源极/漏极结380。如图所示的源极/漏极380向下延伸接触到BOX层150。这里仅是图解说明，在代表性实施例中，源极/漏极380可以或者没有向下达到BOX层界面150，或者可能甚至发生穿透进入BOX层150。在工艺中的另一刻，采用栅极绝缘体310。优选的栅极绝缘体包括但不限于典型地通过等离子体低温工艺形成的沉积氧化物，并且所谓的高-K(高介质)材料，例如HfO2、HfSiO，还有如本领域的技术人员所公知的其它材料。同样，大量不同种类的材料可以用于栅极390，如本领域的技术人员所公知。在器件更进一步制造中，例如在栅极绝缘体310工艺期间，可能，或者可能没有，从Si/SiGe顶层120消耗。例如，附图示出了层120的微小消耗。空穴在压缩应变Ge层100的顶表面301上的沟道中传导，其是与Si或SiGe顶层120的界面。这里形成沟道，由于众所周知的在Ge和Si之间的带隙对准。
图4示出了寄宿在压缩应变Ge层中的掩埋沟道PMOS器件的测量迁移率值作为反型电荷的函数的曲线图。在公开的器件中，最大空穴迁移率是Si通常空穴迁移率的六倍，在图中示出以作比较。
图5示出了寄宿在压缩应变Ge层中的掩埋沟道PMOS器件的测量跨导值的曲线图。显示的特性是具有沉积氧化物栅极绝缘体的器件。如图所示，公开的器件的跨导比起Si器件增强了两倍。
图6示出了寄宿在压缩应变Ge层中的掩埋沟道PMOS器件的测量导电性的曲线图。示出了具有高-K、具体是HfO2的栅极绝缘体的掩埋沟道PMOS的亚阈值和传导特性，用于低和高漏极电压。示出具有相同HfO2作为栅极绝缘体的Si控制器件，以作比较。s-Ge(应变-Ge)器件示出驱动电流大约两倍的增强。
根据上述教导，本发明的许多改进和变化是可能的，并且对于本领域的技术人员来说显而易见。本发明的范围将通过附加的权利要求限定。
x-SEM图像示出了只在SGOI顶部上选择性生长Ge层，    TEM图像示出了只在SGOI顶部上选择性生长Ge层，
没有发现在STI区域顶部上的Ge生长。                没有发现在STI区域顶部上的Ge生长。
低温SPA氧化物                                    低温SPA氧化物
栅极偏压(V)                                      栅极偏压(V)
在Si衬底和掩埋应变Ge衬底上具有低Dit的在500℃     在Si衬底和掩埋应变Ge衬底上具有低Dit的在
形成的低温SPA氧化物的C-V特性。该技术对于应变     500℃形成的低温SPA氧化物的I-V特性。在两个
Ge掩埋沟道高性能MOSFET的说明是关键的。           衬底上获得了可比较的泄漏特性。
                                             A2
Figure A20058001559000141
栅极电压VGS(V)
在选择性形成的应变-Ge掩埋沟道衬底和具有STI
隔离的Si控制上的PMOSFET的亚阈值特性。获得了
＞2X的驱动电流增强。较高截止电流大概与缺陷有关。
栅极偏压(V)
在应变Ge掩埋沟道PMOSFET上测量的线性驱动电流
和反型层电容，用于进行有效迁移率提取。
                                  DTSS测试图形，HfO2栅极氧化物
栅极电压VGG(V)
具有HfO2栅极介质的应变Ge掩埋沟道PMOSFET
的线性跨导特性。示出了具有相同HfO2的Si
控制器件用于比较。S-Ge示出了～2X的跨导增强。
A3

Claims (32)

1.一种叠层结构，包括：
SiGe籽晶层(101)，其中所述SiGe籽晶层是单晶，并且Ge浓度大约在50％到90％之间；以及
压缩应变Ge层(100)，覆盖所述SiGe籽晶层(101)，其中所述压缩应变Ge层是单晶，并且与所述SiGe籽晶层有外延关系。
2.根据权利要求1的叠层结构，其中所述压缩应变Ge层(100)的厚度大约在5nm到20nm之间。
3.根据权利要求1的叠层结构，其中所述SiGe籽晶层(101)的厚度大约在0.3nm到3nm之间。
4.根据权利要求3的叠层结构，其中在所述SiGe籽晶层(101)中的所述Ge有浓度梯度。
5.根据权利要求1的叠层结构，还包括在所述SiGe籽晶层(101)下面的驰豫SiGe层(130)，其中所述驰豫SiGe层是单晶，并且与所述SiGe籽晶层有外延关系，其中所述驰豫SiGe层的Ge浓度大约高达50％。
6.根据权利要求1的叠层结构，还包括覆盖所述压缩应变Ge层(100)的SiGe顶层(120)，其中所述SiGe顶层是单晶，并且与所述压缩应变Ge层有外延关系，其中所述SiGe顶层的Ge浓度大约高达10％。
7.根据权利要求6的叠层结构，其中所述SiGe顶层(120)基本上是纯硅，并且厚度大约在0.3nm到10nm之间。
8.根据权利要求1的叠层结构，其中所述叠层结构被介质(140)包围，其中所述介质为所述叠层结构提供隔离。
9.根据权利要求1的叠层结构，其中所述叠层结构和所述隔离介质(140)具有共面顶表面(121，141)。
10.根据权利要求1的叠层结构，还包括寄宿在所述压缩应变Ge层(100)中的空穴传导型器件。
11.根据权利要求10的叠层结构，其中所述空穴传导型器件是PMOS(210)器件。
12.根据权利要求11的叠层结构，其中所述PMOS(210)器件是掩埋沟道PMOS器件。
13.根据权利要求10的叠层结构，其中所述PMOS器件的栅极绝缘体(310)包括高K材料。
14.根据权利要求10的叠层结构，其中所述PMOS器件的栅极绝缘体(310)包括沉积氧化物。
15.一种CMOS电路，包括：
寄宿在压缩应变Ge层(100)中的PMOS(210)器件，其中所述压缩应变Ge层以外延关系覆盖SiGe籽晶层(101)，其中所述SiGe籽晶层是单晶，并且Ge浓度大约在50％到90％之间。
16.根据权利要求15的CMOS电路，其中所述压缩应变Ge层(100)被SiGe顶层(120)覆盖，其中所述SiGe顶层是单晶，并且与所述压缩应变Ge层有外延关系，其中所述SiGe顶层的Ge浓度大约高达10％，并且其中在所述SiGe籽晶层(101)下面具有驰豫SiGe层(130)，其中所述驰豫SiGe层是单晶，并且与所述SiGe籽晶层有外延关系，并且其中所述驰豫SiGe层的Ge浓度大约高达50％。
17.根据权利要求16的CMOS电路，其中所述SiGe顶层(120)基本上是纯硅，并且厚度大约在0.3nm到10nm之间。
18.根据权利要求16的CMOS电路，其中所述PMOS器件是掩埋沟道PMOS器件。
19.根据权利要求18的CMOS电路，其中所述PMOS器件具有栅极绝缘体(310)，并且所述栅极绝缘体包括高K材料。
20.根据权利要求18的CMOS电路，其中所述PMOS器件具有栅极绝缘体(310)，并且所述栅极绝缘体包括沉积氧化物。
21.一种制造PMOS器件的方法，包括以下步骤：
在Ge浓度大约高达50％的驰豫SiGe层(130)上外延沉积Ge浓度大约在50％到90％之间的单晶SiGe籽晶层(101)；
在所述SiGe籽晶层上外延沉积压缩应变Ge层(100)；以及
在所述压缩应变Ge层(100)中寄宿所述PMOS器件。
22.根据权利要求21的方法，其中所述SiGe籽晶层(101)的厚度选择为大约在0.3nm到3nm之间，并且所述压缩应变Ge层(100)的厚度选择为大约在5nm到20nm之间。
23.根据权利要求21的方法，还包括在所述压缩应变Ge层(100)上外延沉积SiGe顶层(120)的步骤，其中所述SiGe顶层的Ge浓度选择为大约高达10％。
24.根据权利要求23的方法，其中所述SiGe顶层(120)选择为基本上是纯硅，并且厚度大约在0.3nm到10nm之间。
25.根据权利要求21的方法，其中以对介质材料具有选择性的方式实施外延沉积所述SiGe籽晶层(101)和所述压缩应变Ge层(100)的步骤。
26.根据权利要求23的方法，其中以对介质材料具有选择性的方式实施外延沉积所述SiGe顶层(120)的步骤。
27.根据权利要求21的方法，还包括在所述PMOS器件的栅极绝缘体(310)中采用高K材料的步骤。
28.根据权利要求21的方法，还包括在所述PMOS器件的栅极绝缘体(310)中采用沉积氧化物的步骤。
29.一种制造CMOS电路的方法，包括以下步骤：
提供SGOI晶片(151，150，130)，具有Ge浓度大约高达50％的驰豫SiGe层(130)；
在所述SGOI晶片上限定NMOS(220)和PMOS(210)区域；
用介质材料(160)覆盖所述NMOS区域；
以选择性方式在所述驰豫SiGe层上外延沉积Ge浓度大约在50％到90％之间的单晶SiGe籽晶层(101)；
以选择性方式在所述SiGe籽晶层(101)上外延沉积压缩应变Ge层(100)；以及
在所述压缩应变Ge层(100)中寄宿所述PMOS器件。
30.根据权利要求29的方法，还包括以选择性方式在所述压缩应变Ge层(100)上外延沉积SiGe顶层(120)的步骤，其中所述SiGe顶层的Ge浓度选择为大约高达10％。
31.根据权利要求30的方法，其中所述SiGe顶层(120)选择为基本上是纯硅，并且厚度大约在0.3nm到10nm之间。
32.根据权利要求29的方法，还包括剥离覆盖所述NMOS区域的所述介质材料(160)，并且在所述NMOS区域中制造NMOS器件的步骤。
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