CN1893077A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN1893077A
CN1893077A CNA2006100985494A CN200610098549A CN1893077A CN 1893077 A CN1893077 A CN 1893077A CN A2006100985494 A CNA2006100985494 A CN A2006100985494A CN 200610098549 A CN200610098549 A CN 200610098549A CN 1893077 A CN1893077 A CN 1893077A
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China
Prior art keywords
projection
semiconductor device
exclusion area
semiconductor
district
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CNA2006100985494A
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CN100502001C (zh
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进藤昭则
田垣昌利
栗田秀昭
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

本发明提供可在凸起的下方设置半导体器件的高可靠性的半导体装置。该装置包括：半导体层(10)，具有器件形成区(10A)和设于该器件形成区(10A)周围的器件分离区(20)；形成于所述器件形成区(10A)内的器件(30)；设于所述半导体层(10)上面的层间绝缘层(60)；设于所述层间绝缘层(60)上面的电极垫(62)；钝化层(70)，具有位于所述电极垫(62)的上面的、使该电极垫(62)的至少一部分露出的开口(72)；凸起(80)，设于所述开口(72)处，平面形状为具有短边和长边的长方形，在俯视图上与所述器件(30)至少一部分重复，在所述半导体层(10)中，从所述凸起(80)的所述短边的垂直下方朝外侧及内侧的预定范围是器件禁止区(12)。

Description

半导体装置
技术领域
本发明涉及一种半导体装置。
背景技术
目前，当在焊盘(pad)的下方配置MOS晶体管等半导体器件时，由于受到焊接时的应力等影响，经常会破坏MOS晶体管等半导体器件的特性，并且，在半导体芯片(半导体基片)中，形成有焊盘形成部和半导体器件的区域在俯视图上是分开设置的。然而，随着近年来半导体芯片的微型化及高集成化，期望在焊盘及凸起的下方也能配置半导体器件。特开2002-319587号公报中披露了这种技术的一个例子。
专利文献1：特开2002-319587号公报
发明内容
本发明的目的在于提供一种可在凸起(hump)的下方设置半导体器件的高可靠性的半导体装置。
(1)本发明的半导体装置包括：半导体层，具有器件形成区和设于所述器件形成区周围的器件分离区；形成于所述器件形成区内的器件；设于所述半导体层上面的层间绝缘层；设于所述层间绝缘层上面的电极垫；钝化层，位于所述电极垫的上面，具有使所述电极垫的至少一部分露出的开口；以及凸起，设于所述开口处，平面形状为具有短边和长边的长方形，在俯视图上所述凸起与所述器件至少一部分重复，在所述半导体层中，从所述凸起的所述短边的垂直下方朝外侧及内侧的预定范围是器件禁止区。
在根据本发明的半导体装置中，包括具有器件形成区(ActiveRegion：活动区)和设于该器件形成区周围的器件分离区(IsolationRegion：绝缘区)的半导体层，位于凸起下方的半导体层是器件形成区，在从凸起的短边朝内侧及外侧的预定区域上设有器件禁止区。在从凸起的短边朝内侧及外侧的预定区域上容易施加有压力，从而容易产生应力。因此，配置于该器件禁止区上面的层间绝缘层处容易产生裂缝，例如，在将MOS晶体管等半导体器件设置于该区域时，这将成为使MOS晶体管的特性变差的主要原因。因此，在根据本发明的半导体装置中，通过将该预定的范围作为器件禁止区，从而上述问题能够得以避免。此外，还将位于凸起下方的半导体层作为器件形成区，将半导体器件配置在即使将半导体器件配置于凸起下也不会产生任何问题的位置上。简而言之，通过对半导体器件进行如下配置，从而可提供一种既小型、又能维持可靠性的半导体装置，即，在凸起的下方，不将半导体器件配置在会使其可靠性受损的位置，而将半导体器件积极配置在即便设置半导体器件也不会影响其可靠性的位置。
此外，本发明中提及的设于特定的A层(以下称作“A层”)上面的特定的B层(以下称作“B层”)既包括B层直接设置在A层上的情况，也包括B层隔着其他层设置在A层上的情况。
本发明的半导体装置还可采取下述的形式。
(2)在根据本发明的半导体装置中，所述器件禁止区可以是从所述凸起的所述短边的垂直下方朝外侧具有2.0μm至3.0μm距离的范围。
(3)在根据本发明的半导体装置中，所述器件禁止区可以是从所述凸起的所述短边的垂直下方朝内侧具有2.0μm至3.0μm距离的范围。
(4)根据本发明的半导体装置包括：半导体层，具有器件形成区和设于所述器件形成区周围的器件分离区；形成于所述器件形成区内的器件；设于所述半导体层上面的层间绝缘层；设于所述层间绝缘层上面的电极垫；钝化层，位于所述电极垫的上面，具有使所述电极垫的至少一部分露出的开口；凸起，设于所述开口处，在俯视图上所述凸起与所述器件至少一部分重复；以及引线，设于所述凸起上，在俯视图上与所述凸起的一边重叠，从所述凸起的所述一边的垂直下方、以及从与所述一边相对的另一边的垂直下方朝外侧及内侧的预定范围的所述半导体层是未设置所述器件形成区的器件禁止区。
根据本发明的半导体装置在凸起的垂直下方设置器件形成区，并将从凸起的垂直下方朝内侧及外侧具有一定距离的范围的半导体层作为器件禁止区。因此，具有与上述的发明相同的优点，通过在凸起的下方，不将半导体器件配置在会使其可靠性受损的位置上，而将半导体器件积极配置在即便设置半导体器件也不会影响其可靠性的位置上，从而可提供一种既小型、又能维持可靠性的半导体装置。
根据本发明的半导体装置还可采取下述的形式。
(5)在根据本发明的半导体装置中，所述器件禁止区可以是从所述凸起的所述一边和所述另一边的垂直下方朝外侧具有2.0μm至3.0μm距离的范围。
(6)在根据本发明的半导体装置中，所述器件禁止区可以是从所述凸起的所述一边和所述另一边的垂直下方朝内侧具有2.0μm至3.0μm距离的范围。
(7)根据本发明的半导体装置包括：半导体层，具有器件形成区和设于所述器件形成区周围的器件分离区；形成于所述器件形成区内的器件；设于所述半导体层上面的层间绝缘层；设于所述层间绝缘层上面的电极垫；钝化层，位于所述电极垫的上面，具有使所述电极垫的至少一部分露出的开口；以及凸起，设于所述开口处，在俯视图上所述凸起与所述器件重复，其中，在所述半导体层中，从所述凸起的端部的垂直下方朝外侧及内侧的预定范围是器件禁止区。
根据本发明的半导体装置在凸起的垂直下方设置器件形成区，并将从凸起的垂直下方朝内侧及外侧具有一定距离的范围的半导体层作为器件禁止区。因此，具有与上述的发明相同的优点，通过在凸起的下方，不将半导体器件配置在会使其可靠性受损的位置上，而将半导体器件积极配置在即便设置半导体器件也不会影响其可靠性的位置上，从而可提供一种既小型、又能维持可靠性的半导体装置。
(8)在根据本发明的半导体装置中，所述器件禁止区可以是从所述凸起的所述端部的垂直下方朝外侧具有2.0μm至3.0μm距离的范围。
(9)在根据本发明的半导体装置中，所述器件禁止区可以是从所述凸起的所述端部的垂直下方朝内侧具有2.0μm至3.0μm距离的范围。
(10)在根据本发明的半导体装置中，所述器件可以是晶体管。
(11)在根据本发明的半导体装置中，所述器件禁止区可以是低电压驱动晶体管的禁止区。
(12)在根据本发明的半导体装置中，在所述器件禁止区内可设置高压晶体管。
附图说明
图1是根据第一实施例的半导体装置的说明图。
图2是根据第一实施例的半导体装置的说明图。
图3是根据第一实施例的半导体装置的说明图。
图4是根据第二实施例的半导体装置的说明图。
图5是根据第一及第二实施例的半导体装置的说明图。
图6是根据第一及第二实施例的半导体装置的说明图。
具体实施方式
下面，参照附图，对本发明的一实施例进行说明。
1.第一实施例
图1是根据本实施例的半导体装置的示意性剖视图，图2是示意性表示本实施例的半导体装置中电极垫的形状和禁止区关系的俯视图。此外，图1的剖面是沿图2的X-X线的剖面。
如图1所示，根据本实施例的半导体装置包括半导体层10。作为半导体层10可以使用单结晶硅基板，该半导体层(SOI：Siliconon Insulator：绝缘硅)设置在绝缘层上，而且该半导体层是硅层、锗层、及硅锗层的基板。
在半导体层10上设有器件分离绝缘层20。可通过STI法、LOCOS法、以及半埋入式LOCOS法形成器件分离绝缘层20。图1中示出的是通过STI法形成的器件分离绝缘层20。这样，通过设置器件分离绝缘层20，划分出形成器件的器件形成区10A、以及器件禁止区12。如后所述，器件形成区10A是设于凸起80下方的区域。器件禁止区12是图1中的灰色区域，是半导体层10的从凸起80的端部向内侧及外侧具有预定范围的区域。后面将会对该区域进行详细描述。此外，在根据本实施例的半导体装置中，在器件禁止区12的外侧还设有器件形成区10B。
在器件形成区10A中，设置有未在补偿区设置绝缘层的低电压驱动MIS(Metal Insulator Semiconductor：金属绝缘半导体)晶体管30。此外，在器件形成区10B中，也与器件形成区10A中同样，设置MIS晶体管40。MIS晶体管30包括栅极绝缘层32、设于栅极绝缘层32上的栅电极34和设于半导体层10的杂质区36。杂质区36构成源极区或漏极区。MIS晶体管40是具有与MIS晶体管30相同的结构，包括栅极绝缘层42、栅电极44及杂质区46的低电压驱动晶体管，在MIS晶体管40中，未在补偿区设置绝缘层。如图3所示，本发明的器件形成区10A指的是在俯视图上被器件分离绝缘层20包围的区域(用斜线表示的区域)。器件形成区10B也是如此。
在MIS晶体管30、40的上面，依次设有为覆盖MIS晶体管30、40而设的层间绝缘层50、和层间绝缘层60。可使用公知的一般性材料形成层间绝缘层50和层间绝缘层60。在层间绝缘层50上设有具有预定图案的布线层52，通过接触层54将布线层52和MIS晶体管30的杂质区36电连接。
在层间绝缘层60上设有电极垫62。电极垫62通过接触层64而能与布线层52电连接。电极垫62可由铝或铜等金属形成。
如图1所示，根据本实施例的半导体装置还包括钝化层70。钝化层70上形成有使电极垫62的至少一部分露出的开口72。如图1及图2所示，开口72也可以形成为只使电极垫62的中央区域露出。即，钝化层70可以形成为覆盖电极垫62的外周边缘部。例如，钝化层可以由SiO2、SiN、聚酰亚胺树脂等形成。此外，在根据本实施例的半导体装置中，称作电极垫的时候，包含设有开口72的区域，而且是比布线部更宽的区域。
在本实施例涉及的半导体装置中，至少在开口72处设有凸起80。即，凸起80设置在电极垫62的露出面上。在本实施例涉及的半导体装置中，图示了凸起80一直形成至钝化层70上的情况。凸起80由一层或多层形成，且可以由金、镍、或铜等金属形成。此外，凸起80的外形并没有受特别的限制，矩形(包含正方形以及长方形)、或者圆形均可。而且，凸起80的外形也可以小于电极垫62。这时，凸起80也可以只形成在与电极垫62重叠的区域内。
此外，虽然未图示，但也可以在凸起80的最下层设置阻挡层。阻挡层用于防止电极垫62与凸起80两者的扩散。阻挡层可由一层或多层形成。例如，也可以通过溅射法形成阻挡层。甚至，阻挡层还可进一步具有提高电极垫62及凸起80的密接性的功能。阻挡层也可以包括钛钨(TiW)层。在阻挡层由多层构成的情况下，阻挡层的最上面的表面可以是使凸起80析出的电镀供电用的金属层(例如Au层)。
接着，对器件禁止区12进行说明。如上所述，器件禁止区12是半导体层10的位于凸起80端部的内侧及外侧的区域，是具有预定范围的区域。在该器件禁止区12中禁止配置器件形成区。
可将器件禁止区12的范围规定在从凸起80的端部向外侧(与开口72相反的一侧)具有2.0μm至3.0μm距离、以及向内侧(开口72侧)具有2.0μm至3.0μm距离的范围。这样规定器件禁止区12的范围的理由如下。
在形成凸起80的过程中，凸起80的端部附近会有应力产生。并且，在设置好凸起80后，由凸起80的内部应力引起的持续应力会施加在凸起80的端部附近。受到这些应力的影响，在层间绝缘层50、60上，从这些应力产生的位置产生裂缝。这种裂缝往往会一直形成至最下层的层间绝缘层，引起设于该区域的半导体器件的特性变动。例如，如果设置的是MIS晶体管，则会使栅极绝缘层劣化，导致漏电流产生(该问题将在第二实施例中进一步说明)。在根据本实施例的半导体装置中，为了避免这种问题，将凸起80的端部附近的范围作为禁止区12。
在根据本实施例的半导体装置中，位于凸起80下方的半导体层是器件形成区10A，从凸起80的端部朝外侧的预定区域上设有器件禁止区12。在从凸起80的端部朝外侧的预定区域上容易施加有压力，且容易产生应力。因此，配置于该器件禁止区12上面的层间绝缘层50、60处容易产生裂缝，例如，在将MIS晶体管等半导体器件设置于该区域时，这将成为使MIS晶体管的特性变差的要因。因此，在根据本实施例的半导体装置中，通过将该预定的范围作为器件禁止区12，从而上述问题能够得以避免。此外，还将位于凸起80下方的半导体层10作为器件形成区10A来配置半导体器件。简而言之，根据本实施例，通过对半导体器件进行如下配置，从而可提供一种既小型、又能维持可靠性的半导体装置，即，在凸起80的下方，不将半导体器件配置在会使其可靠性受损的位置上，而将半导体器件积极配置在即便设置半导体器件也不会影响其可靠性的位置。
而且，有时会将构成栅电极34的导电层作为用于与其它器件、例如MIS晶体管40连接的布线使用，用作该布线的导电层部分可在器件禁止区12内形成。
2.第二实施例
下面，参照图4，对本发明的第二实施例进行说明。图4是根据第二实施例的半导体装置的示意性剖视图。在根据第二实施例的半导体装置中，将半导体器件设于器件禁止区12这点与根据第一实施例的半导体装置不同。在以下的描述中，将围绕与根据第一实施例的半导体装置不同的点进行说明。
如图4所示，根据第二实施例的半导体装置包括：器件形成区10A和设于其周围的器件禁止区12。虽然图4中未进行图示，但是在根据本实施例的半导体装置中，与根据第一实施例的半导体装置同样，在器件禁止区12的外侧还形成有器件形成区10B。
在根据本实施例的半导体装置中，将高压MOS晶体管设于器件禁止区12。具体而言，设置具有LOCOS补偿结构的MOS晶体管100。MOS晶体管100包括：设于半导体层10中、用于缓和电场的补偿绝缘层22、设于半导体层10上的栅极绝缘层102、设于补偿绝缘层22的局部以及栅极绝缘层102上的栅电极104、和设于栅电极104外侧的半导体层中、构成源极区或漏极区的杂质区106。在补偿绝缘层22下设有补偿杂质区108，补偿杂质区108具有与杂质区106相同的导电型，且杂质浓度低。此外，虽然图4中示出的是补偿绝缘层22通过半埋入式LOCOS法形成的情况，但不限定于此，通过STI法或LOCOS法等形成均可。
在根据本实施例的半导体装置中，将MOS晶体管100的一部分构成要素设于器件禁止区12的半导体层10中。在MOS晶体管100中，栅电极104的端部设于补偿绝缘层22上。简而言之，在器件禁止区12内没有设置作为第一层的导电层的栅电极104的端部通过薄的绝缘层配置在半导体层10上这样的结构。在此，假设将具有设于器件区的结构的MIS晶体管30设置在器件禁止区12内，对这种情况下的问题点进行说明。MIS晶体管30与MOS晶体管100不同，具有栅电极34的端部设于半导体层10上的结构。因此，容易在栅电极34的端部所位于的半导体层10上产生应力。如同在第一实施例中所述，在器件禁止区12上面的层间绝缘层50、60处容易产生裂缝，从而引起膜的劣化。该影响可能波及到应力产生的栅电极34的端部，导致栅极绝缘层32的劣化。于是，可能引起漏泄电流流经MIS晶体管30。
但是，根据第二实施例涉及的半导体装置，由于在器件禁止区12中，将栅电极104的端部配置于补偿绝缘层22上，因而不会使半导体层10产生上述这样的应力，能够抑制栅极绝缘层102的劣化。因此，不仅设于凸起80下的器件形成区10A，而且具有预定结构的半导体器件也可以配置在器件禁止区12内，并且，能使半导体芯片进一步微型化。这使得由一张晶片获得的半导体芯片的个数增加，从而还能降低制造成本。
此外，虽然图4中示出了将MOS晶体管100设于器件禁止区12内的情况，但也不限定于此，也包括将MOS晶体管100的一部分构成设于器件禁止区12内的情况。这时，也可以是单侧补偿结构的MOS晶体管。
3.变形例
接着，参照图5，对根据第一实施例及第二实施例的半导体装置的变形例进行描述。本变形例的特征在于凸起80的平面形状为具有短边和长边的长方形形状这点，图5是凸起80、电极垫62、以及器件禁止区12间的位置关系的示意性俯视图。在下面的描述中，只对不同于根据第一实施例及第二实施例的半导体装置的点进行描述。
参照图1及图4，在根据本变形例的半导体装置中，凸起80设于电极垫62上的开口72处。开口72具有长方形形状，设于其上的凸起80也具有长方形形状。在本变形例中，器件禁止区12设于位于从凸起80的短边的端部向外侧、且从电极垫62的端部向内侧及外侧的半导体层10的预定区域上。根据该种方式，例如，在进行COF安装时，若设于薄膜上的连接线13(引线)的延伸方向是沿着凸起80的长边的方向时，具有如下的优点。凸起80处于在连接线的延伸方向上拉紧的状态，从而压力尤其施加在凸起80的短边侧上。因此，如上所述，尤其在位于凸起80的短边侧的凸起80的端部上容易引起在层间绝缘层50、60处产生裂缝这样的问题。在本变形例中，通过将器件禁止区12设于凸起80的短边侧，从而能够确实地防止将半导体器件设于使可靠性降低的位置。进而，由于在凸起80的长边下方的半导体层中没有设置器件禁止区12，因而能够将半导体器件设于凸起80的长边下方的半导体层中，从而可提供一种微型化的半导体装置。
尤其，如图6所示，在微型化的半导体芯片200中，要求开口72及凸起80的形状为长方形，且需设置数量较多的开口72。在本变形例中，通过在具有像这样的长方形形状的凸起80的半导体装置中，将器件禁止区12设置于适当的区域，从而可提供一种微型、且高可靠性的半导体装置。
此外，虽然在上述实施例中，图示了由两层层间绝缘层50、60构成，且在它们之间还设有一层布线层52的情况，但并不限定于此，具有层压大于等于三层的层间绝缘层，并根据层间绝缘层的层数设置多层布线层的结构也可。而且，虽然未在图1、图6中示出，但在MIS晶体管30、40、100中，可在栅电极34、44、104的侧面分别设置侧壁绝缘层。而且，还可在栅电极34、44、104以及杂质区36、46、106的上表面设置硅化物层。
此外，本发明并不限于上述实施方式，可有各种变形。例如，本发明包括与在实施方式中说明的结构实质上相同的结构(例如，作用，方法以及结果相同的结构，或者，目的以及结果相同的结构)。并且，本发明还包括调换实施方式中说明的结构中的非本质部分的结构。并且，本发明还包括取得与实施方式中说明的结构相同作用效果的结构，或者可以达到相同目的的结构。并且，本发明还包括在实施方式说明的结构中添加现有技术的结构。
附图标记说明
10半导体层                        10A、10B器件形成区
12器件禁止区                      13连接线(引线)
20器件分离绝缘层                  22补偿绝缘层
30、40MIS晶体管                   32、42栅极绝缘层
34、44栅电极                      36、46杂质区
50层间绝缘层                      52布线层
60层间绝缘层                      62电极垫
70钝化层                          72开口
80凸起                            100MIS晶体管
102栅极绝缘层                     104栅电极
106杂质区                         108补偿杂质区

Claims (12)

1.一种半导体装置，包括：
半导体层，具有器件形成区和设于所述器件形成区周围的器件分离区；
形成于所述器件形成区内的器件；
设于所述半导体层上面的层间绝缘层；
设于所述层间绝缘层上面的电极垫；
钝化层，位于所述电极垫的上面，具有使所述电极垫的至少一部分露出的开口；以及
凸起，设于所述开口处，其平面形状为具有短边和长边的长方形，在俯视图上所述凸起与所述器件至少一部分重复，
其中，在所述半导体层中，从所述凸起的所述短边的垂直下方朝外侧及内侧的预定范围是器件禁止区。
2.根据权利要求1所述的半导体装置，其中，
所述器件禁止区是从所述凸起的所述短边的垂直下方朝外侧具有2.0μm至3.0μm距离的范围。
3.根据权利要求1所述的半导体装置，其中，
所述器件禁止区是从所述凸起的所述短边的垂直下方朝内侧具有2.0μm至3.0μm距离的范围。
4.一种半导体装置，包括：
半导体层，具有器件形成区和设于所述器件形成区周围的器件分离区；
形成于所述器件形成区内的器件；
设于所述半导体层上面的层间绝缘层；
设于所述层间绝缘层上面的电极垫；
钝化层，位于所述电极垫的上面，具有使所述电极垫的至少一部分露出的开口；
凸起，设于所述开口处，在俯视图上所述凸起与所述器件至少一部分重复；以及
引线，设于所述凸起上，在俯视图上与所述凸起的一边重叠，
其中，从所述凸起的所述一边的垂直下方和从与所述一边相对的另一边的垂直下方朝外侧及内侧的预定范围的所述半导体层是未设置所述器件形成区的器件禁止区。
5.根据权利要求4所述的半导体装置，其中，
所述器件禁止区是从所述凸起的所述一边和所述另一边的垂直下方朝外侧具有2.0μm至3.0μm距离的范围。
6.根据权利要求4所述的半导体装置，其中，
所述器件禁止区是从所述凸起的所述一边和所述另一边的垂直下方朝内侧具有2.0μm至3.0μm距离的范围。
7.一种半导体装置，包括：
半导体层，具有器件形成区和设于所述器件形成区周围的器件分离区；
形成于所述器件形成区内的器件；
设于所述半导体层上面的层间绝缘层；
设于所述层间绝缘层上面的电极垫；
钝化层，位于所述电极垫的上面，具有使所述电极垫的至少一部分露出的开口；以及
凸起，设于所述开口处，在俯视图上所述凸起与所述器件重复，
其中，在所述半导体层中，从所述凸起的端部的垂直下方朝外侧及内侧的预定范围是器件禁止区。
8.根据权利要求7所述的半导体装置，其中，
所述器件禁止区是从所述凸起的所述端部的垂直下方朝外侧具有2.0μm至3.0μm距离的范围。
9.根据权利要求7所述的半导体装置，其中，
所述器件禁止区是从所述凸起的所述端部的垂直下方朝内侧具有2.0μm至3.0μm距离的范围。
10.根据权利要求1至9中任一项所述的半导体装置，其中，所述器件是晶体管。
11.根据权利要求1至9中任一项所述的半导体装置，其中，所述器件禁止区是低电压驱动晶体管的禁止区。
12.根据权利要求11所述的半导体装置，其中，在所述器件禁止区内设有高压晶体管。
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KR100859385B1 (ko) 2008-09-22
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CN100502001C (zh) 2009-06-17
US20070007662A1 (en) 2007-01-11
JP5234239B2 (ja) 2013-07-10
KR20070100219A (ko) 2007-10-10
US7777334B2 (en) 2010-08-17
US20080142905A1 (en) 2008-06-19
US20080142967A1 (en) 2008-06-19
US20080142906A1 (en) 2008-06-19
KR100813361B1 (ko) 2008-03-12

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