CN1707786A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN1707786A
CN1707786A CNA2005100742939A CN200510074293A CN1707786A CN 1707786 A CN1707786 A CN 1707786A CN A2005100742939 A CNA2005100742939 A CN A2005100742939A CN 200510074293 A CN200510074293 A CN 200510074293A CN 1707786 A CN1707786 A CN 1707786A
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electrode pad
projection
contact site
semiconductor device
passivating film
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汤泽健
汤泽秀树
高野道义
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

一种半导体装置,包括:形成了元件(12)的半导体部分;形成于半导体部分(10)上的绝缘层(20);形成于绝缘层上的电极焊盘(30);由在设置在绝缘层的接触孔内形成的导电材料构成,且用于与电极焊盘电连接的接触部(54);按照在电极焊盘的第一部分(32)上具有开口部(62),并且覆盖在第二部分(34)上的形式形成的钝化膜(60);按照大于钝化膜的开口部,且一部分覆盖到钝化膜上的形式形成的凸块(70);和介于在电极焊盘和凸块之间的阻挡层(64)。接触部在与凸块重叠的范围内避开电极焊盘的第一部分,而与第二部分连接。这样,可以提高电连接可靠性。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
为了缩小半导体芯片的平面面积,将成为外部电极的凸块重叠到多个元件(晶体管)的形成区域的技术已公开(参照特开9-283525号公报)。在元件的形成区域上,夹着绝缘层形成了布线层以及比布线层偏上方的电极焊盘。布线层和电极焊盘通过埋入绝缘层的接触部电连接。电极焊盘的一部分从钝化膜开口,在其开口部重叠了凸块的一部分。在电极焊盘和凸块之间,为防止两者的扩散,介入了阻挡层。
然而,在钝化膜的开口部内部,即使介入了阻挡层,也随其厚度和其他条件,而难以完全防止电极焊盘和凸块的扩散。在现有的结构中,接触部在钝化膜的开口部内与电极焊盘电连接,因此即使发生稍微的扩散,也会有接触部附近的电连接可靠性变差的现象。
阻挡层的膜厚通常为2000~5000左右,但若为了防止阻挡性能变差,加厚阻挡层的膜厚,则成本变高,因此希望在不加厚膜厚的前提下,提高阻挡性能。
发明内容
本发明的目的在于提高电连接可靠性。
(1)本发明的半导体装置,包括:形成了元件的半导体部分;形成于所述半导体部分上的绝缘层;形成于所述绝缘层上的电极焊盘;接触部,其由在设置在所述绝缘层的接触孔内形成的导电材料构成,且用于与所述电极焊盘电连接;钝化膜,其被形成为在所述电极焊盘的第一部分上具有开口部,并且覆盖在第二部分上;凸块,其被形成为大于所述钝化膜的所述开口部,且一部分覆盖到所述钝化膜上;和介于在所述电极焊盘和所述凸块之间的阻挡层;所述接触部在与所述凸块重叠的范围内避开所述电极焊盘的所述第一部分,而与所述第二部分连接。
根据本发明,接触部连接在电极焊盘的第二部分。在电极焊盘的第二部分和凸块之间介入钝化膜,因此第二部分要比从钝化膜露出的第一部分难以从凸块扩散。由此,可以防止因从凸块扩散造成的接触部附近的损坏。因此,能够提高电连接可靠性。
(2)在该半导体装置中,所述凸块也可以与所述半导体部分中的所述元件的形成区域重叠。
(3)在该半导体装置中,所述阻挡层的一部分按照覆盖到所述钝化膜上的形式形成,也可以在所述电极焊盘的所述第二部分和所述凸块之间介入了所述钝化膜和所述阻挡层。由此,在第二部分和凸块之间,不仅介入了钝化膜,还介入了阻挡层。因此,可以更有效地防止扩散。
(4)在该半导体装置中,还可以包括形成于所述半导体部分和所述电极焊盘之间的布线层,所述布线层与所述元件电连接,所述接触部介于所述布线层和所述电极焊盘之间。
(5)在该半导体装置中,也可以在所述电极焊盘的表面上在与所述接触部重叠的位置形成凹陷部。由此,接触部未与电极焊盘的第一部分连接,因此即使电极焊盘上的阻挡层随凹陷部而变薄,也因在凸块和电极焊盘之间形成了钝化膜,可以均匀防止电极焊盘和凸块两者的扩散。
(6)在该半导体装置中,也可以具有多个所述接触部,各个所述接触部以所述凸块的中心轴为基准对称排列。由此,通过安装工序等,可以均衡地分散通过凸块传递的机械应力。因此,可以防止因应力集中造成的接触部或电极焊盘等的损坏。
附图说明
图1为本发明的实施方式的半导体装置的俯视图。
图2为图1的II-II线剖面的局部放大图。
图3为本发明的实施方式的变形例的半导体装置的剖视图。
图4为表示本发明的实施方式的电路基板的图。
图5为表示本发明的实施方式的电子仪器的图。
图6为表示本发明的实施方式的电子仪器的图。
图中:10-半导体部分,12-元件,20-绝缘层,30-电极焊盘,32-第一部分,34-第二部分,40-布线层,54-接触部,60-钝化膜,62-开口部,64-阻挡层,70-凸块,72-中心轴,130-电极焊盘,132-第一部分,134-第二部分,136-凹陷部。
具体实施方式
下面参照附图对本发明的实施方式进行说明。
图1为本发明的实施方式的半导体装置的俯视图,图2为图1的II-II线剖面的局部放大图。
本实施方式的半导体装置可以为半导体芯片(裸芯片)(参照图1),也可以为切成多个半导体芯片之前的半导体晶片,还可以为CSP(Chip SizePackage:芯片尺寸封装)等封装形成的部件。
半导体装置1具有半导体部分(例如为半导体基板)10。半导体部分10的一部分或全部由半导体(例如为硅)构成。在半导体部分10形成了多个元件12。各元件12构成了晶体管(例如为MOS晶体管)。如图2所示,元件12包括:形成于半导体部分10的表层部的扩散区域(源极或漏极)14、和形成于半导体部分10上的电极(栅极)16。也可以在半导体部分10的表层部形成不同导电型的阱,在该阱内部形成扩散区域14。多个元件12的区域称作活性区域。并且,在半导体部分10中除了元件12的区域(非活性区域)形成了元件分离用的绝缘膜(例如通过LOCOS(LocalOxidation of Silicon:硅的局部氧化法)法等形成的氧化膜)18。
在半导体部分10上形成1层或多层绝缘层20(例如第一~第三绝缘层22、24、26)。绝缘层20也可由氧化膜(例如为氧化硅膜)形成。在绝缘层20的最表面上形成与元件12电连接的电极焊盘30。也可以在半导体部分10和电极焊盘30之间形成1层或多层布线层40(例如第一及第二布线层42、44)。布线层40与元件12电连接。布线层40或电极焊盘30也可以由例如铝或铜等金属形成。
在图2所示的例子中,在半导体部分10上形成第一绝缘层22,在第一绝缘层22上形成第一布线层42,通过接触部50将元件12(例如为扩散区域14)和第一布线层42电连接。进而,在第一布线层42上形成第二绝缘层24,在第二绝缘层24形成第二布线层44,通过接触部52将第一及第二布线层42、44电连接。进而,在第二布线层42上形成第三绝缘层(最上层的绝缘层)26,在第三绝缘层26上形成电极焊盘30,通过接触部54将第二布线层44和电极焊盘30电连接。就这样,通过使布线层成为多种结构,能够防止使平面区域扩大的布线迂回。
接触部50、52、54上下贯通绝缘层20的一部分或全部。接触部50、52、54也可以由金属等导电材料形成。接触部50、52、54的一部分或全部也可以由与布线层40或电极焊盘30相同的材料形成,也可以由不同的材料形成。作为接触部的形成方法,例如,通过旋转喷涂法、CVD(ChemicalVapor Deposition:化学气相沉积)法等形成绝缘层20,通过蚀刻法在绝缘层20上形成接触孔,在该接触孔内适用CVD法堆积成为接触部的导电材料。然后,还可以进行通过例如为CMP(Chemical Mechanical Polishing:化学机械研磨法)等使绝缘层的表面平坦化的工序,而后对电极焊盘30或布线层40进行溅射。在这种情况下,如图31所示,电极焊盘30或布线层40的表面随底层表面成为平坦的面。或者,也可在形成接触孔后的绝缘层20上将接触部和电极焊盘30(或为布线层40)溅射而形成一体。在这种情况下,也可以溅射后进行使电极焊盘30的表面平坦化的工序。
另外,布线层也可以如上所述地形成2层结构,还可以为1层结构或3层以上结构。或者,也可以省略上述布线层,通过(笔直延伸的)接触部54将元件12(扩散区域14)和电极焊盘30直接进行电连接。
在绝缘层20的最表面形成钝化膜60。钝化膜60按照在电极焊盘30的第一部分32(例如为中央部)上具有开口部62,并且覆盖到第二部分34(例如为连续围绕中央部的端部)的形式形成。例如,也可以按照在多个电极焊盘30的各中央部上配置任一个开口部62的形式,在钝化膜60上形成多个开口部62。电极焊盘30的第一部分32从钝化膜60的开口部62露出。电极焊盘30的第二部分34被钝化膜60覆盖。钝化膜60可由氧化膜、氮化膜或聚酰亚胺树脂等形成。
在电极焊盘30上形成阻挡层(凸块下金属化层)64。阻挡层64可由1层或多层形成。也可以通过溅射形成阻挡层64。阻挡层64为用于实现防止电极焊盘30和后述的凸块70两者的扩散。阻挡层64还可以具有提高电极焊盘30和凸块70的密封性的功能。阻挡层64也可以具有钛钨(TiW)层。当由多层构成时,阻挡层64的最表面也可以为析出凸块70的电镀供电用的金属层(例如为Au层)。
阻挡层64覆盖了全部从钝化膜60露出的电极焊盘30(第一部分32)。阻挡层64的一部分也可以按照覆盖到钝化膜60上的形式形成,即形成于电极焊盘30的第二部分34的上方。阻挡层64从电极焊盘30的第一部分32至第一部分34连续形成。如图2所示,阻挡层64也可以与电极焊盘30的第二部分34的一部分重叠,也可以与其全部重叠。阻挡层64也可以与连续围绕钝化膜60的开口部62的区域重叠。
在电极焊盘30(详细讲为阻挡层64)上形成凸块70。凸块70可由1层或多层,由金、镍或铜等金属形成。凸块70按照大于钝化膜60的开口部62,且一部分覆盖到钝化膜60的形式形成。换言之,凸块70覆盖钝化膜60的开口部62内的全部,还形成于电极焊盘30的第二部分34的上方。凸块70从电极焊盘30的第一部分32至第二部分34连续形成。如图2所示,凸块70也可以与电极焊盘30的第二部分34的一部分重叠,还可以与其全部重叠。如图1的局部放大图所示,凸块70也可以与连续围绕钝化膜60的开口部62的区域重叠。在电极焊盘30和凸块70之间介入了阻挡层64。
在本实施方式中,在将接触部54与凸块70重叠的范围内避开电极焊盘30的第一部分32后与第二部分34连接。接触部54介于布线层40(在图2中为第二布线层44)和电极焊盘30之间。接触部54和电极焊盘30的接触区域的全部配置在电极焊盘30的第二部分34。由此,在电极焊盘30的第二部分34和凸块70之间介入钝化膜60,因此第二部分34要比从钝化膜60露出的第一部分32难以从凸块70扩散。由此,可以防止因从凸块70扩散造成的接触部54附近的损坏。因此,能够提高电连接可靠性。进而,如图2所示,在电极焊盘30的第二部分34和凸块70之间不仅介入了钝化膜60还介入了阻挡层64时,可更有效地实现防止扩散。
凸块70(电极焊盘30)与半导体部分10中形成元件12的区域重叠。详细讲,凸块70(电极焊盘30)的一部分或全部与元件12的区域(活性区域)的一部分或全部重叠着。凸块70(电极焊盘30)也可以在半导体部分10的平面上以区域阵列(多行多列)排列配置。在本实施方式中,接触部54在与凸块70重叠的范围内与电极焊盘30连接,由于没有无用的布线迂回(例如迂回到外侧),所以可实现电特性的提高。
如图2所示,也可以设置多个连接在电极焊盘30的接触部54。并且,将多个接触部54的全部在与凸块70重叠的范围内避开电极焊盘30的第一部分后连接到第二部分34。例如,如图1所示,将多个接触部54按照从外侧围绕钝化膜60的开口部62(电极焊盘30的第一部分32)的形式排列。
也可以将多个接触部54分别以凸块70的中心轴(从凸块上面方向看时,通过凸块的中心并包含在平面的轴)72为基准对称地排列。详细讲,将某一个接触部54以凸块70的中心轴72为基准相对另一个接触部54对称配置。所谓凸块70的中心轴72为基准对称是指可以相对中心轴72的轴线形成线对称,也可以相对包含中心轴72的轴线的假想面形成面对称,还可以相对中心轴72的一个点形成点对称。由此,将多个接触部54对称地排列,因此可通过安装过程等,均衡地分散通过凸块70传递的机械应力。因此,可防止由应力集中造成的接触部54或电极焊盘30等的损坏。
此外,未连接在电极焊盘30上的其他接触部50、52也和接触部54一样,可以以凸块70的中心轴72为基准对称地排列。
另外,本实施方式的半导体装置的制造方法包括可由上述说明导出的内容,其他详细内容都可适用已知的方法制造。
图3为表示本实施方式的变形例的半导体装置的剖面的图。在本实施例中,在电极焊盘130的表面上与接触部54重叠的位置形成了凹陷部136。凹陷部136避开电极焊盘130中的第一部分132后形成于第二部分134。也可以在凹陷部136内面具有向开口方向扩展的锥角。该凹陷部也可以沿着设在绝缘层20(例如为第三绝缘层26)的接触孔的开口端部的锥形面(包括平面或曲面)形成。详细讲,也可以在绝缘层20(例如为第三绝缘层26)上按照在开口部设有锥角的形式形成接触孔,且通过溅射等在该接触孔及其周边区域使接触部54和电极焊盘130一体成膜。在这种情况下,省略上述的CMP等平坦化工序。
根据本变形例,接触部54未与电极焊盘130的第一部分132连接,因此即使第二部分134上的阻挡层64随凹陷部136而变薄,也因在凸块70和电极焊盘130之间具有钝化膜60,所以可以同样防止电极焊盘130和凸块70两者的扩散。另外,如图3所示,也可以在其他的接触部50、52形成凹陷部。本变形例的其他的详细内容包括可由上述说明导出的内容。
在图4中表示了安装了在上述实施方式中说明的半导体装置1的电路基板1000。作为具有上述的半导体装置1的电子仪器,在图5中表示了笔记本型的个人计算机2000,在图6中表示了移动电话3000。
本发明不限于上述地实施方式,可进行各种变形。例如,本发明包括实质上与实施方式中说明的构成相同的构成(例如为功能、方法及结果相同的构成,或目的及结果相同的构成)。并且,本发明包括置换了实施方式中说明的非本质部分的构成。例如,元件种类也不限于晶体管,包括扩散电阻、二极管、晶闸管、和电容等。例如,包括在电极焊盘下方没有元件而仅有布线的情况。并且,本发明包括起到在实施方式中说明的构成相同作用效果或达到相同目的的构成。并且,本发明包括在实施方式中说明的构成中附加公知技术的构成。

Claims (6)

1、一种半导体装置,其特征在于,包括:
形成了元件的半导体部分;
形成于所述半导体部分上的绝缘层;
形成于所述绝缘层上的电极焊盘;
接触部,其由在设置在所述绝缘层的接触孔内形成的导电材料构成,且用于与所述电极焊盘电连接;
钝化膜,其被形成为在所述电极焊盘的第一部分上具有开口部,并且覆盖在第二部分上;
凸块,其被形成为大于所述钝化膜的所述开口部,且一部分覆盖到所述钝化膜上;和
介于在所述电极焊盘和所述凸块之间的阻挡层;
所述接触部在与所述凸块重叠的范围内避开所述电极焊盘的所述第一部分,而与所述第二部分连接。
2、如权利要求1所述的半导体装置,其中,所述凸块与所述半导体部分中的所述元件的形成区域重叠。
3、如权利要求1或2所述的半导体装置,其中,所述阻挡层的一部分按照覆盖到所述钝化膜上的形式形成,在所述电极焊盘的所述第二部分和所述凸块之间介入了所述钝化膜和所述阻挡层。
4、如权利要求1~3中任一项所述的半导体装置,其中,
还包括形成于所述半导体部分和所述电极焊盘之间的布线层,
所述布线层与所述元件电连接,
所述接触部介于所述布线层和所述电极焊盘之间。
5、如权利要求1~4中任一项所述的半导体装置,其中,在所述电极焊盘的表面上在与所述接触部重叠的位置形成凹陷部。
6、如权利要求1~5中任一项所述的半导体装置,其中,具有多个所述接触部,各个所述接触部以所述凸块的中心轴为基准对称排列。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101866898A (zh) * 2009-04-15 2010-10-20 国际商业机器公司 用于c4球中均匀电流密度的金属布线结构
CN103119735A (zh) * 2010-09-24 2013-05-22 首尔半导体株式会社 晶片级发光二极管封装件及其制造方法
CN104253150A (zh) * 2013-06-26 2014-12-31 英飞凌科技股份有限公司 半导体器件及其制造方法
CN104952841A (zh) * 2014-03-27 2015-09-30 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN105006462A (zh) * 2009-06-18 2015-10-28 罗姆股份有限公司 半导体装置
WO2019228079A1 (zh) * 2018-05-29 2019-12-05 昇印光电(昆山)股份有限公司 导电膜及制备方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7271489B2 (en) 2003-10-15 2007-09-18 Megica Corporation Post passivation interconnection schemes on top of the IC chips
JP2005347623A (ja) * 2004-06-04 2005-12-15 Seiko Epson Corp 半導体装置の製造方法
JP2005347622A (ja) * 2004-06-04 2005-12-15 Seiko Epson Corp 半導体装置、回路基板及び電子機器
JP4606145B2 (ja) 2004-12-09 2011-01-05 セイコーエプソン株式会社 半導体装置及びその製造方法
JP4072697B2 (ja) 2006-05-02 2008-04-09 セイコーエプソン株式会社 半導体装置
US7808117B2 (en) * 2006-05-16 2010-10-05 Freescale Semiconductor, Inc. Integrated circuit having pads and input/output (I/O) cells
US20070267748A1 (en) * 2006-05-16 2007-11-22 Tran Tu-Anh N Integrated circuit having pads and input/output (i/o) cells
US7586132B2 (en) * 2007-06-06 2009-09-08 Micrel, Inc. Power FET with low on-resistance using merged metal layers
CN101630667A (zh) * 2008-07-15 2010-01-20 中芯国际集成电路制造(上海)有限公司 形成具有铜互连的导电凸块的方法和系统
US8581423B2 (en) * 2008-11-17 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Double solid metal pad with reduced area
GB2466313A (en) * 2008-12-22 2010-06-23 Cambridge Silicon Radio Ltd Radio Frequency CMOS Transistor
US20110121438A1 (en) 2009-11-23 2011-05-26 Xilinx, Inc. Extended under-bump metal layer for blocking alpha particles in a semiconductor device
TW201203403A (en) * 2010-07-12 2012-01-16 Siliconware Precision Industries Co Ltd Semiconductor element and fabrication method thereof
TWI493668B (zh) * 2011-05-23 2015-07-21 Via Tech Inc 接墊結構、線路載板及積體電路晶片
KR101916088B1 (ko) * 2012-04-02 2018-11-07 삼성전자주식회사 반도체 패키지
US9673125B2 (en) * 2012-10-30 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnection structure
KR102171197B1 (ko) * 2014-02-20 2020-10-28 삼성전자주식회사 버퍼 패턴을 갖는 범프 패드 구조체를 형성하는 방법
US10115703B2 (en) 2015-03-17 2018-10-30 Toshiba Memory Corporation Semiconductor device and manufacturing method thereof
CN109148401A (zh) * 2017-06-19 2019-01-04 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法、电子装置
TWI706139B (zh) * 2019-10-25 2020-10-01 巨擘科技股份有限公司 金屬探針結構及其製造方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6469035A (en) 1987-09-10 1989-03-15 Oki Electric Ind Co Ltd Connecting structure of bump electrode
JP2859288B2 (ja) * 1989-03-20 1999-02-17 株式会社日立製作所 半導体集積回路装置及びその製造方法
JPH09283525A (ja) 1996-04-17 1997-10-31 Sanyo Electric Co Ltd 半導体装置
JP3354424B2 (ja) * 1997-02-27 2002-12-09 三洋電機株式会社 半導体装置および半導体装置の製造方法
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US20020000665A1 (en) * 1999-04-05 2002-01-03 Alexander L. Barr Semiconductor device conductive bump and interconnect barrier
JP2001176966A (ja) 1999-12-20 2001-06-29 Matsushita Electronics Industry Corp 半導体装置
JP2001319928A (ja) * 2000-05-08 2001-11-16 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2004516682A (ja) * 2000-12-22 2004-06-03 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 集積回路デバイス
TW594993B (en) * 2001-02-16 2004-06-21 Sanyo Electric Co Semiconductor device and manufacturing process therefor
US6727593B2 (en) * 2001-03-01 2004-04-27 Kabushiki Kaisha Toshiba Semiconductor device with improved bonding
JP2002329722A (ja) * 2001-04-27 2002-11-15 Nec Corp 半導体装置及びその製造方法
JP2003017521A (ja) * 2001-06-28 2003-01-17 Sanyo Electric Co Ltd 半導体装置とその製造方法
US6689680B2 (en) * 2001-07-14 2004-02-10 Motorola, Inc. Semiconductor device and method of formation
JP2003037129A (ja) * 2001-07-25 2003-02-07 Rohm Co Ltd 半導体装置およびその製造方法
DE10159466A1 (de) * 2001-12-04 2003-06-12 Koninkl Philips Electronics Nv Anordnung mit Kondensator
JP2003209134A (ja) * 2002-01-11 2003-07-25 Hitachi Ltd 半導体装置及びその製造方法
JP3969295B2 (ja) * 2002-12-02 2007-09-05 セイコーエプソン株式会社 半導体装置及びその製造方法と回路基板及び電気光学装置、並びに電子機器
JP4724355B2 (ja) * 2003-03-31 2011-07-13 ルネサスエレクトロニクス株式会社 半導体装置
US7057296B2 (en) * 2003-10-29 2006-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding pad structure
US7208837B2 (en) * 2004-02-10 2007-04-24 United Microelectronics Corp. Semiconductor chip capable of implementing wire bonding over active circuits
US7061114B2 (en) * 2004-03-25 2006-06-13 Texas Instruments Incorporated Structure and method for contact pads having a protected bondable metal plug over copper-metallized integrated circuits
JP2005347623A (ja) * 2004-06-04 2005-12-15 Seiko Epson Corp 半導体装置の製造方法
JP2005347622A (ja) * 2004-06-04 2005-12-15 Seiko Epson Corp 半導体装置、回路基板及び電子機器

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US10163850B2 (en) 2009-06-18 2018-12-25 Rohm Co., Ltd. Semiconductor device
CN103119735A (zh) * 2010-09-24 2013-05-22 首尔半导体株式会社 晶片级发光二极管封装件及其制造方法
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CN105789235B (zh) * 2010-09-24 2019-05-03 首尔半导体株式会社 晶片级发光二极管封装件及其制造方法
CN104253150A (zh) * 2013-06-26 2014-12-31 英飞凌科技股份有限公司 半导体器件及其制造方法
CN104952841A (zh) * 2014-03-27 2015-09-30 台湾积体电路制造股份有限公司 半导体结构及其制造方法
WO2019228079A1 (zh) * 2018-05-29 2019-12-05 昇印光电(昆山)股份有限公司 导电膜及制备方法
US11443873B2 (en) 2018-05-29 2022-09-13 Shine Optoelectronics (Kunshan) Co., Ltd Conductive film and manufacturing method thereof

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US7560814B2 (en) 2009-07-14
US7230338B2 (en) 2007-06-12

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