CN1751357A - 具有可变刷新控制的存储器及其可变刷新控制方法 - Google Patents
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Abstract
存储器(10)具有存储器阵列(12)、电荷泵(18)、电压调节器(20)、刷新控制电路(16)和刷新计数器(22)。电荷泵(18)向存储器阵列(12)提供衬底偏压。电压调节器(20)提供泵浦使能信号,用于维持衬底偏压的电压水平在上、下限之内。刷新控制电路(16)控制刷新操作。刷新计数器(22)被连接以接收泵浦使能信号,并作为响应,向刷新控制电路(16)提供刷新定时信号以控制存储器阵列(12)的刷新速率。提供可编程保险丝电路(26)以利用该计数器(22)对刷新速率进行编程。可以在晶圆探查测试或板级老化期间对可编程保险丝电路(26)进行编程。可以包含内置自测试(BIST)电路(24)以便于测试。
Description
技术领域
本发明一般性地涉及集成电路存储器,尤其涉及具有可变刷新速率控制的动态随机访问存储器(DRAM)。
背景技术
动态随机访问存储器(DRAM)是众所周知的存储器类型,这种类型的存储器依靠电容器存储表示两种逻辑状态的电荷。一般来说,每个DRAM单元包含电容器和访问晶体管。存储在电容器上的电荷会随着时间的流逝产生泄漏,因此要求DRAM单元所存储的数据被周期性地读取和重写,或“刷新”。周期性的刷新操作需要消耗相当数量的功率。
电容器泄漏的电荷量很大程度上取决于温度和处理的变化。较高的温度引起的泄漏比相对较低的温度引起的泄漏更大。同样,处理变化能引起较大的泄漏。因此,对于具有固定刷新速率的DRAM,存储器单元必须以在最差情形的泄漏下保证可靠存储保持能力的速率进行刷新。对于电池供电的设备,重要的是使功耗尽可能地低。固定的刷新速率可能要求比电池供电的存储器的可靠操作所需要的功耗更高的功耗。
因此,需要一种具有可变速率刷新控制电路的DRAM,该电路精确地确定刷新速率,从而可靠地控制存储器的刷新操作,并在电池供电的应用场合降低存储器的功耗。
附图说明
通过下面结合以下附图对本发明优选实施例进行的详细描述,本领域的技术人员能够容易地明白本发明的前述、进一步和更具体的目的和优点:
图1以方框图的形式图解了根据本发明的集成电路存储器。
图2图解了根据本发明、在晶圆探针测试期间半导体晶圆的俯视图。
图3以流程图的形式图解了测试图1的集成电路存储器的方法。
具体实施方式
本发明一般性地提供一种存储器,它具有:为维持所存储的数据而需要周期性刷新的多个存储器单元,电荷泵,电压调节器,刷新控制电路和刷新计数器。电荷泵向多个存储器单元提供衬底偏压。电压调节器与电荷泵相连,且提供用于维持衬底偏压的电压水平在上、下限以内的泵浦使能信号。刷新控制电路控制多个存储器单元的刷新操作。刷新计数器被连接以接收泵浦使能信号,并作为响应,向刷新控制电路提供刷新定时信号,以控制多个存储器单元的刷新速率。通过刷新计数器响应电压调节器发出泵浦使能信号来调整刷新速率。
并且,提供一种可编程的保险丝电路对刷新速率进行编程。这种可编程的保险丝电路可以在晶圆探针测试期间进行编程。此外,内置自检测(BIST)电路可以包含在集成电路中以便于测试。
因为电荷泄漏以及FET(场效应晶体管)结泄漏随着温度的变化而变化,所以电压调节器将随着温度的增加而更加经常地启动电荷泵。因此,随着温度的增加,由电压调节器泵浦使能信号驱动的刷新计数器将增加存储器阵列的刷新速率。这提供这样一个优点:以温度范围上的最优刷新速率刷新存储器阵列。并且,这允许仅以针对特定温度提供可靠数据存储所需的频繁程度来进行刷新。与使用基于最差情形下的温度和处理变化的固定较高刷新速率的存储器相比,基于温度的可调较低刷新速率提供了较低的存储器功耗。并且,因为电荷泵和调节器已经在集成电路上存在,这里所公布的实施例的功耗将得到进一步的降低。
图1以方框图的形式图解了本发明的集成电路存储器10。集成电路存储器10包含存储器阵列12,控制器、译码器、传感放大器以及I/O电路模块14,刷新控制电路16,电荷泵18,电压调节器20,刷新计数器22,内置自检测(BIST)电路24。集成电路存储器10可以是“独立”(stand-alone)的存储器或嵌入型的存储器。存储器阵列12是在位线和字线交叉处相连的存储器单元的阵列。存储器单元可以被组织成多个存储器单元块。在所图解的实施例中,存储器单元是具有电容器和访问晶体管的普通动态随机访问存储器(DRAM)。电容器用于存储表示所存储的逻辑状态的电荷。访问晶体管用于当访问存储器单元时将电容器与位线相连来响应所选择的字线。在其它的实施例中,存储器阵列12可包含需要周期性刷新以维持所存储的逻辑状态的其它存储器单元类型。
模块14包含用于为读、写和刷新操作而访问存储器阵列12的电路,并且通过多根导线与存储器阵列12相连。集成电路存储器10在读、写操作期间的功能就象普通的DRAM功能一样。模块14包含行和列译码器,传感放大器,控制电路和I/O电路。模块14接收表示存储器中所使用的各种控制信号(例如写使能(WE)、传感使能(SE)等等)、标记为“控制”的控制信号。响应控制信号“控制”和标记为“地址”的地址信号,行和列译码器访问存储器阵列12的一个或多个存储器单元。在读操作期间,传感放大器检测和放大所选择位线上与所存储的逻辑状态相应的电压,并向I/O电路提供相应逻辑信号以进一步的放大和缓冲。I/O电路向存储器10之外的电路传送标记为“数据”的缓冲数据信号。在写操作期间,通过双向数据线“数据”向模块14提供输入数据信号。输入数据信号被提供到对应于地址信号“地址”的存储器位置。控制信号“控制”用于控制读和写周期。
刷新控制电路16控制和协调存储器阵列12的刷新操作。存储器阵列12和电路模块14中的刷新操作都是常规的,并且可自动进行,或通过来自模块14、标记为“RFSH CNTRL”的控制信号响应外部刷新请求而进行。刷新控制电路16也通过多根标记为“刷新控制”和多根标记为“刷新地址”的导线与电路模块14相连。此外,刷新控制电路16从刷新计数器22接收“刷新请求”信号,并从BIST电路24接收标记为“BIST刷新控制”的BIST刷新控制信号。
电荷泵18是常规电荷泵,用于向存储器阵列12提供标记为“VSUB”的衬底偏压。在其它的实施例中,电荷泵18可用于其它的目的。例如,电荷泵18可用于提供针对存储器阵列12的电容器的极板电压,或提升字线电压。根据应用,电荷泵18提供的电压可以是任何电压,通常大于提供给标记为“VDD”和“VSS”的电源电压终端的电源电压。通常,VDD接收正的电源电压,而VSS则处于地电位。在其它的实施例中,向VDD和VSS提供的电压可以不同。并且,在其它的实施例中,电荷泵18可以提供小于电源电压的提升电压,或负电压。
电压调节器20是常规电压调节器。电压调节器20具有被连接以接收衬底偏压VSUB的输入终端,和将控制信号ON/OFF提供给电荷泵18的控制输入端的输出终端。电压调节器20监视电压VSUB,并交替地发出和撤消ON/OFF信号以将衬底偏压VSUB维持在具有上、下限的预定电压范围之内。即,当发出ON/OFF信号时,电压VSUB增加,直到达到上限电压。然后电压调节器20撤消ON/OFF信号,电荷泵18停止提升电压,直到电压VSUB降至下限。这时,再一次发出ON/OFF信号,电荷泵18开始“泵浦(pumping)”,并且VSUB增加。在存储器10的正常操作期间,ON/OFF信号的发出和撤消或多或少是周期性的。此外,当存储器10的电压或温度提升时,电压调节器20将更加频繁地接通和关闭电荷泵18。
除控制电荷泵18之外,电压调节器20还用于控制本发明的存储器阵列12的刷新定时。即,由于存储器10温度和电压的变化而导致的电压调节器20的切换操作的变化,被用于通过刷新计数器22来改变存储器阵列12的刷新频率。刷新计数器22具有与电压调节器20相连、用于接收ON/OFF信号的时钟输入终端(CLK),和用于提供标记为“刷新请求”的刷新请求信号的输出终端。刷新计数器22用于将调节器的ON/OFF周期转换成刷新定时,从而利用ON/OFF周期的温度和电压变化来改变刷新速率。如上所述,温度和电压的变化影响存储器单元电容器的电荷泄漏。因此,随着存储器10的温度或电压的增加,存储器阵列需要的刷新速率将随之增加。随着模片温度的变化而导致的调节器20的ON/OFF输出的频率变化将第一位地追踪阵列单元的泄漏。这是因为:电压VSUB以类似于存储器单元电容器的电荷泄漏方式响应需要更加频繁地接通电荷泵的模片电压和温度而泄漏。
在所图解的实施例中,计数器是常规的模数计数器。该计数器被设计为每当计数器达到预定计数值时,发出“刷新请求”信号。在其它的实施例中,可以使用不同类型的计数器。刷新计数器22包含可编程的保险丝电路26。可编程的保险丝电路26包含多个保险丝28、30和32。通过“熔断”多个保险丝28、30和32中的一个或多个保险丝,可以针对任何给定的半导体模片或晶圆提高或减少与刷新周期之间的ON/OFF周期数相对应的预定计数,以补偿由于处理差异而引起的不同泄漏。可以依据从最好到最差模片的量级改变要补偿的泄漏速度。在所图解的实施例中,多个保险丝28、30和32是电性熔断的。在其它的实施例中,多个保险丝可以是激光熔断的,或者可以包含多个非易失性寄存器位等等。
根据本发明的另一个方面,可以在利用BIST电路24的晶圆级测试期间确定由于处理变化而导致的存储器10的潜在刷新速率。因为刷新速率测试比大部分测试时间更且代价更高,所以必须并行地对模片进行测试,以减少实际测试时间,因此得以减少测试成本。并行地对模片进行测试的一种方式是利用晶圆级测试。对于晶圆级测试,晶圆上所有或较大子集的模片被并行探测和测试,以减少总的测试时间。
BIST电路24与模块14双向连接,以接收和提供用于测试存储器阵列12的测试数据和控制信号。并且,BIST电路24提供标记为“BIST刷新控制”的刷新控制信号。此外,BIST电路24接收串行测试输入数据SIN,提供串行测试输出数据SOUT和接收控制信号“BIST控制”。如限定集成电路存储器10边界的虚线所示,信号SIN、SOUT和“BIST控制”被接至集成电路存储器10之外。
图2根据本发明图解了在晶圆探针测试期间半导体晶圆38的俯视图。半导体晶圆38包含多个集成电路,例如集成电路存储器10,其中利用常规半导体工艺来形成这些集成电路。在制备过程中,晶圆38将被分成单个的“模片”。单个的模片在分离后将进行进一步的加工。然而,在分离之前,晶圆上的集成电路可在称之为“晶圆探测”或“晶圆级测试”的过程期间进行测试。对于晶圆级测试,晶圆包含多个例如探测脚48、50、52、54、56和58这样的探测脚。探测脚与晶圆探针接触。例如图2中探针60、62的晶圆探针被用于在测试设备和在晶圆上形成的电路之间提供电性接触。在其它的实施例中,可以使用凸起膜或其它的晶圆接触技术与晶圆38进行电性接触。
在晶圆上的各个单模片之间包含有切割线。例如,图2中切割线40和42在垂直方向延伸,而切割线44和46在水平方向延伸。切割线限定其中晶圆将被切割以分离成单个模片的区域。然而,在分离之前,切割线为向每个模片传送测试信号提供了方便的位置。在图1中所图解的实施例中,在切割线中传送信号SIN、SOUT和“BIST控制”,以将具有集成电路存储器10的模片与探测脚相连。
BIST电路24被包含在晶圆38的每个集成电路上,并在晶圆38的晶圆探测期间用于分别测试多个集成电路存储器的存储器阵列的刷新时间。例如,参照图1和图2,当要对集成电路存储器10进行测试时,测试数据SIN被扫描到BIST电路24中。可使用“BIST刷新控制”信号触发刷新操作。测试结果作为SOUT数据被扫描输出。相邻模片的SIN和SOUT管脚通常通过切割线一起连接到扫描链,使得链中所有模片的测试结果能够从单个脚进行测试。SOUT数据可以包含模片是否通过测试、任何测试失败的单元和测试失败的地址。利用该测试结果,可以使用刷新计数器22逐个模片地调整刷新时间。此外,测试结果可以被用来根据刷新时间对模片进行储存或分类。
图3以流程图的形式图解用于测试具有图1中多个集成电路存储器的晶圆38的方法70。在所图解的实施例中,方法70在晶圆级老化期间进行。在其它的实施例中,方法70可以用在其它的晶圆级测试环境中。
在步骤72中,提供具有多个集成电路存储器的半导体晶圆。在步骤73中,晶圆的温度被调整到预定的测试温度。在所图解的实施例中,测试温度明显地大于室温,例如,测试温度为摄氏100度。在其它的实施例中,测试温度可以在室温左右或明显地低于室温。在步骤74中,晶圆的测试脚与晶圆探针接触以提供测试模片和测试仪器之间的电性接触。
在步骤76中,对多个存储器集成电路模片的最大刷新速率进行并行BIST测试,以确定特定模片上的存储器单元何时失效,并为该多个集成电路中的每一个记录结果。
在步骤78中,分析多个存储器集成电路的电荷储存能力以确定每个模片的刷新速率和相应的保险丝坐标。在步骤80中,用计算出的保险丝坐标对多个集成电路的可编程保险丝电路进行编程。这些保险丝可以电性熔断、用激光熔断、或通过类似方式进行熔断。
这允许以关于单个模片的处理变化的最优刷新速率来刷新每个模片。因为仅以针对特定温度提供可靠数据存储所需的频繁程度来刷新存储器,与使用基于最差情形下的温度的固定较高刷新速率的存储器相比,降低了该存储器的功耗。
然而在另一个实施例中,可利用常规老化印刷电路板在“板级老化”时对模片进行测试。利用板迹线来传送BIST控制信号“BIST控制”和串行数据信号SIN和SOUT。一般地,测试方法如图3所述,首先将待测试的已封装好的集成电路插入老化印刷电路板的测试插槽中。通常的老化板具有足够的测试插槽,以容纳八个或更多个已封装好的集成电路来进行并行测试。已封装好的集成电路被加温到测试温度。当该集成电路存储器处于测试温度时,测量其电荷保持力。然后,分析已封装好的集成电路的电荷存储能力以确定刷新速率。最后,设置可编程的保险丝电路26,以用该刷新速率对刷新计数器进行编程。参照图2,如上所述,能够单独确定每个封装的集成电路的刷新速率。由于模片已经进行了封装,板级老化和晶圆级老化之间的一个差别是保险丝必须被电性熔断。板级老化的不利之处在于它与晶圆级老化相比,能够并行测试的集成电路存储器较少。然而,封装的集成电路的老化时间通常比BIST测试时间要长得多,因此根据本发明的刷新测试并未延长板级老化的时间。
本领域的技术人员可以容易地想到对这里为图解目的而选择的实施例进行的各种变化和修改。例如,可以容易地对晶体管传导性的类型、晶体管的类型等等进行变化。在这样的修改和变化不偏离本发明范围的情况下,试图将它们都包含在仅由下列权利要求书的公正解释来声明的范围之内。
Claims (9)
1.一种存储器,包括:
需要周期性刷新以维持所存储的数据的多个存储器单元;
与这多个存储器单元相连、用于提供衬底偏压的电荷泵;
与电荷泵相连的电压调节器,用于提供用来控制衬底偏压的电压水平的泵浦使能信号;
具有与电压调节器相连的输入终端的刷新计数器,用于接收泵浦使能信号,并作为响应,提供刷新定时信号;以及
刷新控制电路,其被连接以接收刷新定时信号,并作为响应,控制多个存储器单元的刷新操作。
2.如权利要求1所述的存储器,其中该多个存储器单元和多个测试存储器单元是动态随机访问存储器(DRAM)单元。
3.如权利要求1所述的存储器,其中由刷新计数器响应泵浦使能信号来调整该多个存储器单元的刷新速率。
4.如权利要求1所述的存储器,其中刷新计数器的计数值是可调整的。
5.如权利要求4所述的存储器,其中存储器是包含在半导体晶圆上的集成电路模片,多个集成电路模片的一部分,且其中在半导体晶圆的晶圆探针测试期间使用可编程保险丝电路来调整刷新计数器的计数速率。
6.如权利要求5所述的存储器,进一步包括内置自测试(BIST)电路,用于在晶圆探针测试期间将测试数据扫描进、出多个存储器单元。
7.如权利要求1所述的存储器,其中刷新速率随着温度的改变而改变。
8.一种测试多个集成电路存储器的方法,每个集成电路存储器均具有多个需要周期性刷新以维持所储存的数据的存储器单元,该方法包括步骤:
提供具有多个集成电路存储器的半导体晶圆,该多个集成电路存储器的每一个集成电路存储器均具有刷新计数器,用于向刷新控制电路提供刷新定时信号,以控制该多个存储器单元的刷新速率;
在该多个集成电路存储器中的每个集成电路存储器上提供与刷新控制电路相连的可编程保险丝电路;
在该多个集成电路的每个集成电路上提供内置自测试(BIST)电路,用于将测试数据扫描进、出该多个集成电路存储器的每个集成电路存储器上的多个存储器单元;
在半导体晶圆上提供与BIST电路相连的多个晶圆测试脚;
将晶圆测试脚与晶圆探针接触;
测试该多个集成电路中的每个集成电路上的多个存储器单元的电荷保持能力;
分析该多个集成电路中的每个集成电路上的多个存储器单元的电荷保持能力,以确定多个刷新速率,其中对于该多个集成电路的每个集成电路,均有一刷新速率相对应;以及
用其相应的刷新速率对该多个集成电路的可编程保险丝电路的每一个进行编程。
9.如权利要求8所述的方法,进一步包括调整晶圆测试温度的步骤。
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- 2004-02-06 WO PCT/US2004/003494 patent/WO2004075257A2/en active Application Filing
- 2004-02-06 KR KR1020057014195A patent/KR20050106410A/ko not_active Application Discontinuation
- 2004-02-06 CN CNB200480004696XA patent/CN100538869C/zh not_active Expired - Fee Related
- 2004-02-17 TW TW093103795A patent/TWI330365B/zh not_active IP Right Cessation
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US9490003B2 (en) | 2011-03-31 | 2016-11-08 | Intel Corporation | Induced thermal gradients |
US10514305B2 (en) | 2011-03-31 | 2019-12-24 | Intel Corporation | Induced thermal gradients |
CN104115227A (zh) * | 2011-12-23 | 2014-10-22 | 英特尔公司 | 使用系统热传感器数据的存储器操作 |
US9396787B2 (en) | 2011-12-23 | 2016-07-19 | Intel Corporation | Memory operations using system thermal sensor data |
CN104115227B (zh) * | 2011-12-23 | 2017-02-15 | 英特尔公司 | 使用系统热传感器数据的存储器操作 |
CN106683692A (zh) * | 2015-11-05 | 2017-05-17 | 三星电子株式会社 | 非易失性存储装置及其操作方法 |
CN109031983A (zh) * | 2017-06-12 | 2018-12-18 | 南亚科技股份有限公司 | Dram的帮浦系统及其操作方法 |
CN109031983B (zh) * | 2017-06-12 | 2020-08-14 | 南亚科技股份有限公司 | Dram的帮浦系统及其操作方法 |
CN113936733A (zh) * | 2021-10-15 | 2022-01-14 | 西安紫光国芯半导体有限公司 | 三维集成电路晶圆的测试方法、测试装置和三维集成电路 |
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JP4778889B2 (ja) | 2011-09-21 |
CN100538869C (zh) | 2009-09-09 |
KR20050106410A (ko) | 2005-11-09 |
WO2004075257A3 (en) | 2005-01-13 |
WO2004075257A2 (en) | 2004-09-02 |
US20040160838A1 (en) | 2004-08-19 |
JP2006518532A (ja) | 2006-08-10 |
TWI330365B (en) | 2010-09-11 |
US6781908B1 (en) | 2004-08-24 |
TW200504748A (en) | 2005-02-01 |
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