TWI330365B - Memory having variable refresh control and method therefor - Google Patents

Memory having variable refresh control and method therefor Download PDF

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Publication number
TWI330365B
TWI330365B TW093103795A TW93103795A TWI330365B TW I330365 B TWI330365 B TW I330365B TW 093103795 A TW093103795 A TW 093103795A TW 93103795 A TW93103795 A TW 93103795A TW I330365 B TWI330365 B TW I330365B
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Taiwan
Prior art keywords
update
memory
circuit
memory cells
control
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Application number
TW093103795A
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English (en)
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TW200504748A (en
Inventor
Perry H Pelley
John M Burgan
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Freescale Semiconductor Inc
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Publication of TW200504748A publication Critical patent/TW200504748A/zh
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Publication of TWI330365B publication Critical patent/TWI330365B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4061—Calibration or ate or cycle tuning

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Description

1330365 九、發明說明： 【發明所屬之技術領域】 本發明大體上關於積體電路記憶體，及更特別地，關於 具有可變更新率控制之動態隨機存取記憶體（DRAM)。 【先前技術】 動態隨機存取記憶體（DRAM)習知是依賴電容以儲存表 示二邏輯狀態之電荷的記憶體類型。通常，各DRAM格包 括一電容及一存取電晶體。儲存在電容的電荷會隨著時間 漏出，需要dram格所儲存的資料週期地讀取及寫入，或 更新。週期的更新操作需要大量的能量。 由電谷漏的電荷量因溫度及程序變異而大幅變動。較 冋的/皿度會比較低溫時造成更多的洩漏。因此，對具有固 疋更新率的dram而言，記憶格必須一速率更新，該速率 可在最糟狀況洩漏時擔保可靠的#保留。對電池供能裝置 而言，儘可能低的能量耗損是很重要的。固定的更新率較 電池供 【發明内容】 記憶體之可靠操作所必須需要更高的能量耗損。
控制更新記憶體操作及降低記憶體的能量耗損 【實施方式】 大體上， 大體上，本發明提供一種記憶體， 期性更新以維持儲存的資料的記 其具有複數個需要週 ’一電荷泵，一電壓 91194.doc 1330365 調節器，一更新控制電路’及一更新計數器.電荷泵提供 基板偏壓至複數個記憶格。電壓調節器耦合至電荷果及提 供一果致能彳§號以維持基板偏壓之電壓位準在上下限之 内。更新控制電路控制複數個記憶格的更新操作。更新計 數器輕合以接收泵致能信號’及依回應提供一更新時序信 號至更新控制電路以控制複數個記憶格的更新率^更新率 會藉由更新計數圖依提供泵致能信號的電壓調節器而調 整。 亦，會設置一可程式化熔絲電路以程式化更新率可程 式化熔絲電路可在晶圓探測測試期間程式化。此外，積體 電路上可包括一内建式自我測試（BIST)電壓以利於測試。 因為電荷洩漏，如同FET(場效應電晶體）接面洩漏會隨著 溫度而改變，電壓調節器會隨著溫度增加而更頻繁地改變 電荷泵。因此，當溫度上升時，藉由電壓調節器泵致能信 號所驅動的更新計數器會增加記憶陣列的更新率。因此可 在一溫度範圍内提供最佳更新率的記憶陣列以利於更新。 亦，對特定溫度而言，允許記憶體只以提供可靠之資料儲 存所必須的頻率更新。基於溫度可調整的較低更新率，相 較於依最糟狀況溫度及程序變異而使用固定較高更新率的 記憶體而言，可提供較低的記憶體能量耗損。亦，因為電 荷泵及調節器已存在於積體電路上，關於本文所揭露之實 施例的能量耗損更會再降低。 圖1以方塊圖繪示根據本發明的積體電路記憶體丨〇之方 塊圖。積體電路記憶體10包括記憶陣列12，解碼器，感測 91194.doc 1330365 放大器，及I/O電路方塊14，更新控制電路16，電荷泵18, 電塵調節器20’更新計數器22,及内建式自我測試（bist) 電路24。積體電路記憶體1〇可以是獨立運作的記憶體或嵌 入的記憶體》記憶陣列12是含記憶格的陣列，該記憶格耦 合至位7G線與字線的交叉點。記憶格可組織為含記憶格的 多區塊。在繪示的實施例中，記憶格是習知的動態隨機存 取記憶（DRAM)格，其具有一電容及一存取電晶體。電容用 以耦合表示儲存之邏輯狀態的電荷。存取電晶體用以在存 取記憶格時依一選擇的字線耦合電容至一位元線。在其他 實施例中，記憶陣列12包括其他記憶格類型，其需要週期 性更新以維持儲存的邏輯狀態。 區塊14包括用以存取記憶陣列12以讀取，寫入，及更新 操作的電路，及以複數個導體耦合至記憶陣列12。積體電 路記憶體10在讀取及寫入操作期間作用似習知D R A M。區 塊14包括列及行解碼器’感測放大器，控制電路，及l/〇電 路。區塊14接收控制信號（標示為，iC〇NTR〇L")，其表示用 在5己憶體的多樣控制信號，例如，白色致能（wE)，感測致 能（SE)，等。依控制信號c〇nTR〇l及標示為"AdDrESS" 的疋址信號，列及行解碼器可存取記憶陣列12的至少一記 憶格。在讀取操作期間，感測放大器可感測及放大選擇位元 線上電壓，其對應至儲存邏輯狀態及提供對應的邏輯信號至 1/0電路以再放大及緩衝。I/O電路會傳輸標示為"DATA"的緩 衝資料信號至記憶體1〇外部的電路。在寫入操作期間，輸入 資料信號會經雙方向的資料線DATA提供至區塊14 ^輸入資 91194.doc 1330365 料信號會提供至對應到定址信號address的記憶位置。控 制信號CONTROL可用以控制讀取及寫入環循兩者。 更新控制電路16會控制及統合記憶陣列12的更新操作。 記憶陣列12及電路方塊14内的更新操作是習知的且會自動 發生，或經控制信號（標示為"RFSHCNTRL")回應來自方塊 14以用於更新的外部要求。更新控制電路16亦可經複數個 導體（標示為"REFRESH CONTROL")及複數個導體（標示為 "REFRESH ADDRESS")耦合至電路方塊14。此外，更新控 制16會接收來自更新計數器22的"REFRESH REQUEST"信 號及來自BIST電路24的BIST更新控制信號（標示為"BIST REFRESH CONTROL")。 電荷泵18是習知的電荷泵，及可用以提供標示為"VSUB" 的基板偏基至記憶陣列12。在其他實施例中，電荷泵18可 用於其他目的。例如，電荷泵18可用以提供用於記憶陣列 12之電容的平板電壓或昇壓字線電壓。依賴此樣的應用， 電荷泵18提供的電壓可以是任何電壓，通常大於提供至電 量供應電壓終端（標示為"VDD”及”VSS”）的供應電壓。典型 上，VDD會接收一正電供應電壓，及VSS是地線電位。在 其他實施例中，提供至VDD及VSS的電壓是不同的。亦， 在其他實施例中，電荷泵18提供小於電量供應電壓的提高 電壓，或負電壓》 電壓調節器20是習用的電壓調節器。電壓調節器20具有 一輸入’其耦合以接收基板偏壓VSUB，及一輸出端，其用 以提供控制信號ΟΝ/OFF以控制電荷泵18的輸入。電壓調節 91194.doc 1330365 器20會監視電壓VSUB，及替代地宣稱及反宣稱on/OFF信 號以維持基板偏壓VSUB在具有上限及下限的預設電壓範 圍内。即，當宣稱ΟΝ/OFF信號時，電壓VSUB會增加直至 達到上限電壓。接著，電壓調節器20會反宣稱on/OFF信 號，及電荷泵18會停止唧取直至電壓VSuB掉至下限。此 時，ON/OFFk號可再次地宣稱，及電荷果1 8會開始哪取且 VSUB會增加。在記憶體1 〇的普通操作期間，〇N/〇FF信號 的旦稱及反宣稱多少是週期性的。此外，當記憶體丨〇的電 壓或溫度提高時，電壓調節器20會令電荷泵18頻繁地導通 及截止。 除了控制電荷泵18之外，電壓調節器2〇可用以依本發明 而控制記憶陣列12的更新時序。即，電壓調節器2〇因記憶 體之溫度及電壓的改變所導致之電壓切換操作的改變可用 以經更新計數器22改變記憶陣列12的更新頻率。更新計數 器22具有時脈輸入端(CLK)’其耦合至電壓調節器2〇以接收 ON/OFF信號，及用以提供—更新要求信號（標示為 "咖㈣H REQ刪T”）的輸出端。更新計數器22可用以轉 換調節器⑽㈣循環以更新時序，充份利用⑽卿循環 的溫度及電壓變異以改變更新率。如上述，溫度及電廢變 異會影響由記憶格電容的電荷茂漏。因此，當記憶體⑽ 溫度或電壓増加時’記憶陣列需要再更新的速率會增加。 當晶粒溫度改變至第-等級時，調節器2〇物辦輸出之 頻率的改變會追縱㈣m這是因議以一方式 邊漏’該方式相似於由記憶格電容依晶粒電壓及溫度的電 91194.doc 1330365 何Ά漏’而電何果必須更頻繁地導通。 在繪示的實施例中，計數器是習知的模組計數器。計數 器設計為用以在每一次計數器達到預設的數值時，即宣稱 REFRESH request信號。在其他實施例中可使用不同 類型的計數器。更新計數器22包括可程式化熔絲電路％。 可私式化溶絲電路26包括複數個炫絲28，3〇及32。藉由燒 對應至更新循環 斷複數個熔絲28，30及32之至少一溶絲 間之ΟΝ/OFF循環數的預設計數可因任何特定半導體晶粒 或晶圓的提高或降低以補償因程序差異的不同洩漏。補償 的洩漏速率會由最佳強度等級變動為最糟。在繪示實施例 中’複數個熔絲28，30及32可以是電燒斷的。在其他實施 例中’複數個炫絲可以疋雷射燒斷的’或包括複數個非揮 發性登記位元，等。 根據本發明的另一觀點’記憶體1 〇因程序變動的潛在更 新率可在晶圓級測試期間使用BIST電路24而判定。因為更 新率測試大幅地較長，及更是大為昂貴，因而大多測試中， 晶粒必須並聯測試以降低有效的測試時間及成本。並聯測 試晶粒的一方式是藉由使用晶圓級測試。對晶圓級測試而 言，會並聯探測及測試晶圓上所有或大多的晶粒子集以降 低整體測試時間。 BIST電路24雙方向地耦合至方塊14以接收及提供用以測 試記憶陣列12的測試資料及控制信號。亦，BIST電路24可 提供一更新控制信號（標示為”BIST REFRESH CONTROL")。 此外，BIST電路24可接收連續的測試輸入資料SIN，提供連 91l94.doc 1330365 續的測試輸出資料S0UT ’及接收控制信號 CONTROL。如虛線所界定的㈣電路記憶體心邊界所 示，信號sm，SOUT，及BIST c〇ntr〇l會由外路定 至積體電路記憶體丨〇。 圖2繪示根據本發明在晶圓探測測試㈣的半導體上下 觀圖。半導體晶圓38包括複數個積體電路，如，積體電路 記憶體10’其可使用習知半導體製程形成。在製程期門 晶圓38可分為獨特的晶粒。獨特的晶粒分離後可經再處 =。然而’在分離之前，晶圓上的積體電路可在習知為晶 圓探測或晶圓級測試之程序期間測試。對晶圓級測試而 吞，晶圓包括複數個探測墊，如探測墊48, 5〇, U，W， 56,及58。探測墊可與晶圓探針接觸。晶圓探針，如，圖2 的探針嶋62,可帛讀供測試裝置與晶圓上形叙 電路間的電接觸。在其他實施你 “ 貫施例中，唧取膜或其他晶圓接 觸技術可用以電連接至晶圓38。 切割軌包括在晶圓38上的各獨特晶粒之間^例如， 軌40及42在圖2上是番亩击闩 β ° 疋垂直走向，及切割轨44及46是水平走 向。切割軌界定切分晶圓以令晶圓分為獨特晶粒的區域。 然而’在分離之前，切割軌會提 穴供万便的位置以令測試信 化定路線至各晶粒。在請示的實施例中，信號㈣，$隨 及BIST CONTROL可在切割執中定钤始± 足路線以耦合具有積體電 路记憶體10的晶粒至探測墊。 BIST電路24包括在晶圓38上 妁各積體電路上，及可在晶 圓38的晶圓探測期間用以 K式關於複數個積體電路記 91194.doc •12- 1330365 專利範圍》 【圖式簡單說明】 熟習此技藝者由下文較佳實施例之詳 解本發明的種種特；t目的及優點： 4合附圖可更了 圖1以方塊圖繪示根據本發明的積體電路 圖2繪示根據本發明在晶圓探 觀圖。 圓探心以期間的半導體上下 圖3以流程圖繪示圖丨之積體電 r 士 © _ %吩°G隐體之測試方法。 【主要7G件符號說明】 10 12 14 16 18 20 22 24 26 28 ， 30 ， 32 38 40 48 56 42，44 5〇 > 52 58 46 54 60，62 積體電路記憶體 記憶陣列 I/O電路方塊 更新控制電路 電荷泵 電壓調節器 更新計數器 内建式自我測試（BIST)電路 可程式化熔絲電路 熔絲 晶圓 切割軌 探測墊 探針 91194.doc -15-

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133036¾ 093103795號專利中請案 中文申請專利範圍替換本(99年3月） 十、申請專利範園： 1 · 一種記憶體，包括： 複數個記憶格’其需要週期性更新以維持所儲存之資 料； 一電何泵，其耦合至複數個記憶格以提供一基板偏 壓； 一電壓調節器，其搞合至雷霜；^ 担 王电何泵以铨供一泵致能信號 來控制基板偏壓之電壓位準； -更新計數器，其具有耦合至電壓調節器之輸入端以 接收泵致能信號，及.依回應提供一更新時序 -更新控制電路’其搞合以接收更新時序信號，及依 ， 回應控制複數個記憶格之更新操作。 2. —種記憶體，包括： 複數個記憶格，其需要週期性更新以維持所儲存之資 料； 一電荷泵’其用以提供-基板偏壓至複數個記憶格; -電壓調節器，其耦合至電荷泵以提供一泵致能信號 來維持基板偏壓之電壓位準於上下限之内； 一更新控制電路 作；及 其用以控制複數個記憶格之更新操 -更新计數器，其具有輕合至㈣調節器之輪人端以 接收系致能信號，及依回應提供—更新時序信號至更新 控制電路以控制複數個記憶格之更新率； 其中該更新率係藉由該更新計數器調整以回應提供 91194-990325.doc 3. l9| l 該泵致能信號之該電 —種測試複數個積體電路記憶體之 憶體具有複數個記憶格，其 ：積體電路記 存之資料，該方法包括《下=仙性更新《維持所健 提供-半導體晶圓，其具有複數 各別積體電路妹體呈丨電路5己憶體， C U髖具有一更新計數器，用以 新時序信號至尹報i9t座丨+ '、 ^ 新率； 崎以控制稷數個記憶格之更 於各別積體電路記憶體上提 攸甘*人 了転式化熔絲電 路，耦&至該更新控制電路； 於各別積體電路上提供一 /、内建式自我測試（BIST)電 路其用以掃描測試資料出入各別積體電路記憶體上 複數個記憶格； 提供複數個晶圓測試墊，其搞合至半導體晶圓 BIST電路； 令晶圓測試墊與晶圓探針接觸； 測量各別積體電路上之複數個記憶格之電荷保留能 力； 分析各別積體電路上之複數個記憶格之電荷保留能 力’以決足複數個更新率，一更新率對應至各別積體電 路；及 以各別對應之更新率程式化複數個積體電路之各可 程式化炼絲電路。 91194-990325.doc 1330365 第093103795號專利申請案 中文圖式替換頁(99年3月） Η—、圖式： BIST 控制 • · · Sin » · · Scxrr 24 BIST 14 控制 位址 控制’解碼 感測放大器 I/O電路 資料 η “
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