JP4778889B2 - 可変リフレッシュ制御を有するメモリおよびその方法 - Google Patents
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- JP4778889B2 JP4778889B2 JP2006503388A JP2006503388A JP4778889B2 JP 4778889 B2 JP4778889 B2 JP 4778889B2 JP 2006503388 A JP2006503388 A JP 2006503388A JP 2006503388 A JP2006503388 A JP 2006503388A JP 4778889 B2 JP4778889 B2 JP 4778889B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
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- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
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- G11C11/40626—Temperature related aspects of refresh operations
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- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
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- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
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- G11C7/1045—Read-write mode select circuits
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- G11C8/00—Arrangements for selecting an address in a digital store
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- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4061—Calibration or ate or cycle tuning
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
Description
ADDRESS」と表示した複数の導体を介して回路ブロック14にも結合されている。さらに、リフレッシュ制御16は、リフレッシュ計数器22から「REFRESH REQUEST」信号を受け取り、またBIST回路24から「BIST REFRESH CONTROL」と表示したBISTリフレッシュ制御信号を受け取る。
び32のうちの1つまたは複数を「飛ばし」て、リフレッシュ・サイクル間のON/OFFサイクルの数に対応する所定計数値を任意の半導体チップまたはウエハについて上げるかまたは下げるかして、工程差による漏れの違いを補償することが可能である。補償すべき漏れ速度は、最良チップから最悪チップの範囲で桁のオーダで変化することがある。例示の実施形態では、複数のヒューズ28、30および32は、電気的に飛ばす。他の実施形態では、複数のヒューズは、レーザで飛ばすことが可能であり、または、複数の不揮発性レジスタ・ビットまたは同様なものを含むことができる。
験すべき時、試験データSINをBIST回路24に取り込む。BIST REFRESH CONTROL信号を使用してリフレッシュ動作を起動することが可能である。試験結果は、SOUTデータとして取り出される。隣り合うチップのSINピンおよびSOUTピンは、通常、ダイシング・レーンを通して走査チェーン中に一緒に結合されるので、チェーン中のチップ全ての試験結果は単一パッドから調べることができる。SOUTデータは、チップが合格したかどうか、不良セルおよび不良アドレスを含むことができる。試験結果を使用すると、チップごとにリフレッシュ計数器22を使用してリフレッシュ時間を調整することが可能である。さらに、試験の結果を使用して、リフレッシュ時間に従ってチップを箱に入れること、すなわち選別することができる。
でヒューズを電気的に飛ばさなければならないことである。基板レベルのバーンインの不利点は、ウエハ・レベルのバーンインに比べてより少ない集積回路メモリを並列に試験することが可能なことである。しかし、パッケージされた集積回路のバーンイン時間は通常BIST試験時間よりもはるかに長いので、本発明に従ったリフレッシュ試験は、基板レベルのバーンイン時間を延長することにならない。
Claims (2)
- 格納されたデータを維持するために周期的なリフレッシュを必要とする複数のメモリ・セル(12)と;
同複数のメモリ・セル(12)に接続された、基板バイアス(VSUB)を該複数のメモリ・セル(12)に供給するための充電ポンプ(18)と;
同充電ポンプ(18)に接続された、該基板バイアス(VSUB)の電圧レベルを制御するポンプ・イネーブル信号を供給するための電圧調整器(20)と;
該ポンプ・イネーブル信号を受け取るように該電圧調整器(20)に接続された入力端子を有し、かつ該ポンプ・イネーブル信号に応答してリフレッシュ・タイミング信号を供給するリフレッシュ計数器(22)と;
該リフレッシュ計数器(22)に接続されたプログラム可能ヒューズ回路(26)と;
同リフレッシュ・タイミング信号を受け取るように接続され、かつ同リフレッシュ・タイミング信号に応答して該複数のメモリ・セル(12)のリフレッシュ動作を制御するリフレッシュ制御回路(16)と;
各々の該複数のメモリ・セル(12)に試験データを取り込みまた該複数のメモリ・セル(12)から該試験データを取り出すための内蔵自己試験回路(24)と
からなる集積回路メモリ(10)であって、
個々の該集積回路メモリ(10)が切り出される前の半導体ウエハ(38)が試験温度に設定され(73)、該集積回路メモリ(10)それぞれが備える該複数のメモリ・セル(12)の電荷保持能力が該試験温度で測定され(76)、該集積回路メモリ(10)ごとに電荷保持能力が解析されることによって、該集積回路メモリ(10)それぞれに対応するリフレッシュ速度が決定され(78)、該プログラム可能ヒューズ回路(26)それぞれは、該集積回路メモリ(10)の温度ごとに最適な該リフレッシュ速度で該複数のメモリ・セル(12)をリフレッシュすべく、該リフレッシュ計数器(22)が該リフレッシュ制御回路(16)に該リフレッシュ・タイミング信号を供給するようにプログラムされ、
該試験温度は、該集積回路メモリ(10)がパッケージされる製品ごとに、その製品が使用される温度に該当するように、室温よりも十分に高い温度と、室温と、室温よりも十分に低い温度とのうちから選択されることを特徴とする、集積回路メモリ。 - 複数の集積回路メモリ(10)を試験する方法であって、該集積回路メモリ(10)の各々は、格納されたデータを維持するために周期的なリフレッシュを必要とする複数のメモリ・セル(12)を有し、
該複数の集積回路メモリ(10)を有する半導体ウエハ(38)を供給する工程(72)であって、該複数の集積回路メモリ(10)の各々が、該複数のメモリ・セル(12)のリフレッシュ速度を制御するためのポンプ・イネーブル信号を受け取るように電圧調整器(20)に接続された入力端子を有し、かつ応答してリフレッシュ・タイミング信号を供給するリフレッシュ制御回路(16)に供給するリフレッシュ計数器(22)を有することと;
該複数の集積回路メモリ(10)の各々に、該リフレッシュ制御回路(16)に結合されたプログラム可能ヒューズ回路(26)を設ける工程と;
該複数の集積回路メモリ(10)の各々の該複数のメモリ・セル(12)に試験データを取り込みまた該複数のメモリ・セル(12)から取り出すための内蔵自己試験回路(24)を該複数の集積回路メモリ(10)の各々に設ける工程と;
該内蔵自己試験回路(24)に結合された複数のウエハ試験パッドを該半導体ウエハ(38)に設ける工程と;
該半導体ウエハ(38)を試験温度に設定する工程(73)であって、該試験温度は、該集積回路メモリ(10)がパッケージされる製品ごとに、その製品が使用される温度に該当するように、室温よりも十分に高い温度と、室温と、室温よりも十分に低い温度とのうちから選択されることと;
該ウエハ試験パッドにウエハ・プローブ針(60,62)を接触させる工程(74)と;
該複数の集積回路メモリ(10)の各々の該複数のメモリ・セル(12)の電荷保持能力を該試験温度で測定する工程(76)と;
該複数の集積回路メモリ(10)の各々の該複数のメモリ・セル(12)の電荷保持能力を解析することによって、該複数の集積回路メモリ(10)の各々に対応するリフレッシュ速度を決定する工程(78)と;
該プログラム可能ヒューズ回路(26)の各々をプログラムする工程(80)であって、該プログラム可能ヒューズ回路(26)は、該集積回路メモリ(10)の温度ごとに最適な該リフレッシュ速度で該複数のメモリ・セル(12)がリフレッシュするように、該リフレッシュ計数器(22)から該リフレッシュ制御回路(16)に該リフレッシュ・タイミング信号を供給させることと
からなる方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/370,011 | 2003-02-19 | ||
US10/370,011 US6781908B1 (en) | 2003-02-19 | 2003-02-19 | Memory having variable refresh control and method therefor |
PCT/US2004/003494 WO2004075257A2 (en) | 2003-02-19 | 2004-02-06 | Memory having variable refresh control and method therefor |
Publications (3)
Publication Number | Publication Date |
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JP2006518532A JP2006518532A (ja) | 2006-08-10 |
JP2006518532A5 JP2006518532A5 (ja) | 2007-03-29 |
JP4778889B2 true JP4778889B2 (ja) | 2011-09-21 |
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JP2006503388A Expired - Fee Related JP4778889B2 (ja) | 2003-02-19 | 2004-02-06 | 可変リフレッシュ制御を有するメモリおよびその方法 |
Country Status (6)
Country | Link |
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US (1) | US6781908B1 (ja) |
JP (1) | JP4778889B2 (ja) |
KR (1) | KR20050106410A (ja) |
CN (1) | CN100538869C (ja) |
TW (1) | TWI330365B (ja) |
WO (1) | WO2004075257A2 (ja) |
Families Citing this family (46)
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- 2004-02-06 CN CNB200480004696XA patent/CN100538869C/zh not_active Expired - Fee Related
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CN1751357A (zh) | 2006-03-22 |
TWI330365B (en) | 2010-09-11 |
JP2006518532A (ja) | 2006-08-10 |
WO2004075257A3 (en) | 2005-01-13 |
CN100538869C (zh) | 2009-09-09 |
US20040160838A1 (en) | 2004-08-19 |
TW200504748A (en) | 2005-02-01 |
WO2004075257A2 (en) | 2004-09-02 |
US6781908B1 (en) | 2004-08-24 |
KR20050106410A (ko) | 2005-11-09 |
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