CN1714434A - 电介质膜的形成方法 - Google Patents

电介质膜的形成方法 Download PDF

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Publication number
CN1714434A
CN1714434A CNA038256304A CN03825630A CN1714434A CN 1714434 A CN1714434 A CN 1714434A CN A038256304 A CNA038256304 A CN A038256304A CN 03825630 A CN03825630 A CN 03825630A CN 1714434 A CN1714434 A CN 1714434A
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film
dielectric film
formation method
upgrading
film according
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CN100411116C (zh
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肖石琴
大场隆之
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Fujitsu Semiconductor Ltd
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Fujitsu Ltd
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Abstract

一种把电介质膜形成在基板表面上的电介质膜形成方法，包含在所述基板表面上分多次形成高K电介质膜的工序，在所述分多次进行的高K电介质膜形成工序的各个工序中，在以氮气为主的气氛中对所形成的高K电介质膜进行改质的处理工序。

Description

电介质膜的形成方法
技术领域
本发明涉及半导体器件，特别是涉及具有由金属氧化物或金属硅酸盐构成的高介质绝缘膜(所谓高K电介质膜)的半导体器件及其制造方法。
背景技术
在要求超高速动作的CMOS-LSI之类的半导体集成电路器件中，构成半导体集成电路器件的场效应晶体管(MOSFET)要求具有非常短的栅极长度，因此，对于MOSFET的微细化正在付出巨大的努力。
在被这样微细化了的MOSFET中，按照定标规则的要求也要对栅极绝缘膜的膜厚加以限制，例如，按氧化膜膜厚换算，要求把栅极绝缘膜的膜厚减小到大约2.5nm以下。
以往，一般使用漏电流特性好且界面能级密度低的硅氧化膜作为栅极绝缘膜。但是，由硅氧化膜构成的原来的栅极绝缘膜中，随着栅极绝缘膜的物理膜厚的减少会直接增加隧道电流，因此，从上述的值进一步减少栅极绝缘膜的膜厚时，由隧道电流引起的栅极漏电流就会增大。一旦栅极漏电流增大，例如在栅极关断时就会产生实质的漏电流，半导体器件的电路就不能正常动作，或者会增大耗电等。
因此，为解决上述的问题，正在探讨采用具有高介电常数的金属氧化物或金属硅酸盐之类的高介质膜(下称“高K电介质膜”)作为栅极绝缘膜。
以往，在200～600℃的基板温度下用MOCVD法或原子层CVD(ALD)法来形成这种高K电介质膜。按照ALD法，以原料气体的形式供给包含构成高K电介质膜的金属元素的原料化合物，将原料化合物分子吸附在被处理基板表面上，再用水之类的氧化气体将其氧化，由此，1层原子层、一层原子层地生长高K电介质膜。采用这样的低温成膜技术可以生长出具有优良形态的高K电介质膜，用MOCVD法同样可以得到一样膜厚的高K电介质膜。
另一方面，在半导体制造工艺中，不仅有这种高K电介质膜的成膜工序，还包含经多次进行的离子注入工序，在这种离子注入工序中为了将导入到半导体基板中的元件区内的杂质元素激活，在1000℃左右，典型地在1050℃温度下的急速热处理工序是必不可少的。
因此，在具有由高K电介质膜构成的栅极绝缘膜的半导体器件中，即使在实施过这样的高温热处理之后，高K电介质膜栅极绝缘膜也必须保持优良的电气特性。
在栅极绝缘膜中包含有固定电荷或界面能级等缺陷的情况下，载流子被这些固定电荷或界面能级捕获，这样就会产生平带电压的位移或阈值特性的变化等问题。通过这些缺陷的漏电流也会增大，使半导体器件的可靠性下降。因此，与原来的热氧化膜一样，在高K介质栅极绝缘膜中也要求膜内不包含固定电荷或界面能级。
但是，用低温MOCVD法或ALD法形成的高K电介质膜是非晶质膜，一看就具有优良形态，而实际上在膜中也包含有种种缺陷。特别是用水作为氧化剂的ALD法形成的情况下，膜大多都含有大量的OH基。
因此，本发明的发明者在以本发明为基础的研究中，对这样在膜中包含大量的缺陷的非晶质状态的高K电介质膜，在实际的半导体器件的制造工艺中以激活杂质元素所使用的条件下进行热处理，由此来探讨特性的变化。
图1A所表示的是本发明的发明者在以上述本发明为基础的研究中用ALD法形成的HfO2膜的断面TEM像。
参照图1A，在300℃的基板温度下，像图2所示的那样间断设置氮气驱气工序同时反复供给HfCl4气体和H2O气，由此在形成了1nm厚的界面氧化膜(热氧化膜)的硅基板上形成3.0nm膜厚的HfO2膜，并具有表面平坦的一样的膜厚。
参照图1B，这样的高温热处理的结果使硅基板上的HfO2膜上发生显著的凝聚，丧失了图1A所见到的以一样的膜厚连续延展的HfO2膜的形态。随之，如后面所说明的那样，图1B的结构使漏电流大幅度地增大。这表示如前述的那样即使见到图1A的HfO2膜具有优良的形态，而实际上在膜中包含有大量的缺陷，所以进行热处理时发生经由这种缺陷的原子的大规模的移动。这样的膜不能用作高速半导体器件的栅极绝缘膜。
图1A、1B的TEM像上，应注意到能见到所述硅基板的网格像。
专利文献1 特开平11-177057号公报
专利文献2 特开2001-152339号公报
发明内容
本发明的概括的目的是提供解决上述课题的新颖的有用的电介质膜的形成方法。
本发明的更具体的目的是提供在基板表面上形成对高温热处理稳定的高K电介质膜的方法。
按照本发明的一个方案，提供一种在基板表面上形成电介质膜的电介质膜形成方法，该电介质膜形成方法包括如工序：
在所述基板表面上分多次形成所述电介质膜的工序；
在分多次形成的电介质膜形成工序的各个工序中，在以氮气为主的气氛中对所形成的电介质膜进行改质的处理工序。
按照本发明的其他方案，提供一种半导体器件，该半导体器件具备：基板、形成在所述基板上的高K介质栅极绝缘膜、形成在所述高K介质栅极绝缘膜上的栅极电极和在所述基板中形成在所述栅极电极两侧的一对扩散区；所述高K介质栅极绝缘膜具有重复叠层高K介质分子层和SiON分子层的结构。
按照本发明，在将高K电介质膜作为栅极绝缘膜而使用的半导体器件的制造工艺中，分多次进行所述高K电介质膜的形成，并在所述多次形成工序的各个工序中在氮气气氛内进行改质处理，由此使构成高K膜的原子在高K电介质膜中移动到平衡位置，来消除膜中的缺陷。结果，在将这样的高K电介质膜用作栅极电极的半导体器件的制造工艺中，形成高K电介质膜之后，进行离子注入工序，进一步在高温下激活用离子注入工序导入到基板内的杂质元素，即使在进行过这种激活热处理工序的情况下，也能得到对激活热处理稳定的高K电介质膜。特别是用添加了氧的氮气气氛中的热处理工序进行所述改质处理工序，能够使半导体基板和高K电介质膜之间的界面稳定性，另外，还可以抑制高K电介质膜中的氧缺损的发生。在高K电介质膜的膜中反复导入Si、O、N，就可以进一步提高对高温热处理的稳定性，同时能够降低漏电流。膜内这样导入了Si、O、N的高K电介质膜能够有效地阻止包含在栅极中的B(硼)等杂质元素的扩散。另外，还可以用等离子体处理来进行所述改质处理工序。
参照附图进行的优选实施例的详细说明将使本发明的其他目的和特征更加明确。
附图说明
图1A和1B是用原来的方法形成的高K电介质膜及其问题点的说明图。
图2是原来的ALD处理序列示意图。
图3A～3D是本发明的第一实施例的电介质膜的形成方法的说明图。
图4是本发明的第一实施例使用的ALD处理序列的示意图。
图5是用本发明的第一实施例形成的高K电介质膜的示意图。
图6是图5的高K电介质膜的高温热处理后的状态示意图。
图7是本发明的第一实施例使用的叶片式处理装置的构成示意图。
图8是用本发明的第二实施例形成的高K电介质膜的高温热处理后的状态示意图。
图9是本发明的第二实施例使用的膜改质装置的构成示意图。
图10是本发明的第三实施例的MOS二极管的结构示意图。
图11是图10的MOS二极管的漏电流特性示意图。
图12A和12B分别是高温热处理前后的状态下，图10的MOS二极管的C-V特性示意图。
图13是改质处理时的温度与所得到的高K电介质膜的平均膜厚的关系示意图。
图14是本发明的第四实施例使用的膜改质处理装置的构成图。
图15和16是本发明的第四实施例中所得到的高K电介质膜的概略结构示意图。
图17是图10的MOS二极管中按照本发明的第四实施例形成高K电介质膜的情况下的C-V特性示意图。
图18是图10的MOS二极管中按照本发明的第四实施例形成高K电介质膜的情况下的漏电流特性示意图。
图19A～19F是本发明第五实施例的半导体器件的制造工序示意图。
具体实施方式
[第一实施例]
图3A～3D表示的是本发明的第一实施例的电介质膜的形成方法。
参照图3A，用ALD法或MOCVD法在硅基板11表面上经厚度约1nm的界面氧化膜12形成HfO2膜之类的高K电介质膜13，其膜厚为对应于2～3原子层厚度的约0.6nm。
例如，在用ALD法形成高K电介质膜13的情况下，在图3A的工序中设定基板温度为300℃，如图4的「阶段1」所示，间断地设置氮气进行的驱气工序，同时交替地将HfCl4等气相原料和H2O等反应剂供给到气相反应装置中。用这种工序最初将HfCl4分子化学吸附在所述硅基板11的表面上，更准确地说是化学吸附在所述界面氧化膜12的表面上，H2O气将化学吸附的这种HfCl4分子氧化，从而形成所述2～3原子层厚度的HfO2膜13。图4是本实施例中使用的处理序列图。在图3A的工序即图4的阶段1的工序中，反复进行11次这样的HfCl4分子的化学吸附和氧化处理，由此来形成所述HfO2膜，如前述所说明的那样，其膜厚为对应于2～3原子层厚度的约0.6nm。
再在对应于图4的处理序列图中的「阶段2」的图3B的工序中，在氮气气氛中600～700℃温度下对用图3A的工序形成的高K电介质膜13进行15秒钟的热处理，结果，就消除了所述HfO2膜13内的缺陷，并缓和了应力。进一步用这样的热处理使非晶质状态的HfO2膜结晶化。在例如图3A的工序后从ALD装置中取出被处理的基板并经真空气氛的基板传输室将其移动到别的处理室内，就能容易地进行图3B工序的热处理。
然后，在本实施例中，在对应于图4的处理序列内的「阶段3」的图3C的工序中进行ALD处理工序，在这样结晶化了的HfO2膜上再堆积上HfO2膜，使所述HfO2膜13生长；进一步在对应于图4的处理序列内的「阶段4」的图3D的工序中，再在600～700℃温度下对前面所堆积的HfO2膜13进行15秒钟的热处理，进行所述HfO2膜13的改质处理。
另外，如图中箭头所示，将图3C和图3D的工序反复进行所需的次数，从而如图5所示，得到了在所述硅基板11上经SiO2界面氧化膜12形成了膜厚约3.0nm的HfO2膜的结构。
图6是一幅TEM像，表示的是为激活由离子注入工艺导入到硅基板的杂质元素而在原来使用的1050℃温度下对这样得到的图5的结构进行10秒钟热处理后的状态。
如图6所示，即使在这样的高温热处理之后，HfO2膜13也维持着平坦的形态，不会发生像图1B所示的那种凝聚现象。在图6的TEM像上也应注意到解像有硅基板11的网格像。
图7所表示的是本实施例中形成高K电介质膜所使用的成膜装置的概略构成。
参照图7，成膜装置设置有用具备机械手传送机构(未图示)的真空传送室20相互结合起来的样品安装室(Load Lock)21、具备执行图3A或图3C的工序的ALD装置的堆积室22和执行图3B或图3D的工序的改质处理室23；将经样品安装室21导入的被处理基板送到所述堆积室22之后，根据需要在所述堆积室22与改质处理室23之间往复，最后返回到所述样品安装室21。
使用这种构成的成膜装置就能够连续反复进行必要次数的图2A～图2D所示的工序，而不会把被处理基板暴露于大气之中。
在本实施例中，使用保持在500～800℃优选600～700℃的温度并供给氮气而在氮气气氛中对基板进行热处理的热处理炉作为所述改质处理室23，用这样的热处理炉可以抑制气氛中的氧浓度，实质上就能够进行无氧气氛中的热处理。也可以根据需要如图中的虚线所示供给氧气，并控制气氛中的氧分压。
[第二实施例]
可是，在图6的TEM像上，在SiO2界面氧化膜12的一部分中产生有缺陷，对应于该缺陷，观察到在硅基板11中形成有反应层乃至迁移层。
虽然现在还不清楚该迁移层的组成，但是这可能是在图3B或图3D中的实质上不含氧的氮气气氛中的热处理时还原出非常薄的界面氧化膜12的一部分，其结果形成的Si和HfO2膜13中的Hf反应而形成硅化物。
对于此，图8所表示的是试样的FEM像。所述试样是在图7的改质处理室23中，使用图9所示的等离子体氮化处理装置30，在等离子体氮化处理装置30中于650℃下进行所述图3B或图3D的改质处理，此时将少量的氧气添加到处理气氛中而得到的。其中所示的构造是将所得到的试样进一步在1050℃下进行10秒钟高温热处理后的状态的结构。
参照图9，等离子体氮化处理装置30具有设置有排气口31A和保持被处理基板W的基板支座31B的处理容器31，并将氮气和氧气供给所述处理容器31，而且设置有用13.56MHz的RF波激励该气体而形成氮原子团和氧原子团的远程等离子体源32。在所述远程等离子体源32中，也可以供给He气或Ar气等稀有气体。使用这样的远程等离子体处理装置能够有效地抑制带电粒子随等离子体被进入到高K电介质膜中。
用图9的装置将被处理基板W上的HfO2膜等的高K电介质膜暴露于由所述远程等离子体源32形成的氮原子团或氧原子团中，结果，就将氮原子或氧原子导入到所述HfO2膜的表面上。
再参照图8，在本实施例中，在进行图3B或图3D的改质处理时，将氧添加到气氛中就能够稳定硅基板11和界面氧化膜12的界面，而且不会产生前面的图6上所见到的缺陷。
按照图8的结构，由于在这种改质处理时在气氛中包含有氧，所以在所述高温热处理之后所述SiO2界面氧化膜12的膜厚会增大到1.75nm。但是，在使用图9的装置进行改质处理时，通过适当控制氧分压就能够将这样的界面氧化膜12的增厚抑制到最小限度，即不产生所述SiO2界面氧化膜12的增厚。
按照本实施例，由等离子体处理装置30这样产生活性的原子团，并使用这种原子团来进行改质处理，所以，能够进行650℃以下的低温改质处理。这样，在低温下进行改质处理的情况下，可以除掉随着改质处理的高K电介质膜13的空位悬键(vacancy dangling bond)，可以抑制结晶化了的膜中的晶粒晶界的形成。
[第三实施例]
图10所表示的是将这样形成在硅基板上的高K电介质膜作为电容器绝缘膜的MOS二极管10的结构。在图10中，对前面说明过的部分标注相同的标号，并省略其说明。
参照图10，本实施例中，使用n型硅基板作为所述硅基板11，另外，在所述HfO2膜13上形成直径200μm的白金电极14。
图10中，构成所述MOS二极管10的SiO2界面氧化膜12和HfO2膜13在对应于图1A的刚堆积之后的状态下分别具有1nm和3nm的膜厚。
图11表示的是这样形成的MOS二极管10的漏电流特性。在图11中，①表示分两次由ALCVD堆积工序形成所述HfO2膜13，并在各次堆积工序中在氮气气氛中700℃温度下进行热处理后的结构的漏电流特性；②表示将所述①的结构进行1050℃下10秒钟的高温热处理之后的漏电流特性。③表示分11个循环用ALD法形成所述HfO2膜13，并在各堆积循环中在氮气气氛中700℃温度下进行过热处理的情况下的漏电流特性。图11中，纵轴表示漏电流，横轴表示对所述电极14施加的电压。
参照图11可知，分两次形成所述HfO2膜13的试样，所述高温热处理的结果使漏电流从①大幅度地增大到②。相对于此，分11次形成所述HfO2膜13的试样，即使进行所述高温热处理，漏电流也没有大的变化，反而从③到④稍微有些减少。
这样，由图11可知，虽然在形成HfO2之类的高K电介质膜13时未必限定于ALD法，但是分多次进行膜形成，每次都进行所述改质处理，就能够提高高K电介质膜13的漏电流特性，而且增加膜形成时的重复循环周期能够进一步提高膜质量。
图12A和12B表示的是图10的MOS二极管的制造时对所述改质处理的气氛进行种种变化的情况下所得到的MOS二极管的电容特性(C-V特性)。其中图12A表示对这样的MOS二极管进行1050℃下10秒钟的高温热处理前的特性；图12B表示所述高温热处理后的特性。
参照图12A、12B可知，①表示对应于前面的图1A的例子，用图2的ALD法形成厚约3nm的所述HfO2膜13，并在成膜后进行1050℃下10秒钟的高温热处理后，不能测定漏电流。这表示在HfO2膜中产生有图1B所示的凝聚。
图12A、12B中，②所表示的例子是像图4那样分3次形成所述HfO2膜13，每次0.6nm，此时，在NH3气氛中进行所述改质处理，但是，这种情况下，1050℃下10秒钟的高温热处理后测定的电容量也是零，认为这是因强还原性NH3气氛使HfO2膜13中产生了氧缺损所致。
相对于此，③所表示的是按照图4的处理序列分3次形成所述HfO2膜13，每次0.6nm，此时，在NO气氛中进行所述改质处理的情况。这种情况下，即使进行1050℃下10秒钟的高温热处理后，MOS二极管也还具有与热处理前几乎一样的电容量。
另外，图12A、12B中，④所表示的是按照图4的处理序列分3次形成所述HfO2膜13，每次0.6nm，此时，用前面图9说明过的远程等离子体氮化处理装置进行所述改质处理的情况。这种情况下，改质处理之后，MOS二极管的电容量进一步增大。
图12B中，⑤所表示的是按照图4的处理序列分3次形成所述HfO2膜13，每次0.6nm，在氮气气氛中进行过所述改质处理的情况的结果。
如上说明，按照本发明尽可能分多次进行高K电介质膜的形成，每次都进行改质处理，从而得到高温稳定性优良且电气特性好的高K电介质膜，但是图12A、12B的结果表示在分多次进行这样的高K电介质膜的形成时，只要是3次以上，实际上就能够得到膜质足够好的高K电介质膜。
图13表示的是在1050℃下10秒钟的高温热处理前后，比较在图3A～3D的工序中用氮气气氛中的热处理进行所述HfO2膜13的改质处理的情况下的热处理温度与所得到的HfO2膜13的平均膜厚的关系。
参照图13，一旦改质处理温度超过800℃，所述高温热处理前的平均膜厚稍微增大，改质处理时产生有先前图1B说明的HfO2膜的凝聚。另一方面，在用热处理进行所述改质处理的情况下，如果处理温度低于500℃，改质处理后的平均膜厚大幅度地增大，不能进行有效的改质处理。
相对于此，如果所述改质处理温度在500℃以上而低于800℃，所述高温热处理前后的平均膜厚几乎没有变化，能够维持相当平坦的形态。其中，依平均膜厚的观点来看，600～700℃的范围特别好。
[第四实施例]
图14表示的是本发明的第四实施例所使用的改质处理装置40的构成。图14中，前面说明过的部分标注同样的标号，并省略其说明。
参照图14，在改质处理装置40中，除将氮原子团或氧原子团从所述远程等离子体导入处理装置32导入到处理容器31中之外，还从管线33导入SiH4等硅化物气体，对形成在所述被处理基板W表面上的高K电介质膜等的表面进行改质。
将图14的改质处理装置40用于图7的处理室23，在例如图3B或图3D的工序中将具有Si-O-N键的层形成在所述HfO2膜13的表面，从而显著改善了对膜13的高温热处理的稳定性。
图15、16概略表示在650℃温度下进行这样的改质处理而形成的HfO2膜的结构。
参照图15，对应于图2A～2D的工序，在这样得到的HfO2膜中反复形成图16所示的HfO2层和SiON层，在图示的例子中，在HfO2的2分子层的上下形成一对SiON分子层。
如图15所示重复形成这样的结构，就能够在膜中形成含N-Si-O键的高K电介质膜。由于膜中的原子移动被SiON层挡住，所以在这样的膜中含N-Si-O键的高K电介质膜对高温热处理特别稳定，而且能够得到对包含于栅极电极的B(硼)等的扩散的优良的耐性。
图17表示的是在100MHz和1GHz下测定使用图10的MOS二极管中通过远程等离子体处理来把Si-N键导入到膜中的厚度为3nm的HfO2膜的情况下的电容量(C-V)特性。
参照图17，①、③是比较例，①表示用图2所示的ALD法形成3nm膜厚的HfO2膜13后在氮气气氛中700℃下进行过热处理的情况下的频率100kHz的C-V特性；③表示具有同样的HfO2膜13的MOS二极管的频率1MHz的C-V特性。即，在①和③，未进行1050℃、10秒钟的高温热处理。
相对于此，②表示按照图4的处理序列分3次形成3nm的HfO2膜13，每次0.6nm，各膜形成时用远程等离子体氮化处理把Si、O和N导入膜中进行所述改质处理，再将所得到的HfO2膜进行1050℃下10秒钟的高温热处理情况下的频率100kHz的C-V特性；④表示具有同样的HfO2膜13的MOS二极管的频率1MHz的C-V特性。
由图17可知，在频率为100kHz的情况下，②的特性与①的特性略同，而在频率为1MHz的情况下，进行过1050℃下的高温热处理的④的特性能够优于未进行高温热处理的③的特性。这就意味着在②、④的情况下尽管在膜中包含有可能使HfO2膜13的介电常数降低的SiON层，但是由于这种结构消除了膜中的缺陷，所以在特别实施了高温热处理的情况下能够得到胜过缺陷多的①或③的HfO2膜的电气特性。
图18表示的是比较图17的①或③的MOS二极管和②或④的MOS二极管的漏电流。其中，图18上的◆表示图10的MOS二极管中对用图2的ALD法形成厚3nm的HfO2膜仅在氮气气氛中进行700℃的热处理的情况下的漏电流；□表示在图4的处理序列中通过用图14的远程等离子体氮化装置进行所述改质处理而将N、O、Si导入膜中，再把这样改质的HfO2膜进行1050℃下10秒钟的高温热处理的情况下的漏电流。
由图18可知，分多次形成HfO2膜，再对其进行高温热处理的情况下，能够改善漏电流特性。
如上面所说明的那样，在本实施例中，这样也会由等离子体氮化处理装置40产生活性原子团，使用这样的原子团来进行改质处理就能够进行650℃以下的改质处理。在进行这种低温下的改质处理的情况下，能够抑制伴随改质处理的高K电介质膜13的结晶化，同时能够抑制结晶化的膜中的晶粒晶界的形成。结果，能够阻断沿这种晶粒晶界形成的漏电流通路。
这时，按照本实施例，由于将形成非晶质膜的SiON单体导入到高电介质膜中，所以即使进行杂质激活处理所使用的高温热处理之后，也可以抑制高K电介质膜的结晶化，并能够抑制伴随晶界形成的漏电流通路的形成或界面能级等缺陷的形成。
[第五实施例]
图19A～图19F表示本发明的第五实施例的半导体器件的制造工序。
参照图19A，在p型硅基板51中形成划分元件区51A的元件分离区51B，再在图19B的工序中将As或P离子注入到所述元件区51A内，由此形成隧道掺杂区(channel dope)51a。
进一步在图19C的工序中，在图19B的结构上与所述界面氧化膜12对应地同样形成厚约1nm的热氧化膜，之后，在其上按照图4的处理序列形成约3nm厚的HfO2等高K电介质膜，由此形成栅极绝缘膜52。
然后，在图19D的工序中，在所述栅极绝缘膜52上一样地堆积多晶硅膜，通过将其构图来形成多晶硅栅极电极53。本实施例中，所述多晶硅栅极电极53具有0.1μm以下的栅极长度。
进一步在图19D的工序中，掩住所述多晶硅栅极电极53，进行As或P的斜罩注入，再连续进行外延注入，由此在所述元件区51A中、所述栅极电极53的两侧形成源极扩展区51b和漏极扩展区51c。
然后在图19E的工序中，在所述栅极电极53的两侧形成侧壁绝缘膜53a之后；在图19F的工序中，为了掩住所述栅极电极53和侧壁绝缘膜53a，离子注入As或P，由此形成源极区51d和漏极区51e。
本实施例中，在图19C的工序中形成所述栅极绝缘膜52中的高K电介质膜时，重复地夹杂先前图4所说明的改质工序来进行该工序。这时，阶段1和阶段3既可以是ALD工序，也可以是MOCVD工序；而阶段2和阶段4既可以是氮气气氛中的热处理，也可以是添加了氧的氮气气氛中的热处理，或者，既可以是等离子体氮化处理，也可以是添加了氧的等离子体氮化处理，还可以是添加了SiH4等Si化合物和氧的等离子体氮化处理。
通过这样形成所述栅极绝缘膜52，能够提高所述栅极绝缘膜52中的高K电介质膜对热处理的耐受性，即使用高温热处理来激活被注入到所述源极扩展区51a、漏极扩展区51b、源极区51d和漏极区51e的As或P等杂质时，也不会发生膜的凝聚等缺陷的形成。而且即使在所述高温热激活处理之后，这样形成的栅极绝缘膜52仍然能维持漏电流小且C-V特性好的优良电气特性。
在以上的说明中，是用ALD法来形成HfO2膜，但是也可以用MOCVD法来形成，这时，可以使用TDEAH、TDMAH等作为有机金属原料。用ALD法来形成HfO2膜时的原料不限定于HfCl4，也可以使用TDMAH等。
本发明中，高K电介质膜不限定于HfO2膜，可以使用ZrO2膜、Al2O3膜、Ta2O5、Y2O3等金属氧化物或过渡金属氧化物，还可以使用稀土类氧化物、HfSiO4、ZrSiO4膜等过渡金属或稀土金属的硅酸盐、或它们的铝酸盐。
前面在图7中说明了使用叶片式处理装置一面在各个处理室内移动基板一面进行高K电介质膜的形成和改质处理，但是，也可以在同一个处理装置中一面切换处理气体一面进行所述高K电介质膜的形成和改质处理。
本发明中，也可以在氮气中添加氧、NO、O3、SiH4、Si2H6、NH3、H2、He的任一种气体的气氛中进行所述改质处理工序。
另外，在以上的说明中，将高K电介质膜用作高速半导体器件的栅极绝缘膜的例子，但是本发明也可以适用于把高K电介质膜用作电容器绝缘膜的DRAM的制造。
以上说明了本发明的优选实施例，但是并不限定于这些特定的实施例，在本发明的宗旨内可有各种各样的变形·变更。
产业上的利用可能性
按照本发明，在把高K电介质膜用作栅极绝缘膜的半导体器件的制造工序中，分多次进行所述高K电介质膜的形成，再在所述多次形成工序的各次工序中在氮气气氛内进行改质处理，从而能够减小高K电介质膜中的应力，并能消除膜中的缺陷。结果，可以得到对在把这样的高K电介质膜用作栅极绝缘膜的半导体器件的制造工序中高K电介质膜形成后进行的用离子注入工序导入到基板内的杂质元素的高温激活热处理工序稳定的高K电介质膜。特别是采用在添加了氧的氮气气氛中的热处理工序来进行所述改质处理工序，就能够使半导体基板与高K电介质膜的界面稳定，而且还能抑制高K电介质膜中的氧缺损的发生。反复把Si、O、N导入高K电介质膜的膜中，进一步提高了对高温热处理的稳定性，同时减低了漏电流。这样，把Si、O、N导入膜中的高K电介质膜能够有效地阻止栅极电极中包含的B(硼)等杂质元素的扩散。另外，还可以用等离子体处理来进行所述改质处理。

Claims (20)

1.一种电介质膜的形成方法，在基板表面上形成电介质膜，其特征在于包括如下工序：
在所述基板表面上分多次形成所述电介质膜的工序；
在所述分多次进行的电介质膜形成工序的各个工序中，在以氮气为主的气氛中对所形成的电介质膜进行改质的处理工序。
2.根据权利要求1所述的电介质膜的形成方法，其特征在于，所述气氛还包含氧。
3.根据权利要求1所述的电介质膜的形成方法，其特征在于，所述气氛还包含Si化合物的气相分子。
4.根据权利要求1所述的电介质膜的形成方法，其特征在于，在所述热处理工序中，在所述气氛内还添加有由NO、O3、SiH4、Si2H6、NH3、H2和He构成的组中选择的一种或多种气体。
5.根据权利要求1所述的电介质膜的形成方法，其特征在于，所述改质处理工序由热处理工序构成。
6.根据权利要求5所述的电介质膜的形成方法，其特征在于，在大于等于500℃小于800℃的温度下进行所述热处理工序。
7.根据权利要求5所述的电介质膜的形成方法，其特征在于，在600℃～700℃的温度下进行所述热处理工序。
8.根据权利要求1所述的电介质膜的形成方法，其特征在于，所述改质处理工序由等离子体处理工序构成。
9.根据权利要求8所述的电介质膜的形成方法，其特征在于，所述等离子体处理工序包含把所述电介质膜暴露于氮原子团中的工序。
10.根据权利要求9所述的电介质膜的形成方法，其特征在于，所述等离子体处理工序还包含把所述电介质膜进一步暴露于氧原子团中的工序。
11.根据权利要求10所述的电介质膜的形成方法，其特征在于，所述等离子体处理工序还包含把所述电介质膜进一步暴露于Si化合物分子中的工序。
12.根据权利要求8所述的电介质膜的形成方法，其特征在于，所述等离子体处理工序由远程等离子体处理工序进行。
13.根据权利要求8所述的电介质膜的形成方法，其特征在于，在650℃或其以下的温度下进行所述等离子体处理工序。
14.根据权利要求1所述的电介质膜的形成方法，其特征在于，用ALD法进行所述分多次进行的电介质膜形成工序的各个工序。
15.根据权利要求1所述的电介质膜的形成方法，其特征在于，用MOCVD法进行所述分多次进行的电介质膜形成工序的各个工序。
16.一种半导体器件的制造方法，该半导体器件具备：基板、形成在所述基板上的高K介质栅极绝缘膜、形成在所述高K介质栅极绝缘膜上的栅极电极和在所述基板中形成在所述栅极电极两侧的一对扩散区；其特征在于，该制造方法包括如下工序：
在所述基板上分多次形成所述高K介质栅极绝缘膜的工序；
在分多次进行的高K电介质膜形成工序的各个工序中，在以氮气为主的气氛中对所形成的高K电介质膜进行改质的处理工序。
17.根据权利要求16所述的半导体器件的制造方法，其特征在于，所述气氛还包含氧。
18.根据权利要求16所述的半导体器件的制造方法，其特征在于，所述气氛还包含Si化合物的气相分子。
19.一种半导体器件，该半导体器件具备：基板、形成在所述基板上的高K介质栅极绝缘膜、形成在所述高K介质栅极绝缘膜上的栅极电极和在所述基板中形成在所述栅极电极两侧的一对扩散区；其特征在于，所述高K介质栅极绝缘膜具有重复叠层高K介质分子层和SiON分子层的构造。
20.根据权利要求19所述的半导体器件，其特征在于，所述高K介质分子层是选自金属氧化物、过渡金属氧化物、金属硅酸盐和金属铝酸盐的任一种。
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