CN1577842A - 芯片装置 - Google Patents

芯片装置 Download PDF

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Publication number
CN1577842A
CN1577842A CNA2004100587553A CN200410058755A CN1577842A CN 1577842 A CN1577842 A CN 1577842A CN A2004100587553 A CNA2004100587553 A CN A2004100587553A CN 200410058755 A CN200410058755 A CN 200410058755A CN 1577842 A CN1577842 A CN 1577842A
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China
Prior art keywords
circuit
chip
lead frame
integrated
chip apparatus
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Granted
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CNA2004100587553A
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English (en)
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CN100367499C (zh
Inventor
F·塔伊彻
J·-P·福斯特纳
G·里普佩尔
S·韦伯
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN1577842A publication Critical patent/CN1577842A/zh
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Abstract

一先进的芯片装置包含一芯片(10)，其中一集成电路以及一导线架(12)被整合，包含一支撑区(18)于芯片(10)且其中一线路(22)系被构造形成一部分的集成电路之匹配电路。本发明基于发现一导线架外壳之导线架(12)本身可能被使用以形成线路，例如分布线路，片状线路或者一线圈，其可能接着再次被使用作为一部分的集成电路之匹配电路。此方法，在一比较简单的方式中，一芯片(10)包含一集成电路伴随一匹配电路可能被容纳于一壳体且因此同时一高品质的匹配电路之零件可能被实现，其藉由导线架(12)中的线路(22)被形成。

Description

芯片装置
技术领域
本发明关于芯片装置且特别是关于一芯片中整合之电路之匹配电路之设施伴随芯片进入一壳体。
背景技术
鉴于通讯技术领域中之继续技术发展，例如行动无线通讯，有一继续成长的集成半导体电路的需求，其系一方面被最佳化关于他们的壳体需求且另一方面关于他们的成本。除了在流行的行动无限应用中根据GSM，PCM，PCS，CDMA，UMTS，US-TDMA标准相对高讯号频率必须被处理，有单独整合的半导体电路之一最佳的高频率匹配的问题存在，例如高频率匹配在整合的高频率功率放大器之输入侧以及在输出侧。
高频率功率放大器需要特定的加载阻抗以可以有效转变消耗的DC功率成为一高频率输出功率，基于他们的应用以及特别是依赖于有用的功率提供，所欲之输出功率以及调整方法被使用或者类似。一般上，在高频率技术中，不同电路区块之间的接口系关联于一波形阻抗50ohm。如果对于一高频率放大器，一加载阻抗脱离50ohm被需要，则一般上转换电路被使用，其转换此标准化的高频率放大器之参考阻抗50ohm成为一特定加载阻抗以一频率选择的方式。对于此，一般分布的惰性网络系被使用。
第4图显示一范例，一功率晶体管之输出转换电路，当其如范例被使用在一行动无限装置中。T1代表一功率晶体管其发射体被连接到地表，其集电器被连接到一DC电压源V1经由一感应组件L1且到其控制输入高频率输入讯号HF IN被放大而被使用。在功率晶体管之集电器，放大的输出讯号造成。藉由功率晶体管T1之集电器形成之此输出系被对应于一参考阻抗50ohm藉由一输出匹配网络OMN。
特别是在手提装置中，例如行动电话，该处低电池电压V1为有用于供应一功率晶体管，输出站加载阻抗脱离参考阻抗50ohm。第4图中的匹配网络OMN如一范例包含三个电容器C1，C2，C3以及两个感应器或者感应组件，分别地，为TRL1以及TRL2。感应组件TRL1，TRL2以及电容器C3系以此顺序被连接于功率晶体管T1之集电器以及一阻抗匹配的输出之间，在其终点该放大输出讯号RF OUT系被输出。一方面在阻抗TRL1以及TRL2之间且另一方面感应器TRL2以及电容器C3，电容器C1或者C2，分别地，被连接到地表。
输出站加载阻抗以及参考波型阻抗之间的转换率系典型地为0.05。为了可以在低损失下实现此高转换率，在匹配网络OMN中一高品质的匹配组件系被需要。当品质，特别是那些感应器TRL1以及TRL2，在一半导体芯片上系经常为低的，这些转换电路在实际功率放大器装置或芯片外部系一般上被实现，分别地。
一团的一功率放大器装置以及一联合外部匹配电路的实现之一个范例被描述于DE 19534382 A1。特别是，一单微影集成电路具有一微波功率放大器具有一匹配电路使用分布线路系被描述于其中。在一单一基板上，多站放大器电路之FETs与装置以及匹配电路之分布线路均被提供。DE 19534382 A1之一单微影集成放大器之设定系以一简化方式被说明于第5图中。在一普通基板900上，端点面902，904，芯片端面906，908，以及一分布线路910系被提供。在芯片端面906以及908上，功率放大器912以及匹配电路之装置914系分别被安装。结合金属线916，918，920，922提供一电连接分别地于端点面902，904，功率放大器912或者匹配装置914与分布线路910之间。
DE 10152652.0描述一功率放大器芯片，其系被容纳于一导线架壳体中伴随一输入以及输出匹配电路，其中功率放大器芯片以及一匹配电路芯片系被安装于一普通芯片岛上。一功率放大器芯片整合于一导线架壳体中，以此一方式系被说明于第6图中。导线架系被构造成为接触地930，932以及一普通芯片岛934。在普通芯片岛934上，线路放大器芯片936以及一整合惰性匹配模块938系被安装。在接触地930，932，功率放大器芯片936以及匹配模块938之间的电连接系藉由结合金属线940，942以及944来制造。构造系以一塑料材料946来维持在一起，其作为一覆盖层以及藉其导线架930，932，934以及装置936，938以及结合金属线940-944系被形成在一起。第6图进行的缺点就是难以获得具有一高品质的匹配组件，特别是具有高品质的感应器。
发明内容
本发明的目的系提供一根据一芯片具有一集成电路以及集成电路之一匹配电路之一整合成为一芯片装置的原理而可能较容易被提供。
本发明系藉由一根据权利要求第1项而被达成。
一先进的芯片装置包含一芯片，其中一集成电路系被整合以及一导线架包含芯片之一支撑区且其中一线路系被构造形成一部份的集成电路之匹配电路。
本发明系基于发现一导线架壳体之导线架可能被使用以形成线路，例如一分布线路，一片状线路或者一线圈，其可能再次被使用作为一部份的集成电路之一匹配电路。此方法，在一相对简单的方法中，一芯片包含一集成电路伴随着集成电路之一匹配电路可能被容纳于一壳体中且在其，同时一高品质的匹配电路之那部分可能被实现，其系藉由导线架其中的线路来形成。
需要一高品质的匹配电路之零件可能被提供于导线架本身之中事实上的另一个优点为导线架之结构已经需要一操作步骤无论如何在导线架基础壳体中，因此没有额外的操作被需求。
此外，在导线架基础的外壳中，导线架无论如何占据垂直方向的壳体且一般上包含足够的侧面方向的可用壳体，因此可以实现导线架中的线路，如根据本发明的目的，实质上没有额外的壳体需求，但其甚至可能被降低。
附图说明
在下列中，本发明之较佳实施例系更加详细地被解释伴随参考随附的图示，其中：
第1图显示整合于一壳体中根据本发明实施例之一功率放大器伴随一匹配电路之一纲要剖面图；
第2A-K图显示一芯片装置之随后状态于一纲要性剖面图中其系被设定于随后处理步骤之后以制造根据本发明之一实施例之芯片装置；
第3A-B图分别显示整合于一壳体中伴随一匹配电路之一功率放大器芯片之一上视或下视图；
第4图显示具有一典型输出转换电路之一功率放大器之电路图；
第5图显示一功率放大器芯片以及一匹配电路之一传统结合之一概略剖面图；以及
第6图显示具有一匹配魔组织一功率放大器芯片之一整合到一导线架壳体中之传统解决之一纲要剖面图。
在本发明更加详细参考图示被解释之前，必须注意的是，图标中相似组件系被提供具有相似的参考符号且那些组件之一重复的描述系被省略。
具体实施方式
第1图概略显示根据本发明实施例容纳于一单一壳体伴随一结合的匹配电路之集成电路之一实施例。
集成电路系整合于一芯片10中且例如为一功率放大器或任何其它电子电路。匹配电路被提供作为一阻抗或者另外类型的配对在集成电路之输入或输出上，例如对于设定功率放大器之波形阻抗到一数值为50ohm。
芯片10系被安装于一导体层12之一主要侧12a之上。导体层12系被构造成为几个区域，即金属岛14，16，芯片岛或支撑区18，20，分别地，以及一线路22。芯片10系被安装于芯片岛18之主要侧12a之上。
集成电路之匹配电路在芯片10中系一方面从第1图之适当装置被结合，另一方面仅一个被指示作为一范例在24以及线路22上。导线架12中之线路22之侧面导线，其剖面部分以及接触点系以适当方式被选择以作为一感应组件，一片状线路，一分布线路或者其类似具有适当电子特性的，例如一预先决定的电阻数值，一预先决定的感应，一预先决定的讯号运作时间或者匹配电路其中类似的。换句话说，线路22在匹配电路中藉由被执行以侧面地引导电流而接管一电子功能，即在导线架平面其中。装置24可能例如为一SMD装置(表面安装装置)，例如一电容器。
为了形成一匹配电路，例如一输出转换电路，从装置24以及线路或者线路22，分别地，例如晶体管以及电容器组件系被安装如装置24到导线架12之上而感应器以及传导追踪组件系被提供作为导线架12之结构22。晶体管以及电容器装置可能以一成本有效的方式被提供于一惰性SI整合中。
结合金属线26，28，30以及32提供一电连接于金属岛14以及芯片10之间，芯片10以及线路22，线路22以及装置24或者装置24以及金属岛16之间。分别地。
导线架12之结构具有物理分隔的区域14，18，22，20以及16，芯片12以及装置24以及连结的结合金属线26-32系被维持在一起藉由一塑料材料34，其系被使用作为一覆盖层/涂布层或者一结合且藉其此结构系被铸造而成。
层12之一主要侧12b或者导线架12对面的主要侧12a系与覆盖层之塑料材料34齐平而延伸到层12之非构造的区域中直到此主要侧12b。主要侧12b形成芯片装置或者壳体之所谓的足点，分别地，说明于第1图中且作为一安装侧藉其第1图之芯片装置系被安装到一板或者另外的支撑基板且系电连接到板上或支撑基板上之适当配置的接触端面，分别地，经由金属岛14以及16。特别是，在与塑料材料34相邻的足点上，导线架之结构区域14，16，18，20以及22系被曝光。以此侧12b，第1图之导线架壳体可能被安装到一板，其中至少金属岛14以及16之配置对应板上接触地之一配置，金属岛14以及16可能被焊接到其上。芯片岛14以及16可能举例被连接到板上的地端且远离电子连接以用作热消散。亦，线路22可能为电连接到板上之一接点端面在一特定位置上沿着其方向，其上第1图之壳体被安装，当电路设计标出此一外部端用于匹配电路中。
图示说明于第1图中之壳体对应于一所谓的TSLP壳体(薄小无导线封装)，即其可能藉由提供用于此壳体类型之制造步骤被制造。一个制造根据第1图之一壳体的实施例系藉由参考第2A-2L图被描述。一特别的实施例其中显示线路22如何可能被使用作为一部份的匹配电路于导线架12中系藉由参考第3A-3B图而被描述。
在下列叙述中，参考第2图，一芯片装置之一可能的制造程序之一实施例系被描述包含一芯片安装于一芯片岛上以及一线路形成于导线架其中。第2图之描述因此亦容易被延伸到第1图芯片装置之一制造中，虽然在第2A-2L图中，匹配电路之装置没有芯片岛被显示。
在制造中，首先一基底50包含铜系被作为一开始。在铜基底50上，藉由一直流电程序首先导线架被形成，目前实例分别包含芯片或者安装岛52，对于芯片包含集成电路，其中匹配电路系被提供，且匹配电路之装置以及从一或几个线路52，其系代表一部份的匹配电路。为了构造导线架在铜基底50之一主要侧50a上，首先一光罩系被使用且在导线架之被构造的区域52以及54配置之位置中被移除，其中在直流电制造程序期间镍之材料生长之后系被执行。
材料生长系于光罩较晚被执行，因此镍结构或者线路54以及芯片岛52，分别地，包含一蘑菇状的剖面区域，如第2A图中所示。此步骤提供一较少的品质的电子功能由线路54所接管，保证，然而，在另一方面来说，导线架52，54藉由拓宽56在部分的导线架面对远离主要侧50a之一好的固定于壳体中。
之后，导线架结构52，54之一镀金步骤58，60以及镍材料生长所需要的光罩的移除系被执行。在芯片岛上接着藉由冲模结合芯片62其中集成电路被整合为了匹配电路被提供而被安装或附加，分别地，到镀金的芯片岛52上。在从其远离之芯片岛上(未显示)，匹配电路之装置系被安装，如果可行。
状态设定于上述方法步骤中系被说明于第2A图中。代替上述导线架结构52以及54在光罩厚度之后之镍之材料生长亦使用一直流电程序其中材料生长系较早被终止，即此镍生长终止于光罩之中或者光罩厚度之中，分别地。在此例中，导线架结构52以及54之剖面部分接着对应于几乎垂直的随后被移除的光罩之侧边缘，藉其电功能由线路54代表而达成一较高的品质。
随后，电组件，类似芯片62，线路54或未显示于第2A图中之组件，例如整合于芯片62中的电路之匹配电路之可能的装置系以一特定的方式使用一金属线结合安装藉由结合金属线64电连接到彼此。至此造成的结构系显示于第2B图中。
第2B图之结构系被完成于一随后的方法步骤中具有一覆盖层66。此方法步骤较佳地发生在一增加的温度层级中，其中一塑料材料形成一覆盖层66系被液化。在温度层级之最终的降低中，塑料材料之一浓度以及一固化造成，因此接着导线架结构52以及54系被不动地固定于塑料材料中，因为他们的蘑菇状结构。当结构在铜基底50上以塑料材料66模造时，塑料材料66穿过直到铜基底50之主要基底54a以紧靠于此主要侧50a上。在以覆盖层完成之后设定之状态系被说明于第2C图中。
第2D图仅说明在提供一雷射记号58之后在覆盖层66面对远离铜基底之主要侧50a之侧造成的状态以举例确认导线架52，54，芯片62以及结合金属线54之结合。记号68可能举例亦包含一连串的数字以可以从彼此区分个别结构，其系被形成于一单一基底50上之彼此隔壁。
在一随后的步骤中，铜基底50系藉由一铜蚀刻步骤来移除，藉其芯片岛52以及剩余部分的导线架，例如线路54，系被制造为可用于一曝光端点面70之一后来的接触。端点面70之一具体实例参考第3B图将被详细讨论于下，系因此一基本的平面其系由覆盖层66之塑料材料之区域以及导线架52，54之构造区域之镍材料所组成。结果结构系显示于第2E图中。
在铜蚀刻步骤之后，较佳地导线架52，54之暴露区域在至此形成的结构之现在暴露的端点面70之一镀金系被执行。结果铜电镀在导线架52，54之暴露的区域中系被指示在72或74，分别地，在第2F图中。
在参考第2A-F图描述之方法步骤之后，根据本发明之典型芯片装置已经可使用。参考第2G-2L图所述之随后的方法步骤仅参考一更有利的处理用于制造一复数的芯片装置具有一导线架包含一匹配电路之一线路。在下列图标之叙述中，假设前述程序步骤被执行于一复数的位置之一延伸的铜基底50以产生一复数的结构如第2F图所示。那些芯片装置的全部整体系经由覆盖层66之塑料被连接。
覆盖层66之主要面面对端点面70系现在被层压或黏附，分别地，到一箔片76上在一方法步骤中。箔片76用于全部芯片装置之粘着于覆盖层66中，因此当每一芯片装置，如已经被显示于第2F图中，藉由一切片步骤在一随后方法步骤中被分成小块时亦被维持在一起。此方法站系显示于第2H图中藉由切割方向78以及80。
如此被切片之芯片装置系接着被测试结构缺陷例如藉由一光学装置82如显示于第2I图中或者藉由其它测试装置，例如触觉测试装置，以及接着测试他们的电子功能于一另外的方法步骤中，藉由一电子测试装置接触导线架52，54之镀金暴露的区域以测试探针84，如其被指示于第2J图中。藉由一适当的UV辐射86，在其之后正向测试或者无缺陷的芯片装置系被从箔片76释放且在一随后的方法步骤中容纳在一转运封装88中以运送到客户，如第2L图所示。
第3A以及3B图显示根据本发明之一芯片装置之一实施例，其中一功率放大器芯片其中一功率放大器或者一功率放大器电路系被整合，分别地，被安装到一导线架之一芯片岛，其中在芯片岛隔壁的导线架中更有一线路被形成，其形成部分的匹配电路，特别是一功率放大器电路之一阻抗匹配电路。
第3A以及3B图之芯片装置系基本上设定如根据第2A-L图或者第1图之芯片装置且实质上包含塑料材料100形成覆盖层，导线架102之构造区，功率放大器芯片104以及不同的装置106a，106b，106c以及106d，其接管芯片104中功率放大器之匹配电路中的电子功能。为了显现全部主要细部于第3A以及3B图中显示上视(第3A图)或者底部(端点面)(第3B图)，覆盖层之塑料材料100作为下层区域系不被说明如隐藏。
第3A以及3B图之功率放大器芯片装置之导线架包含四个支撑区域102a-102d对匹配电路之装置106a以及106d以及一支撑区域或者一芯片岛102e，分别地，对于功率放大器芯片104以及一线路102f，一金属岛102g作为一供应电压端点以及另外的金属岛102h，在其中亦有一金属岛作为一50奥姆的高频率讯号输出。
一些部分的线路102f系被引导为弯曲状在导线架层平面其中以产生适当的线路长度或者讯号运作时间周期，分别地，提供适当的阻抗数值或者类似的。线路102f之一些循环系藉由结合金属线连结起来，如其作为实例指示于106。此可能被使用以调谐匹配电路。连结线路102f之两点之结合金属线的数量可能被改变以设定结合金属线连接于此点之阻抗。线路102f之一终点108在安装芯片装置于一板上例如作为一额外的电压供应端。支撑区域102a-102d之一或者，无论如何，一另外的点在线路104f上可能作为一阻抗对应50奥姆的高频率输出，依赖于下层的匹配电路设计。
装置106a-106d可能举例来说为电容器，就像例如硅MIS或者MIM电容器(MIS＝金属绝缘半导体；MIM＝金属绝缘金属)。功率放大器电路之端点以及芯片岛104以及金属岛102h以及线路102f以及金属岛102g之间的连接以及金属岛102h，线路102f以及装置106a-106d之间的电子连接系被一分别结合的金属线或者多个平行的运作结合金属线实现，如其以黑色线被说明于弟3A图中，其中再次结合金属线之数量的变化对于每一个电子连接可能被使用以设定连接之阻抗。
第3B图说明底视图或者芯片装置之端点面，分别地。底视图系由覆盖层100之塑料以及导线架102之暴露(镀金的)结构的铜区域所组成。如上所述，除了金属岛102h，102g之外，亦有其它部分的暴露导线架作为一电子连接到对应配置的一板之接触端面之端点位置，例如芯片或安装岛，分别地，为102a，102b，102c，102d以及102e作为接地，安装岛102e作为一讯号输出以及线路102f之终点108作为一额外的供应端。在这些位置中，接触端面系被配置于板上，第3A，3B图之芯片装置系被安装于其上。
上述实施例可能被使用以联合一MMIC壳体(MMIC＝单微影微波集成电路)之低制造成本以及输出转换地乱之工具以一有效方式，因此一成本以及因此一有竞争力的优点造成。Infineon之公司之TSLP壳体允许一弹性的壳体设计在目前为止如不同的线路构造可能被实现于壳体中，其可能被使用作为片状线路或者感应器，分别地，具有一相对较高的品质于输出转换电路中。上述实施例因此具有在制造中低金属话损失之优点，他们制造一多芯片的安装，他们制造一制造成本降低，他们制造一功率放大器装置具有一好的热阻抗之制造等等，且全部再客户端具有一低执行所需要的努力。
特别是，对于实施上述实施例于已经存在的制造部位无额外的改变被需求以使用本发明，如举例使用在制造一TSLP壳体之技术无论如何允许半导体安装岛之一自由设计。换句话说，上述上层构造系可兼容非被安装以及被释放程序且并不需要新的步骤或者工具，分别地，以一唯一使用的芯片。因此可想象的安装结构于导线架，其对应于传导性的轨迹且可能被使用如不需要遭受这些制造部位成本上的改变。安装之设计以及功能性的面可能藉由便宜的光程序被执行。从传导轨迹之结构精确造成分界线。为了说明根据上述实施例之一输出转换电路，其可能因此为明显的，如上所述，安装晶体管以及电容器组件作为装置较佳地在一惰性Si中整合到导线架，例如藉由芯片以及金属结合安装，且设计感应性以及传导性的轨迹组件作为导线架之结构。
第2A-2L图之上述制造实施例在目前为止为不利的是每一个别的芯片装置之一测试系仅可能在一完全安装之后，即仅在步骤2i。分别被封装或者壳体之上层结构所制约，制造流程中在第2A-2L图之后，无论如何，没有ESD损害可能造成(ESD＝静电放电)，另一方面，无论如何，功能调整系非常地困难。唯一的调整可能性为导线架中的程序后的传导性轨迹构造，例如导线架中线路个别部位之切断。
上述实施例之优点在于一非常好的结合到安装基板(板)，其上上述实施例之芯片装置系被安装到他们的端点面，相较于其它方面的传统陶瓷上层结构，例如根据DE 19534382 A1。好的热结合的原因在于从放大器芯片之背侧经由直流电制造的芯片岛到安装基板之短热路径。
参考组件符号列表
10芯片
12导线架
14金属岛
16金属岛
18芯片岛
20芯片岛
22线路
24装置
26结合金属线
28结合金属线
30结合金属线
32结合金属线
50铜基座
50a主要侧
52芯片岛
54线路
56扩大
58镀金
60镀金
62芯片
64结合金属线
66覆盖层
68作标志
70端点面
72镀金
74镀金
76贴箔
78切
80切
82光学测试装置
84电子测试器
86 uv辐射
88封装
100覆盖层
102导线架
102a支撑区
102b支撑区
102c支撑区
102d支撑区
102e芯片岛
102f线路
102g金属岛
102h金属岛
104功率放大器芯片
106a-106d装置
900基板
902终端面
904终端面
906芯片端面
908芯片端面
910分布线路
912功率放大器
914匹配装置
916结合金属线
918结合金属线
920结合金属线
922结合金属线
930接触地
932接触地
934芯片岛
936功率放大芯片
938整合惰性匹配模块
940结合金属线
942结合金属线
944结合金属线
946塑料材料

Claims (10)

1.一种芯片装置，包含：
一芯片(10，62，104)具有一集成电路整合于其中；
一导线架(12，52，54，102)包含一支撑区(18，52，102e)用于芯片(10，62，104)且其中一线路(22，54，102f)被形成而造成一部份的一匹配的电路用于该集成电路。
2.根据权利要求第1项所述之芯片装置，其中该集成电路形成一功率放大器且该匹配的电路被提供用于一输入或输出的阻抗匹配。
3.根据权利要求第1或第2项所述之芯片装置，其中该芯片(10，62，104e)以及该导线架(12，52，54，102)系由一塑料材料(34，66，100)来模造，因此该导线架之一主要侧(70)面对该导线架之一主要侧，该芯片(10，62，104e)系被支撑于其上，系实质上与该塑料材料齐平以形成一实质上平面的芯片装置之接点端侧面。
4.根据权利要求第1至第3项其中一项所述之芯片装置，其中该线路(22，54，102f)系藉由一结合金属线(28，64)被连接到该集成电路。
5.根据权利要求第1至第4项其中一项所述之芯片装置，其中该线路(22，54，102f)形成一感应组件。
6.根据权利要求第1至第5项其中一项所述之芯片装置，其中该导线架(12，102)更包含一另外的支撑区(20，102a-102d)用于一装置(24，106a-106d)以形成该集成电路中该匹配电路的部分。
7.根据前述权利要求其中一项所述之芯片装置，其中该导线架系一导体平面构成于该支撑区(18，52，102a)以及该线路(22，54，102f)之中。
8.根据前述权利要求其中一项所述之芯片装置，其中该线路(42，54，102f)系执行于剖面部分以及侧面方向以形成一阻抗数值或一讯号运作时间，其系被最佳化于该匹配的电路。
9.根据前述权利要求其中一项所述之芯片装置，其中该线路(22，54，102f)系在两间隔的点上被接触以被连接到一点上之该匹配电路之一剩余部分以及连接到其它点之该芯片或者以医不同方式被连接到该匹配电路之剩余部分以接管这些点之间一部份的该匹配电路之一电子功能。
10.一种制造一芯片装置的方法，包含：
提供一基座(50)具有一导体平面于该基座(50)之主要面(50a)上；
构造该导体平面成为一支撑区(52)以及一线路(54)以获得一导线架(52，54)；
安装该芯片(62)到该支撑区(52)，其中在该芯片(62)中，一集成电路被整合且其中该线路形成一部份的该集成电路之匹配电路。
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CN104601124B (zh) * 2013-10-31 2017-10-10 三菱电机株式会社 放大器

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