CN1866515A - 包含顺序堆叠的模拟半导体芯片和数字半导体芯片的sip型封装及其制造方法 - Google Patents

包含顺序堆叠的模拟半导体芯片和数字半导体芯片的sip型封装及其制造方法 Download PDF

Info

Publication number
CN1866515A
CN1866515A CNA2006100848891A CN200610084889A CN1866515A CN 1866515 A CN1866515 A CN 1866515A CN A2006100848891 A CNA2006100848891 A CN A2006100848891A CN 200610084889 A CN200610084889 A CN 200610084889A CN 1866515 A CN1866515 A CN 1866515A
Authority
CN
China
Prior art keywords
semiconductor chip
chip
analog
ground plane
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006100848891A
Other languages
English (en)
Inventor
菊岛公弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN1866515A publication Critical patent/CN1866515A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Position Fixing By Use Of Radio Waves (AREA)

Abstract

在一种半导体封装中，在其内形成具有接地层的布线板。在接地层上或者上方设置模拟半导体芯片，并且在模拟半导体芯片上或者上方设置数字半导体芯片，使得数字半导体芯片的衬底面向模拟半导体芯片。

Description

包含顺序堆叠的模拟半导体芯片 和数字半导体芯片的SIP型封装及其制造方法
技术领域
本发明涉及一种包含模拟半导体器件和数字半导体器件的系统级封装型(SIP)封装，其可以有利地用于接收和处理例如全球定位系统(GPS)中的射频(RF)信号，并且还涉及该SIP封装的制造方法。
背景技术
在GPS信号接收装置中，同时需要射频(RF)信号处理单元和基带信号处理单元以接收和处理GPS信号。也就是说，在RF信号处理单元中，GPS信号被降频转换为中频信号，然后对该中频信号进行解调，从而产生模拟基带信号。该模拟基带信号被转换为数字基带信号，然后将该数字基带信号输出到基带处理单元。接着，在基带信号处理单元中，对数字基带信号进一步进行处理，从而产生GPS位置信息信号。
RF信号处理单元被形成为模拟半导体封装，而基带信号处理单元被形成为数字半导体封装。这些半导体封装被贴装在GPS信号接收装置的布线板上，该布线板上还贴装有其他各种单元。
因此，GPS信号接收装置的尺寸大而且笨重，因此不适合用于小型的电子设备中，诸如移动电话终端、个人数字助理(PDA)等。
JP-2004-214249-A公开了一种现有技术的半导体封装，所述封装包含两个数字半导体芯片，其中一个半导体芯片布置在另一个半导体芯片上方。因此，在上述GPS信号接收装置中，如果RF信号处理单元中包含的模拟半导体芯片和基带信号处理单元中包含的数字半导体芯片被构造成一个封装，那么这种封装将可以有助于降低GPS信号接收装置的布线板的尺寸。
JP-2002-033439-A公开了另一现有技术的半导体封装，所述封装包含模拟RF信号处理半导体芯片和数字基带信号处理半导体芯片，前者布置在后者上方。这种封装也可以有助于降低GPS信号接收装置的布线板的尺寸。
发明内容
现在已经发现上述现有技术具有如下所述的有待解决的问题。
上述现有技术不足以有助于降低GPS信号接收装置的布线板的尺寸，原因在于在GPS信号接收装置的布线板上必须进一步贴装诸如带通滤波器单元、阻抗匹配电路等各种单元。
另外，在JP-2002-033439-A中公开的现有技术中，模拟RF信号处理半导体芯片易受高频噪声，尤其是数字基带信号处理半导体芯片产生的高频噪声的影响。
根据本发明的第一个方面，提供了一种半导体封装，其包括：具有在其内形成的接地层的布线板；设置在接地层上或者上方的模拟半导体芯片；以及数字半导体芯片，其设置在模拟半导体芯片上或者上方，使得数字半导体芯片的衬底面向模拟半导体芯片。
模拟半导体芯片可被形成为射频信号处理半导体芯片，并且数字半导体芯片可被形成为基带信号处理半导体芯片。优选地，接地层与模拟半导体芯片共同扩展。
在该半导体封装中，模拟半导体芯片的有效层(active layer)可面向上，并且数字半导体芯片的有效层面向上。在这种情况下，模拟半导体芯片和数字半导体芯片通过多条导线与形成在布线板上的布线构图层连接。
另一方面，模拟半导体芯片的有效层可面向下，而数字半导体芯片的有效层面向上。在这种情况下，数字半导体芯片贴装在模拟半导体芯片的衬底上。另外，模拟半导体芯片具有在其有效层上设置的多个金属凸点，并且通过该金属凸点与形成在布线板上的布线构图层连接。此外，数字半导体芯片通过多条导线与布线构图层连接。
优选地，数字半导体芯片的特征在于尺寸大于模拟半导体芯片的尺寸。
该半导体封装可进一步包括设置在模拟半导体芯片和数字半导体芯片之间的间隔物单元。
该半导体封装可进一步包括设置在布线板上的用于模拟半导体芯片的阻抗匹配电路，以及包围模拟和数字半导体芯片以及阻抗匹配电路的模制树脂包封(enveloper)。
该半导体封装可进一步包括设置在布线板上的用于模拟半导体芯片的带通滤波器，以及包围模拟和数字半导体芯片以及带通滤波器的模制树脂包封。
该半导体封装可进一步包括多个金属球，其作为电极端牢固地接合到形成在布线板的下表面上的各个电极焊盘。
优选地，布线板可被形成为多层布线板，其至少包括最下绝缘层、中间绝缘层以及最上绝缘层。
在该半导体封装中，当模拟半导体芯片的有效层面向上时，并且当数字半导体芯片的有效层面向上时，接地层形成在最上绝缘层中，从而模拟半导体芯片位于接地层上。
另一方面，当模拟半导体芯片的有效层面向下时，并且当数字半导体芯片的有效层面向上时，接地层形成在最上绝缘层正下方的中间绝缘层中，从而模拟半导体芯片位于接地层上方。
根据本发明的第二个方面，提供一种制造半导体封装的方法，包括：制备布线板；在布线板内形成接地层；在接地层上或上方设置模拟半导体芯片；以及在模拟半导体芯片上或上方设置数字半导体芯片，使得数字半导体芯片的衬底面向模拟半导体芯片。
附图说明
通过以下参照附图进行的说明，将更清楚地理解本发明，其中：
图1A是现有技术的GPS信号接收装置的方框电路图；
图1B是图1A的RF信号处理单元的方框电路图；
图2是现有技术的半导体封装的部分剖视图；
图3A是另一现有技术的半导体封装的剖视图；
图3B是图3A的部分透视图；
图4A至图8A是用于说明制造根据本发明的SIP型封装的实施例的方法的平面图；
图4B至图8B分别是沿着图4A至图8A的B-B线截取的剖视图；以及
图9是示出了图8A和8B的SIP型封装的实施例的修改的剖视图。
具体实施方式
在描述本发明的优选实施例之前，为了能够更好地理解本发明，现在参照图1A和1B说明现有技术的GPS信号接收装置。
首先，参照图1A，在方框图中示出了通常用参考标号10表示的GPS信号接收装置。GPS信号接收装置10包括带通滤波器单元10A、阻抗匹配电路单元10B、RF信号处理单元10C、带通滤波器单元10D以及基带信号处理单元10E。注意，这些单元10A至10E贴装在合适的布线板(未示出)上。带通滤波器单元10A在其输入端与GPS天线11相连，用于接收GPS信号。RF信号处理单元10C被构造为包含模拟RF信号处理半导体芯片的模拟半导体封装，而基带信号处理单元10E被构造为包含数字基带信号处理半导体芯片的数字半导体封装。注意，在图1A中，阻抗匹配电路单元10B象征性地由特征阻抗Z0表示。
在操作中，GPS天线11接收频率为1575.42MHz的GPS信号，该GPS信号被发送到从GPS信号中滤除噪声的带通滤波器10A，然后，通过阻抗匹配电路单元10B将GPS信号输入到RF信号处理单元10C。在RF信号处理单元10C中，GPS信号先被放大，放大的GPS信号被输出到从GPS信号中滤除放大的噪声的带通滤波器10D。
接下来，将GPS信号再次输入到RF信号处理单元10C中，GPS信号(1575.42MHz)在其中被降频转换为中频信号，其频率落入从几MHz到几十MHz的范围内，并且该中频信号被解调为模拟基带信号。然后根据从基带信号处理单元10E输出的时钟信号CLK，将模拟基带信号转换为数字基带信号BBS。接着，将数字基带信号BBS从RF信号处理单元10C输出到基带信号处理单元10E。
在数字半导体封装或者基带信号处理单元10E中，基带信号BBS被适当地处理，从而产生GPS位置信息信号PIS，然后从基带信号处理单元10E输出信号PIS。
如图1B所示，模拟半导体封装或者RF信号处理单元10C包含放大器10C1、混频器10C2、本地振荡器10C3、低通滤波器10C4、解调器10C5以及输出电路10C6。注意，输出电路10C6具有采样保持电路、模拟-数字转换器、分频器等，并且其根据从基带信号处理单元10E输出的时钟信号CLK来工作。
在RF信号处理单元10C中，通过放大器10C1来实现GPS信号的上述放大。混频器10C2和本地振荡器10C3二者用作将GPS信号(1575.42MHz)转换为中频信号(几MHz到几十MHz)的降频转换器。也就是说，混频器10C2将GPS信号与从本地振荡器10C3输出的本地频率信号混合，从而产生中频信号，该中频信号被输入到低通滤波器10C4，在低通滤波器10C4中将噪声从中频信号中滤除。
然后，通过解调器10C5进行中频信号到模拟基带信号的上述解调，并且通过输出电路10C6进行模拟基带信号到数字基带信号的上述转换。
具体地，从基带信号处理单元10E输入的时钟信号CLK被分频电路分为频率低于时钟信号CLK的频率的时钟信号。根据具有较低频率的时钟信号通过采样保持电路对模拟基带信号进行采样，并且根据时钟脉冲CLK将采样信号转换为数字基带信号BBS。
上述GPS信号接收装置被构造为大尺寸装置，其中各单元10A到10E被贴装在布线板上，从而不适合用于小型电子设备中，诸如移动电话终端、个人数字助理(PDA)等。具体地，当将GPS信号接收装置贴装在小型电子设备的母板上时，母板上的被GPS信号接收装置的布线板占据的贴装区域相对较大。
另外，在图1A到1B的现有技术中，当制作多个GPS信号接收装置10时，必需单独调整阻抗匹配单元10B，这导致GPS信号接收装置10的生产成本增加。
参照图2，通过剖视图示出了现有技术的半导体封装的一部分，并且该现有技术的半导体封装已经在例如JP-2004-214249-A中公开。
该半导体封装包括多层布线板20，多层布线板20具有顺序堆叠的多个绝缘层20A、20B、20C、20D和20E。绝缘层20A到20E中的每一个都具有形成在其上的布线构图层(未示出)，并且具有其内形成的多个通孔(未示出)，由此在两个相邻的布线构图层之间建立电连接。
在多层布线板20中，最下绝缘层20A具有形成在其下表面上的接地层20A1，接地层20A1作为热辐射层。此外，最下绝缘层20A具有形成在其下表面上的多个电极焊盘20A2。注意，在图2中，仅代表性地示出了电极焊盘20A2中的一个。
另外，最上绝缘层20E具有形成在其上表面上的多个电极焊盘20E1和多个电极焊盘20E2，并且每个电极焊盘与形成在最上绝缘层20E的上表面上的布线构图层相连。注意，形成在最上绝缘层20E上的布线构图层通过以通孔和介于其间的布线构图层为中介与电极焊盘20A2连接。
如图2所示，多层布线板20具有形成在接地层或热辐射层20A1上方的绝缘层20D和20E内的矩形的凹陷21。多个金属栓塞22形成在矩形凹陷21的底部的绝缘层20A、20B和20C内，从而到达热辐射层20A1。另外，多个金属栓塞23形成在绝缘层20A、20B、20C、20D和20E内，从而到达热辐射层20A1，并且被布置为环绕矩形凹陷21。
该半导体封装还包括通过粘合层25贴装并且粘结到矩形凹陷21的底部的数字半导体芯片24，并且数字半导体芯片24通过焊接线261与电极焊盘20E1连接。数字半导体芯片24通过金属栓塞22与热辐射层20A1热连接，从而能够有助于从数字半导体芯片24辐射热。
该半导体封装还包括数字半导体芯片27，其贴装并且固定到多个金属支撑球28，该金属支撑球28固定在金属栓塞23的各个上表面上，并且数字半导体芯片27通过焊接线262与电极焊盘20E2连接。数字半导体芯片27还通过金属栓塞23与热辐射层20A1热连接，从而能够有助于从数字半导体芯片27辐射热。
在半导体芯片24和27贴装完成后，这些芯片24和27与布线构图层、电极焊盘20E1和20E2以及焊接线261和262通过模制树脂包封29密封在一起，为了简化说明，在图2中仅以虚线示出了模制树脂包封29的轮廓。
如图2所示，在模制树脂包封29中，半导体芯片27布置在半导体芯片24上方。因此，当将半导体封装贴装在母板上时，母板上的由GPS信号接收装置的布线板占据的贴装区域相对较小。
因此，在图1A和图1B的现有技术中，如果包含在RF单元10C中的模拟RF信号处理半导体芯片和包含在基带信号处理单元10E中的数字半导体芯片构成为一个封装，如图2所示，那么该封装可以有助于降低GPS信号接收装置10的布线板的尺寸。
参照图3A和3B，示出了另一现有技术的半导体封装，其为方型扁平封装(QFP)型，并且在例如JP-2002-033439-A中公开了这种QFP类型的半导体封装。注意，图3A是QFP型半导体封装的剖视图，而图3B是图3A的部分透视图。
参照图3A，该QFP型的半导体封装包括：岛或者贴装板30，通过粘合层32贴装并且粘接在贴装板30上的数字基带信号处理半导体芯片31，通过粘合层34贴装并且粘接到数字基带信号处理半导体芯片31的模拟RF信号处理半导体芯片33，通过焊接线36与基带信号处理芯片31和RF信号处理半导体芯片33连接的多个引脚35，密封并且包围贴装板30的模制树脂包封37，半导体芯片31和33，焊接线36，以及成型的引脚35的内部部分。注意，在图3A中，为了简化图示，仅以虚线示出了模制树脂包封的轮廓。
如图3B中代表性示出的，数字基带信号处理半导体芯片31具有在其上表面上形成的电极焊盘31A，焊接线36在相应的电极焊盘31A处与基带信号处理半导体芯片31连接。类似地，模拟RF信号处理半导体芯片33具有在其上表面上形成的电极焊盘33A，焊接线36在相应的电极焊盘33A处与RF信号处理半导体芯片33连接。
另外，如图3A所示，在基带信号处理半导体芯片31的引脚35处适当地设置作为电感元件的调谐线38，其用于传输高频信号，从而改善相关的引脚35中的阻抗特性。
在图1A和1B的上述GPS信号接收装置10中，当用图3A和3B的QFP型半导体封装替代RF信号处理单元10C和基带信号处理单元10E时，这种替代会有助于降低GPS信号接收装置10的布线板的尺寸。然而，在带通滤波器单元10A中，这种尺寸减小并不充分，阻抗匹配电路10B和低通滤波器单元10D必须单独并且分开地贴装在布线板上，从而导致GPS信号接收装置10的体积庞大。
在图3A和3B的QFP型半导体封装中，RF信号处理半导体芯片33易受到高频噪声，尤其是基带信号处理半导体芯片31产生的噪声的影响，这是因为RF信号处理半导体芯片33的有效层仅由一部分模制树脂包封37覆盖，其中该有效层中形成有诸如晶体管、电容器、电阻器、电感器等各种元件。
接着，参照图4A至8A以及图4B至8B，将在下面描述用作GPS接收装置的、根据本发明的系统级封装(SIP)型封装的第一个实施例的制造方法。
注意，图4A至图8A是用于说明制造方法的平面图，而图4B至图8B分别是沿着图4A至图8A的B-B线截取的剖视图。
参照图4A和4B，制备了被称作封装板或者转接板(interposer)的多层布线板40。该多层布线板40包括顺序堆叠的四个绝缘层：最下绝缘层40A，中间绝缘层40B，中间绝缘层40C，以及最上绝缘层40D，并且绝缘层40A、40B、40C和40D的每一个可由合适的树脂材料构成，例如环氧树脂。
虽然在图4B中并未示出，但是最下绝缘层和中间绝缘层40A、40B和40C的每一个都具有在其上表面上形成的布线构图层，以及在其内形成的多个通孔，由此在两个相邻的布线构图层之间建立电连接。布线构图层和通孔可由合适的金属材料构成，诸如铜(Cu)，并且可利用光刻和蚀刻工艺来进行布线构图层和通孔的形成。
如图4B所示，最下绝缘层40A具有在其下表面上形成的多个电极焊盘40A1。这些电极焊盘40A1通过以最下绝缘层40A中形成的通孔(未示出)为中介与形成在最下绝缘层40A的上表面上的布线构图层适当地相连。
如图4A和4B所示，在最上绝缘层40D中形成有凹陷41，并且通过利用光刻和蚀刻工艺在最上绝缘层40D中形成多个通孔(未示出)。
然后，参照图5A和5B，通过镀铜工艺在最上绝缘层40D的上表面上形成铜(Cu)层42，从而凹陷41被铜填充。注意，在图5B中，虽然夸张地示出了绝缘层40A、40B、40C和40D的每一个的厚度，但实际上其厚度非常薄，由此Cu层42基本上均匀地形成，且Cu层42并未在凹陷41处下陷。
然后，参照图6A和6B，通过使用光刻和蚀刻工艺对Cu层42(见图5A和5B)进行构图，从而在最上绝缘层40D的上表面上形成多个电极焊盘421和多个电极焊盘422，由此在矩形凹陷41内留下铜(Cu)层部分423作为接地层。如图6A所示，布置电极焊盘421使其环绕Cu层部分或者矩形接地层423，并且沿着电极焊盘421的排列的外周边布置电极焊盘422。
注意，虽然通过上述光刻和蚀刻工艺在最上绝缘层40D的上表面上进一步形成了布线构图层，但是图6A和6B中并未示出，以避免图示过于复杂。
另外，注意，形成在最上绝缘层40D的上表面上的布线构图层与最上绝缘层40D中形成的上述通孔合适地连接，从而在相关的布线构图层与最下绝缘层40A的下表面上形成的电极焊盘40A1之间建立电连接。
此外，注意，电极焊盘421和422与相关的布线构图层合适地连接。
如图6A所示，在完成了在最上绝缘层40D上形成布线构图层之后，在最上绝缘层40D上贴装两个带通滤波器单元43和44，使其与相关的布线构图层合适地连接，并且带通滤波器单元43和44的每一个可被形成为表面声波(SAW)型芯片。注意，带通滤波器单元43和44与图1A和1B的GPS信号接收装置10的带通滤波器单元10A和10D相对应。
另外，通过在最上绝缘层40D上贴装和布置各种无源元件45A和45B来构成阻抗匹配电路45，阻抗匹配电路45与最上绝缘层40D上的布线构图层(未示出)合适地连接。例如，无源元件45A的每一个被形成为电容器芯片，而无源元件45B的每一个被形成为电感器芯片。注意，阻抗匹配电路45与图1A和1B的GPS信号接收装置10的阻抗匹配电路10B相对应。
另外，由参考标号46代表性地表示的各种无源元件被贴装和布置在最上绝缘层40D上，并且如果必要的话，与最上绝缘层40D上的布线构图层(未示出)合适地连接。无源元件46的一部分可以用电阻器芯片表示，另一部分可以用电容器芯片表示。例如，信号强度转换电路由一些无源元件46构成。
接着，参照图7A和7B，通过使用合适的粘合剂将模拟矩形半导体芯片47牢固地贴装在矩形接地层423上。
如图7B所示，RF信号处理半导体芯片47包括衬底47A和形成在衬底47A上的有效层47B，有效层47B包括形成在其内的各元件，例如晶体管、电容器、电阻器等。简言之，进行RF信号处理半导体芯片47在接地层423上的贴装，使得有效层47B面向上。
另外，如图7A所示，矩形RF信号处理半导体芯片47具有多个电极焊盘47C，其中电极焊盘47C形成在有效层47B的表面上，从而沿着其四边布置。
在完成RF信号处理半导体芯片47在接地层423上的贴装之后，利用线焊机(未示出)通过焊接线481将电极焊盘47C与形成在最上绝缘层40D上的电极焊盘421连接。
接着，参照图8A和8B，通过使用适当的粘合剂在RF信号处理半导体芯片47上固定地贴装可由合适的树脂材料制成的间隔物部件49，并且通过使用适当的粘合剂将尺寸大于RF信号处理半导体芯片47的数字矩形基带信号处理半导体芯片50牢固地贴装在间隔物部件49上。显然，设置间隔物部件49是为了避免焊接线482与基带信号处理半导体芯片50之间的干扰。
如图8B所示，基带信号处理半导体芯片50包括衬底50A和形成在衬底50A上的有效层50B，有效层50B包括形成在其内的各种元件，例如晶体管、电容器、电阻器等。简言之，进行基带信号处理半导体芯片50在间隔物部件49上的贴装，使得有效层50B面向上。
此外，如图8A所示，矩形基带信号处理半导体芯片50具有多个电极焊盘50C，其中电极焊盘50C形成在有效层50B的表面上，从而沿其四边布置。
在完成基带信号处理半导体芯片50在间隔物部件49上的贴装之后，利用线焊机(未示出)通过焊接线482将电极焊盘50C与形成在最上绝缘层40D上的电极焊盘422连接。
此后，通过模制树脂包封51密封设置在最上绝缘层40D上的所有元件，为了简化图示，在图8A中仅以虚线示出了模制树脂包封的轮廓。然后，如图8B所示，作为电极端的多个金属球52牢固地接合到形成在最下绝缘层40A的下表面上的电极焊盘40A1，从而完成根据本发明的SIP型封装的制作。也就是说，该SIP型封装的特征是由金属球52形成的球栅阵列(BGA)。
注意，参照图6A进行描述的上述信号强度转换电路用于对从RF信号处理半导体芯片47输入到基带信号处理半导体芯片50的基带信号的强度进行调整。
虽然如此制作的SIP型封装能够以与图1A和1B的GPS信号接收装置10基本相同的方式工作，但是与图1A和1B的GPS信号接收装置10相比，这种封装的尺寸显著降低，原因在于所有的元件(43、44、45、46、47、50等)被集成为一个封装。
另外，在图8A和8B的SIP型封装中，接地层423与RF信号处理半导体芯片47共同扩展，从而接地层47的接地能力显著增强。由此，流过衬底47A的电流可被有效地泄漏到接地层423，从而能够稳定地保持RF信号处理半导体芯片47的高频特性。另一方面，RF信号处理半导体芯片47的有效层47B被基带信号处理半导体芯片50的衬底50A覆盖，并且在基带信号处理半导体芯片50工作期间，衬底50A的电位相对稳定，因此衬底50A作为有效的电磁屏蔽。结果，不但能够保证RF信号处理半导体芯片47的稳定工作，而且可以有效地保护RF信号处理半导体芯片47不受高频噪声干扰。
在基带信号处理半导体芯片50的工作期间，其有效层50B会产生高频噪声。因此，当基带信号处理半导体芯片50堆叠在RF信号处理半导体芯片47上时(见图8B)，RF信号处理半导体芯片47会受到有效层50B产生的高频噪声影响。
但是，根据发明人进行的实验发现，RF信号处理半导体芯片47基本上不会受到有效层50B产生的高频噪声影响。
在实验中，制备第一组样品，在该第一组样品的每一个中，基带信号处理半导体芯片(50)堆叠在贴装在RF信号处理半导体芯片(47)上的间隔物部件(49)上(见图8B)，并且对于第一组中包括的每个样品，测量由信噪比(SNR)表示的RF信号处理半导体芯片(47)的敏感特性。另一方面，制备第二组样品，在该第二组样品的每一个中，RF信号处理半导体芯片(47)直接堆叠在基带信号处理半导体芯片(50)上，并且对于第二组中的每个样品，测量由信噪比(SNR)表示的RF信号处理半导体芯片(47)的敏感特性。在测量中，使用自主(AUTONOMOUS)模式，并且输入/输出(I/O)电压为2.9V。另外，GPS信号的强度被设定为-130dBm，但是其在最大值和最小值之间可变。在GPS信号的强度的最大值和最小值之间进行测量。
下面的表中示出了测量结果：
                              第一组
                  SNR(最大)              SNR(最小)
平均值            38.1dB                 37.3dB
                              第二组
                  SNR(最大)              SNR(最小)
平均值            35.4dB                 34.5dB
如这些表中所示，第一组样品的测量结果比第二组样品的测量结果高大约3dB。这表示基带信号处理半导体芯片50的衬底50A起到保护RF信号处理半导体芯片47的有效的电磁屏蔽作用。
正如已经描述过的，在图1A和1B的现有技术中，当制作多个GPS信号接收装置10时，需要单独地调节阻抗匹配单元10B。相反，当根据本发明制造多个SIP型封装时，不需要单独调节阻抗匹配电路45，这是因为能够预先确定用于形成阻抗匹配电路45的电容器45A和电感器45B的最优值。类似地，不需要单独调节参照图6A描述的上述信号强度转换电路，这是因为能够预先确定用于形成信号强度转换电路的诸如电容器、电阻器等无源元件的最优值。
在图8A和8B的上述实施例中，虽然基带信号处理半导体芯片50具有比RF信号处理半导体芯片47宽的尺寸，但是如果需要的话，后者可以宽于前者。在这种情况下，如果在焊接线482和基带信号处理半导体芯片50之间没有干扰，则可以省略间隔物部件49。也就是说，基带信号处理半导体芯片50可以直接接合到RF信号处理半导体芯片47而无需使用间隔物部件49。
参照与图8A相对应的图9，示出了根据本发明的SIP型封装的上述实施例的修改。
在该修改中，倒装芯片(FC)型模拟RF信号处理半导体芯片53取代了RF信号处理半导体芯片47，并且其包括衬底53A以及形成在衬底53A上的有效层53B。FC型模拟RF信号处理半导体芯片53具有多个金属凸点53C，其作为电极端牢固地接合在有效层53B的表面上。
另外，在该修改中，从最上绝缘层40D省略了接地层423，而替代地在最上绝缘层40D正下方的中间绝缘层40C中形成了接地层54。与接地层423的形成类似，当在中间绝缘层40C上形成布线构图层(未示出)时同时进行接地层54的形成。
另一方面，形成在最下绝缘层40D上的布线构图层具有多个电极焊盘(未示出)，所述电极焊盘被设置为与金属凸点53C的排列具有镜像关系。也就是说，FC型RF信号处理半导体芯片53被倒置并且贴装在最上绝缘层40D上，从而金属凸点与各个电极焊盘相接触并且被焊接在其上。
与图8A和8B的实施例类似，在图9的修改中，接地层54与FC型RF信号处理半导体芯片53共同扩展，从而接地层54的接地能力充分地增强。另外，基带信号处理半导体芯片50的衬底50A作为有效的电磁屏蔽。由此，不但能够保证FC型RF信号处理半导体芯片53的稳定工作，而且可以有效地保护FC型RF信号处理半导体芯片53不受高频噪声干扰。
最后，本领域技术人员应该理解，以上描述是方法和器件的优选实施例，在不偏离本发明精神和范围的情况下可以对本发明进行各种改变和调整。

Claims (19)

1.一种半导体封装，包括：
具有在其内形成的接地层的布线板；
设置在所述接地层上或者上方的模拟半导体芯片；以及
数字半导体芯片，其设置在所述模拟半导体芯片上或者上方，使得所述数字半导体芯片的衬底面向所述模拟半导体芯片。
2.如权利要求1所述的半导体封装，其中所述模拟半导体芯片被形成为射频信号处理半导体芯片，并且所述数字半导体芯片被形成为基带信号处理半导体芯片。
3.如权利要求1所述的半导体封装，其中所述接地层与所述模拟半导体芯片共同扩展。
4.如权利要求1所述的半导体封装，其中所述模拟半导体芯片的有效层面向上，并且所述数字半导体芯片的有效层面向上。
5.如权利要求4所述的半导体封装，其中所述模拟半导体芯片和所述数字半导体芯片通过多条导线与形成在所述布线板上的布线构图层连接。
6.如权利要求1所述的半导体封装，其中所述模拟半导体芯片的有效层面向下，并且所述数字半导体芯片的有效层面向上。
7.如权利要求6所述的半导体封装，其中所述数字半导体芯片贴装在所述模拟半导体芯片的衬底上。
8.如权利要求6所述的半导体封装，其中所述模拟半导体芯片具有在其有效层上设置的多个金属凸点，并且通过所述金属凸点与形成在所述布线板上的布线构图层连接，并且其中所述数字半导体芯片通过多条导线与所述布线构图层连接。
9.如权利要求1所述的半导体封装，其中所述数字半导体芯片的特征是尺寸大于模拟半导体芯片的尺寸。
10.如权利要求9所述的半导体封装，进一步包括设置在所述模拟半导体芯片和所述数字半导体芯片之间的间隔物单元。
11.如权利要求1所述的半导体封装，进一步包括：
设置在所述布线板上的用于所述模拟半导体芯片的阻抗匹配电路；以及
包围所述模拟和数字半导体芯片以及所述阻抗匹配电路的模制树脂包封。
12.如权利要求1所述的半导体封装，进一步包括：
设置在所述布线板上的用于所述模拟半导体芯片的带通滤波器；以及
包围所述模拟和数字半导体芯片以及所述带通滤波器的模制树脂包封。
13.如权利要求1所述的半导体封装，进一步包括多个金属球，其作为电极端牢固地接合到形成在布线板的下表面上的各个电极焊盘。
14.如权利要求1所述的半导体封装，其中所述布线板被形成为多层布线板，其至少包括最下绝缘层、中间绝缘层以及最上绝缘层。
15.如权利要求14所述的半导体封装，其中所述模拟半导体芯片的有效层面向上，并且所述数字半导体芯片的有效层面向上，所述接地层形成在所述最上绝缘层中，从而所述模拟半导体芯片位于所述接地层上。
16.如权利要求14所述的半导体封装，其中所述模拟半导体芯片的有效层面向下，并且所述数字半导体芯片的有效层面向上，所述接地层形成在所述最上绝缘层正下方的所述中间绝缘层中，从而所述模拟半导体芯片位于所述接地层上方。
17.一种制造半导体封装的方法，包括：
制备布线板；
在所述布线板内形成接地层；
在所述接地层上或上方设置模拟半导体芯片；以及
在所述模拟半导体芯片上或上方设置数字半导体芯片，使得所述数字半导体芯片的衬底面向所述模拟半导体芯片。
18.如权利要求17所述的方法，其中所述模拟半导体芯片被形成为射频信号处理半导体芯片，并且所述数字半导体芯片被形成为基带信号处理半导体芯片。
19.如权利要求17所述的方法，其中进行所述接地层的形成，使得所述接地层与所述模拟半导体芯片共同扩展。
CNA2006100848891A 2005-05-20 2006-05-22 包含顺序堆叠的模拟半导体芯片和数字半导体芯片的sip型封装及其制造方法 Pending CN1866515A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005147831A JP4408832B2 (ja) 2005-05-20 2005-05-20 半導体装置
JP2005147831 2005-05-20

Publications (1)

Publication Number Publication Date
CN1866515A true CN1866515A (zh) 2006-11-22

Family

ID=36968879

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2006100848891A Pending CN1866515A (zh) 2005-05-20 2006-05-22 包含顺序堆叠的模拟半导体芯片和数字半导体芯片的sip型封装及其制造方法

Country Status (6)

Country Link
US (1) US20060261471A1 (zh)
EP (1) EP1724833A2 (zh)
JP (1) JP4408832B2 (zh)
KR (1) KR100744979B1 (zh)
CN (1) CN1866515A (zh)
TW (1) TW200707699A (zh)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100744979B1 (ko) * 2005-05-20 2007-08-02 엔이씨 일렉트로닉스 가부시키가이샤 아날로그 반도체 칩 및 디지털 반도체 칩이 순서대로적층된 ｓｉｐ 타입 패키지, 및 그 제조 방법
CN101150123B (zh) * 2007-10-31 2010-06-02 日月光半导体制造股份有限公司 具有电磁屏蔽罩盖的半导体封装结构
CN101908082A (zh) * 2010-04-30 2010-12-08 梅州市志浩电子科技有限公司 印刷电路板的阻抗设计方法及阻抗设计装置
CN103390612A (zh) * 2012-05-11 2013-11-13 富士通半导体股份有限公司 半导体器件、半导体器件模块以及半导体器件的制造方法
CN103441124A (zh) * 2013-08-27 2013-12-11 矽力杰半导体技术(杭州)有限公司 电压调节器的叠成封装方法及相应的叠成封装装置
CN106324485A (zh) * 2016-08-30 2017-01-11 福州瑞芯微电子股份有限公司 芯片的无线测试电路及无线测试方法
CN106324484A (zh) * 2016-08-30 2017-01-11 福州瑞芯微电子股份有限公司 芯片的无线调试电路和方法
CN106374962A (zh) * 2016-08-30 2017-02-01 福州瑞芯微电子股份有限公司 一体化wifi芯片及其封装方法
CN106361303A (zh) * 2016-08-30 2017-02-01 福州瑞芯微电子股份有限公司 血管检测一体化芯片及其实现方法
CN112415075A (zh) * 2019-08-21 2021-02-26 生命技术公司 包含多通道流动池的装置
CN113172036A (zh) * 2015-03-26 2021-07-27 生命技术公司 用于处理半导体传感器阵列装置的方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100764682B1 (ko) * 2006-02-14 2007-10-08 인티그런트 테크놀로지즈(주) 집적회로 칩 및 패키지.
DE102006033175A1 (de) * 2006-07-18 2008-01-24 Robert Bosch Gmbh Elektronikanordnung
US20110193243A1 (en) * 2010-02-10 2011-08-11 Qualcomm Incorporated Unique Package Structure
CN103969572B (zh) * 2013-02-05 2017-05-17 泰斗微电子科技有限公司 一种sip芯片测试平台和方法
WO2015037390A1 (ja) * 2013-09-10 2015-03-19 株式会社村田製作所 センサモジュール
TWI553817B (zh) 2014-06-17 2016-10-11 瑞昱半導體股份有限公司 具有電磁防護功能之積體電路及其製造方法
KR20160036945A (ko) * 2014-09-26 2016-04-05 삼성전기주식회사 인쇄회로기판 및 이를 포함하는 전자부품 패키지
JP2018032680A (ja) * 2016-08-23 2018-03-01 日本電信電話株式会社 積層集積回路
US10332820B2 (en) * 2017-03-20 2019-06-25 Akash Systems, Inc. Satellite communication transmitter with improved thermal management
US10374553B2 (en) * 2017-06-15 2019-08-06 Akash Systems, Inc. Microwave transmitter with improved information throughput
US10680633B1 (en) * 2018-12-21 2020-06-09 Analog Devices International Unlimited Compnay Data acquisition system-in-package

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
US5198693A (en) * 1992-02-05 1993-03-30 International Business Machines Corporation Aperture formation in aluminum circuit card for enhanced thermal dissipation
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
US5642261A (en) * 1993-12-20 1997-06-24 Sgs-Thomson Microelectronics, Inc. Ball-grid-array integrated circuit package with solder-connected thermal conductor
US5858814A (en) * 1996-07-17 1999-01-12 Lucent Technologies Inc. Hybrid chip and method therefor
US6381283B1 (en) * 1998-10-07 2002-04-30 Controlnet, Inc. Integrated socket with chip carrier
JP2000323617A (ja) * 1999-05-12 2000-11-24 Mitsubishi Electric Corp 高周波用半導体パッケージ
JP2001035994A (ja) * 1999-07-15 2001-02-09 Toshiba Corp 半導体集積回路装置およびシステム基板
US6261869B1 (en) * 1999-07-30 2001-07-17 Hewlett-Packard Company Hybrid BGA and QFP chip package assembly and process for same
US6531784B1 (en) * 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
JP3417388B2 (ja) * 2000-07-19 2003-06-16 松下電器産業株式会社 半導体装置
KR100391093B1 (ko) * 2001-01-04 2003-07-12 삼성전자주식회사 히트 싱크가 부착된 볼 그리드 어레이 패키지
US6586825B1 (en) * 2001-04-26 2003-07-01 Lsi Logic Corporation Dual chip in package with a wire bonded die mounted to a substrate
US6867500B2 (en) * 2002-04-08 2005-03-15 Micron Technology, Inc. Multi-chip module and methods
JP2004111656A (ja) * 2002-09-18 2004-04-08 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
US7479407B2 (en) * 2002-11-22 2009-01-20 Freescale Semiconductor, Inc. Digital and RF system and method therefor
JP2004214249A (ja) * 2002-12-27 2004-07-29 Renesas Technology Corp 半導体モジュール
TWI317549B (en) * 2003-03-21 2009-11-21 Advanced Semiconductor Eng Multi-chips stacked package
JP2004296719A (ja) * 2003-03-26 2004-10-21 Renesas Technology Corp 半導体装置
TWI278947B (en) * 2004-01-13 2007-04-11 Samsung Electronics Co Ltd A multi-chip package, a semiconductor device used therein and manufacturing method thereof
US7235889B2 (en) * 2004-09-10 2007-06-26 Lsi Corporation Integrated heatspreader for use in wire bonded ball grid array semiconductor packages
JP4748648B2 (ja) * 2005-03-31 2011-08-17 ルネサスエレクトロニクス株式会社 半導体装置
JP4408832B2 (ja) * 2005-05-20 2010-02-03 Ｎｅｃエレクトロニクス株式会社 半導体装置

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100744979B1 (ko) * 2005-05-20 2007-08-02 엔이씨 일렉트로닉스 가부시키가이샤 아날로그 반도체 칩 및 디지털 반도체 칩이 순서대로적층된 ｓｉｐ 타입 패키지, 및 그 제조 방법
CN101150123B (zh) * 2007-10-31 2010-06-02 日月光半导体制造股份有限公司 具有电磁屏蔽罩盖的半导体封装结构
CN101908082A (zh) * 2010-04-30 2010-12-08 梅州市志浩电子科技有限公司 印刷电路板的阻抗设计方法及阻抗设计装置
CN101908082B (zh) * 2010-04-30 2012-10-24 梅州市志浩电子科技有限公司 印刷电路板的阻抗设计方法及阻抗设计装置
CN103390612A (zh) * 2012-05-11 2013-11-13 富士通半导体股份有限公司 半导体器件、半导体器件模块以及半导体器件的制造方法
CN103441124B (zh) * 2013-08-27 2016-01-06 矽力杰半导体技术(杭州)有限公司 电压调节器的叠层封装方法及相应的叠层封装装置
CN103441124A (zh) * 2013-08-27 2013-12-11 矽力杰半导体技术(杭州)有限公司 电压调节器的叠成封装方法及相应的叠成封装装置
CN113172036A (zh) * 2015-03-26 2021-07-27 生命技术公司 用于处理半导体传感器阵列装置的方法
CN106324485A (zh) * 2016-08-30 2017-01-11 福州瑞芯微电子股份有限公司 芯片的无线测试电路及无线测试方法
CN106324484A (zh) * 2016-08-30 2017-01-11 福州瑞芯微电子股份有限公司 芯片的无线调试电路和方法
CN106374962A (zh) * 2016-08-30 2017-02-01 福州瑞芯微电子股份有限公司 一体化wifi芯片及其封装方法
CN106361303A (zh) * 2016-08-30 2017-02-01 福州瑞芯微电子股份有限公司 血管检测一体化芯片及其实现方法
CN106324485B (zh) * 2016-08-30 2019-04-02 福州瑞芯微电子股份有限公司 芯片的无线测试电路及无线测试方法
CN106324484B (zh) * 2016-08-30 2019-04-02 福州瑞芯微电子股份有限公司 芯片的无线调试电路和方法
CN112415075A (zh) * 2019-08-21 2021-02-26 生命技术公司 包含多通道流动池的装置

Also Published As

Publication number Publication date
JP2006324563A (ja) 2006-11-30
TW200707699A (en) 2007-02-16
JP4408832B2 (ja) 2010-02-03
US20060261471A1 (en) 2006-11-23
KR100744979B1 (ko) 2007-08-02
EP1724833A2 (en) 2006-11-22
KR20060120462A (ko) 2006-11-27

Similar Documents

Publication Publication Date Title
CN1866515A (zh) 包含顺序堆叠的模拟半导体芯片和数字半导体芯片的sip型封装及其制造方法
CN1190113C (zh) 陶瓷叠层器件
CN100345285C (zh) 高频器件
TWI520231B (zh) 半導體元件以及在膠封之後形成通過互連結構而接地的遮蔽層之方法
CN1224301C (zh) 高频模块
CN1206732C (zh) 具有集成射频能力的多芯片模块
US9743519B2 (en) High-frequency component and high-frequency module including the same
KR101374463B1 (ko) 내장-다이 코어리스 기판들을 이용한 패키지형 시스템 및 그것을 형성하는 프로세스
CN1441613A (zh) 高频组件
CN101080958A (zh) 部件内置模块及其制造方法
US20080067656A1 (en) Stacked multi-chip package with EMI shielding
KR20190067839A (ko) 오버몰드 구조를 갖는 양면 라디오-주파수 패키지
CN1215545C (zh) 半导体测试装置
US20070053167A1 (en) Electronic circuit module and manufacturing method thereof
CN1877829A (zh) 半导体装置以及用于制造该半导体装置的方法
US20160126200A1 (en) Semiconductor device package with integrated antenna for wireless applications
JP4504204B2 (ja) 接続要素を有する高周波チップパッケージ
CN1941641A (zh) 信号接收装置
CN1864259A (zh) 电子器件及其承载衬底
JP2004128288A (ja) 半導体装置および電子装置
JP2005340741A (ja) 半導体装置
JP2011009776A (ja) 半導体装置
US7362038B1 (en) Surface acoustic wave (SAW) device package and method for packaging a SAW device
US7763960B2 (en) Semiconductor device, method for manufacturing semiconductor device, and electric equipment system
CN1685502A (zh) 高频信号传输构件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication

Open date: 20061122