CN1472808A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN1472808A CN1472808A CNA031381928A CN03138192A CN1472808A CN 1472808 A CN1472808 A CN 1472808A CN A031381928 A CNA031381928 A CN A031381928A CN 03138192 A CN03138192 A CN 03138192A CN 1472808 A CN1472808 A CN 1472808A
- Authority
- CN
- China
- Prior art keywords
- substrate
- semiconductor chip
- mentioned
- connection
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/015—Manufacture or treatment of bond wires
- H10W72/01515—Forming coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/381—Auxiliary members
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/853—On the same surface
- H10W72/859—Bump connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/853—On the same surface
- H10W72/865—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/944—Dispositions of multiple bond pads
- H10W72/9445—Top-view layouts, e.g. mirror arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP219909/2002 | 2002-07-29 | ||
| JP2002219909A JP2004063767A (ja) | 2002-07-29 | 2002-07-29 | 半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1472808A true CN1472808A (zh) | 2004-02-04 |
Family
ID=30437667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA031381928A Pending CN1472808A (zh) | 2002-07-29 | 2003-05-29 | 半导体装置 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6841870B2 (https=) |
| JP (1) | JP2004063767A (https=) |
| KR (1) | KR20040011348A (https=) |
| CN (1) | CN1472808A (https=) |
| DE (1) | DE10324598A1 (https=) |
| TW (1) | TW200402133A (https=) |
Families Citing this family (56)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI225291B (en) * | 2003-03-25 | 2004-12-11 | Advanced Semiconductor Eng | Multi-chips module and manufacturing method thereof |
| JP4370513B2 (ja) * | 2004-02-27 | 2009-11-25 | エルピーダメモリ株式会社 | 半導体装置 |
| KR100587081B1 (ko) * | 2004-06-30 | 2006-06-08 | 주식회사 하이닉스반도체 | 개선된 열방출 특성을 갖는 반도체 패키지 |
| KR100593703B1 (ko) * | 2004-12-10 | 2006-06-30 | 삼성전자주식회사 | 돌출부 와이어 본딩 구조 보강용 더미 칩을 포함하는반도체 칩 적층 패키지 |
| US20060202317A1 (en) * | 2005-03-14 | 2006-09-14 | Farid Barakat | Method for MCP packaging for balanced performance |
| KR101141707B1 (ko) * | 2006-02-24 | 2012-05-04 | 삼성테크윈 주식회사 | 반도체 패키지 및 그 제조 방법 |
| KR100780691B1 (ko) * | 2006-03-29 | 2007-11-30 | 주식회사 하이닉스반도체 | 폴딩 칩 플래나 스택 패키지 |
| KR100766502B1 (ko) * | 2006-11-09 | 2007-10-15 | 삼성전자주식회사 | 반도체 소자 패키지 |
| KR100851108B1 (ko) * | 2007-01-22 | 2008-08-08 | 주식회사 네패스 | 웨이퍼 레벨 시스템 인 패키지 및 그 제조 방법 |
| KR100885918B1 (ko) * | 2007-04-19 | 2009-02-26 | 삼성전자주식회사 | 반도체 디바이스 스택 패키지, 이를 이용한 전기장치 및 그패키지의 제조방법 |
| US8643157B2 (en) * | 2007-06-21 | 2014-02-04 | Stats Chippac Ltd. | Integrated circuit package system having perimeter paddle |
| US7915719B2 (en) * | 2007-09-28 | 2011-03-29 | Renesas Electronics Corporation | Semiconductor device |
| KR100972052B1 (ko) * | 2008-02-16 | 2010-07-22 | 김회진 | 비점오염원 처리시설 |
| US8102666B2 (en) * | 2008-08-19 | 2012-01-24 | Stats Chippac Ltd. | Integrated circuit package system |
| US7691674B1 (en) * | 2009-06-20 | 2010-04-06 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked device and method of manufacturing thereof |
| US8553420B2 (en) | 2010-10-19 | 2013-10-08 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
| KR101061531B1 (ko) * | 2010-12-17 | 2011-09-01 | 테세라 리써치 엘엘씨 | 중앙 콘택을 구비하며 접지 또는 배전을 개선한 적층형 마이크로전자 조립체 |
| US8928153B2 (en) | 2011-04-21 | 2015-01-06 | Tessera, Inc. | Flip-chip, face-up and face-down centerbond memory wirebond assemblies |
| US8952516B2 (en) | 2011-04-21 | 2015-02-10 | Tessera, Inc. | Multiple die stacking for two or more die |
| US8633576B2 (en) | 2011-04-21 | 2014-01-21 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
| US8304881B1 (en) * | 2011-04-21 | 2012-11-06 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
| US8338963B2 (en) * | 2011-04-21 | 2012-12-25 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
| US9013033B2 (en) | 2011-04-21 | 2015-04-21 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
| US8970028B2 (en) | 2011-12-29 | 2015-03-03 | Invensas Corporation | Embedded heat spreader for package with multiple microelectronic elements and face-down connection |
| US8841765B2 (en) | 2011-04-22 | 2014-09-23 | Tessera, Inc. | Multi-chip module with stacked face-down connected dies |
| US8513817B2 (en) | 2011-07-12 | 2013-08-20 | Invensas Corporation | Memory module in a package |
| US8823165B2 (en) | 2011-07-12 | 2014-09-02 | Invensas Corporation | Memory module in a package |
| US8502390B2 (en) | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
| WO2013052080A1 (en) | 2011-10-03 | 2013-04-11 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with orthogonal windows |
| US8659141B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
| US8917532B2 (en) | 2011-10-03 | 2014-12-23 | Invensas Corporation | Stub minimization with terminal grids offset from center of package |
| US8441111B2 (en) | 2011-10-03 | 2013-05-14 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
| US8436457B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
| US8659142B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
| US8345441B1 (en) | 2011-10-03 | 2013-01-01 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
| US8659140B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
| EP2764543A2 (en) | 2011-10-03 | 2014-08-13 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
| US8525327B2 (en) | 2011-10-03 | 2013-09-03 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
| KR20150040998A (ko) * | 2012-08-02 | 2015-04-15 | 테세라, 인코포레이티드 | 두 개 이상의 다이에 대한 다중 다이 페이스-다운 적층 |
| US8848392B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support module and microelectronic assembly |
| US9368477B2 (en) | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
| US8848391B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support component and microelectronic assembly |
| US8787034B2 (en) | 2012-08-27 | 2014-07-22 | Invensas Corporation | Co-support system and microelectronic assembly |
| KR102190382B1 (ko) * | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | 반도체 패키지 |
| US9123600B2 (en) * | 2013-02-27 | 2015-09-01 | Invensas Corporation | Microelectronic package with consolidated chip structures |
| US9070423B2 (en) | 2013-06-11 | 2015-06-30 | Invensas Corporation | Single package dual channel memory with co-support |
| US9123555B2 (en) | 2013-10-25 | 2015-09-01 | Invensas Corporation | Co-support for XFD packaging |
| US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
| US10453785B2 (en) * | 2014-08-07 | 2019-10-22 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming double-sided fan-out wafer level package |
| US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
| US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
| US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
| KR200485491Y1 (ko) | 2017-03-30 | 2018-01-16 | 오승아 | 학습용 간이 정수장치 |
| KR20180130043A (ko) * | 2017-05-25 | 2018-12-06 | 에스케이하이닉스 주식회사 | 칩 스택들을 가지는 반도체 패키지 |
| KR102647423B1 (ko) * | 2019-03-04 | 2024-03-14 | 에스케이하이닉스 주식회사 | 와이어 본딩 연결 구조를 가지는 반도체 패키지 및 이를 포함하는 반도체 패키지 구조물 |
| CN117577634A (zh) * | 2022-08-08 | 2024-02-20 | 长鑫存储技术有限公司 | 三维堆叠封装结构及其形成方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0177395B1 (ko) | 1995-04-27 | 1999-05-15 | 문정환 | 반도체소자를 칩 상태로 장착시켜서 된 전자회로 보드 및 그 제조방법 |
| JP2000349228A (ja) | 1999-06-09 | 2000-12-15 | Hitachi Ltd | 積層型半導体パッケージ |
| TW415056B (en) * | 1999-08-05 | 2000-12-11 | Siliconware Precision Industries Co Ltd | Multi-chip packaging structure |
| US6265763B1 (en) * | 2000-03-14 | 2001-07-24 | Siliconware Precision Industries Co., Ltd. | Multi-chip integrated circuit package structure for central pad chip |
-
2002
- 2002-07-29 JP JP2002219909A patent/JP2004063767A/ja active Pending
-
2003
- 2003-03-07 US US10/382,497 patent/US6841870B2/en not_active Expired - Lifetime
- 2003-05-27 TW TW092114249A patent/TW200402133A/zh unknown
- 2003-05-27 KR KR1020030033615A patent/KR20040011348A/ko not_active Ceased
- 2003-05-29 CN CNA031381928A patent/CN1472808A/zh active Pending
- 2003-05-30 DE DE10324598A patent/DE10324598A1/de not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| JP2004063767A (ja) | 2004-02-26 |
| DE10324598A1 (de) | 2004-02-26 |
| TW200402133A (en) | 2004-02-01 |
| US6841870B2 (en) | 2005-01-11 |
| KR20040011348A (ko) | 2004-02-05 |
| US20040016999A1 (en) | 2004-01-29 |
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