CN1471164A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN1471164A CN1471164A CNA031452809A CN03145280A CN1471164A CN 1471164 A CN1471164 A CN 1471164A CN A031452809 A CNA031452809 A CN A031452809A CN 03145280 A CN03145280 A CN 03145280A CN 1471164 A CN1471164 A CN 1471164A
- Authority
- CN
- China
- Prior art keywords
- fuse
- macrocell
- common piece
- semiconductor device
- redundant block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 230000007257 malfunction Effects 0.000 claims description 27
- 230000006870 function Effects 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 21
- 230000001788 irregular Effects 0.000 description 10
- 230000008859 change Effects 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/812—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a reduced amount of fuses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
- G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002190800A JP4311917B2 (ja) | 2002-06-28 | 2002-06-28 | 半導体装置 |
JP190800/2002 | 2002-06-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1471164A true CN1471164A (zh) | 2004-01-28 |
CN1329925C CN1329925C (zh) | 2007-08-01 |
Family
ID=29774342
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB031452809A Expired - Fee Related CN1329925C (zh) | 2002-06-28 | 2003-06-27 | 半导体器件 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6822912B2 (zh) |
JP (1) | JP4311917B2 (zh) |
KR (1) | KR100882344B1 (zh) |
CN (1) | CN1329925C (zh) |
TW (1) | TWI257700B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100452236C (zh) * | 2004-05-14 | 2009-01-14 | 富士通株式会社 | 具有需要刷新操作的动态存储器单元的半导体存储器 |
CN115295059A (zh) * | 2022-10-09 | 2022-11-04 | 浙江力积存储科技有限公司 | 半导体器件及其操作方法、装置和计算机可读存储介质 |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7415640B1 (en) * | 2003-10-13 | 2008-08-19 | Virage Logic Corporation | Methods and apparatuses that reduce the size of a repair data container for repairable memories |
KR100587076B1 (ko) | 2004-04-28 | 2006-06-08 | 주식회사 하이닉스반도체 | 메모리 장치 |
KR100604868B1 (ko) * | 2004-06-11 | 2006-07-31 | 삼성전자주식회사 | 트위스트 비트라인 구조를 갖는 메모리 장치의 리던던시회로 및 불량 셀 구제 방법 |
US7082065B2 (en) * | 2004-09-17 | 2006-07-25 | International Business Machines Corporation | Method and apparatus for efficient utilization of electronic fuse source connections |
JP4584773B2 (ja) * | 2005-05-31 | 2010-11-24 | 富士通セミコンダクター株式会社 | 半導体記憶装置 |
JP2007227883A (ja) * | 2006-01-27 | 2007-09-06 | Matsushita Electric Ind Co Ltd | ベース半導体チップ、半導体集積回路装置及びその製造方法 |
JP4899557B2 (ja) | 2006-03-17 | 2012-03-21 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP2007323726A (ja) * | 2006-05-31 | 2007-12-13 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP4891748B2 (ja) * | 2006-12-11 | 2012-03-07 | 株式会社東芝 | 半導体集積回路およびそのテスト方法 |
JP2009043328A (ja) * | 2007-08-08 | 2009-02-26 | Toshiba Corp | 半導体集積回路 |
US9229887B2 (en) * | 2008-02-19 | 2016-01-05 | Micron Technology, Inc. | Memory device with network on chip methods, apparatus, and systems |
US8086913B2 (en) * | 2008-09-11 | 2011-12-27 | Micron Technology, Inc. | Methods, apparatus, and systems to repair memory |
US9123552B2 (en) | 2010-03-30 | 2015-09-01 | Micron Technology, Inc. | Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same |
US8929165B2 (en) | 2011-12-21 | 2015-01-06 | Samsung Electronics Co., Ltd. | Memory device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5208782A (en) * | 1989-02-09 | 1993-05-04 | Hitachi, Ltd. | Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement |
US6282145B1 (en) * | 1999-01-14 | 2001-08-28 | Silicon Storage Technology, Inc. | Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
US6363020B1 (en) * | 1999-12-06 | 2002-03-26 | Virage Logic Corp. | Architecture with multi-instance redundancy implementation |
JP2001167595A (ja) * | 1999-12-08 | 2001-06-22 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6249465B1 (en) * | 2000-02-18 | 2001-06-19 | Hewlett-Packard Company | Redundancy programming using addressable scan paths to reduce the number of required fuses |
JP2002074981A (ja) * | 2000-09-05 | 2002-03-15 | Mitsubishi Electric Corp | 半導体集積回路装置 |
-
2002
- 2002-06-28 JP JP2002190800A patent/JP4311917B2/ja not_active Expired - Fee Related
-
2003
- 2003-05-30 US US10/448,003 patent/US6822912B2/en not_active Expired - Lifetime
- 2003-06-12 TW TW092115964A patent/TWI257700B/zh not_active IP Right Cessation
- 2003-06-25 KR KR1020030041489A patent/KR100882344B1/ko active IP Right Grant
- 2003-06-27 CN CNB031452809A patent/CN1329925C/zh not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100452236C (zh) * | 2004-05-14 | 2009-01-14 | 富士通株式会社 | 具有需要刷新操作的动态存储器单元的半导体存储器 |
CN115295059A (zh) * | 2022-10-09 | 2022-11-04 | 浙江力积存储科技有限公司 | 半导体器件及其操作方法、装置和计算机可读存储介质 |
Also Published As
Publication number | Publication date |
---|---|
TWI257700B (en) | 2006-07-01 |
KR20040002693A (ko) | 2004-01-07 |
US6822912B2 (en) | 2004-11-23 |
KR100882344B1 (ko) | 2009-02-12 |
JP2004039680A (ja) | 2004-02-05 |
CN1329925C (zh) | 2007-08-01 |
US20040001384A1 (en) | 2004-01-01 |
JP4311917B2 (ja) | 2009-08-12 |
TW200401429A (en) | 2004-01-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081017 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20081017 Address after: Tokyo, Japan, Japan Patentee after: Fujitsu Microelectronics Ltd. Address before: Kawasaki, Kanagawa, Japan Patentee before: Fujitsu Ltd. |
|
C56 | Change in the name or address of the patentee |
Owner name: FUJITSU SEMICONDUCTOR CO., LTD. Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD. |
|
CP03 | Change of name, title or address |
Address after: Kanagawa Patentee after: Fujitsu Semiconductor Co., Ltd. Address before: Tokyo, Japan Patentee before: Fujitsu Microelectronics Ltd. |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070801 Termination date: 20200627 |
|
CF01 | Termination of patent right due to non-payment of annual fee |