CN1328782C - 半导体工艺与集成电路 - Google Patents

半导体工艺与集成电路 Download PDF

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Publication number
CN1328782C
CN1328782C CNB02809395XA CN02809395A CN1328782C CN 1328782 C CN1328782 C CN 1328782C CN B02809395X A CNB02809395X A CN B02809395XA CN 02809395 A CN02809395 A CN 02809395A CN 1328782 C CN1328782 C CN 1328782C
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China
Prior art keywords
bipolar transistor
active area
layer
region
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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CNB02809395XA
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English (en)
Chinese (zh)
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CN1507656A (zh
Inventor
T·约翰森
H·诺斯特雷姆
P·阿戈特森
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Infineon Technologies AG
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Infineon Technologies AG
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Publication date
Priority claimed from SE0101567A external-priority patent/SE522527C2/sv
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN1507656A publication Critical patent/CN1507656A/zh
Application granted granted Critical
Publication of CN1328782C publication Critical patent/CN1328782C/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
    • H10P10/00—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
CNB02809395XA 2001-05-04 2002-04-29 半导体工艺与集成电路 Expired - Fee Related CN1328782C (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
SE01015676 2001-05-04
SE0101567A SE522527C2 (sv) 2001-05-04 2001-05-04 Halvledarprocess och integrerad krets
SE01030360 2001-09-13
SE0103036A SE0103036D0 (sv) 2001-05-04 2001-09-13 Semiconductor process and integrated circuit
PCT/SE2002/000838 WO2002091463A1 (en) 2001-05-04 2002-04-29 Semiconductor process and integrated circuit

Publications (2)

Publication Number Publication Date
CN1507656A CN1507656A (zh) 2004-06-23
CN1328782C true CN1328782C (zh) 2007-07-25

Family

ID=26655455

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB02809395XA Expired - Fee Related CN1328782C (zh) 2001-05-04 2002-04-29 半导体工艺与集成电路

Country Status (7)

Country Link
US (2) US20050020003A1 (enExample)
EP (1) EP1384258A1 (enExample)
JP (2) JP2005509273A (enExample)
KR (1) KR100918716B1 (enExample)
CN (1) CN1328782C (enExample)
SE (1) SE0103036D0 (enExample)
WO (1) WO2002091463A1 (enExample)

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WO2006018974A1 (ja) * 2004-08-17 2006-02-23 Rohm Co., Ltd. 半導体装置およびその製造方法
EP1630863B1 (en) 2004-08-31 2014-05-14 Infineon Technologies AG Method of fabricating a monolithically integrated vertical semiconducting device in an soi substrate
WO2006025037A1 (en) * 2004-09-02 2006-03-09 Koninklijke Philips Electronics, N.V. Contacting and filling deep-trench-isolation with tungsten
EP1646084A1 (en) 2004-10-06 2006-04-12 Infineon Technologies AG A method in the fabrication of an integrated injection logic circuit
US7638385B2 (en) * 2005-05-02 2009-12-29 Semiconductor Components Industries, Llc Method of forming a semiconductor device and structure therefor
US20070069295A1 (en) * 2005-09-28 2007-03-29 Kerr Daniel C Process to integrate fabrication of bipolar devices into a CMOS process flow
US20070158779A1 (en) * 2006-01-12 2007-07-12 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a buried damage layer
US7648869B2 (en) * 2006-01-12 2010-01-19 International Business Machines Corporation Method of fabricating semiconductor structures for latch-up suppression
US7276768B2 (en) * 2006-01-26 2007-10-02 International Business Machines Corporation Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures
US7491618B2 (en) * 2006-01-26 2009-02-17 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a conductive region
US20070194403A1 (en) * 2006-02-23 2007-08-23 International Business Machines Corporation Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods
US7439119B2 (en) * 2006-02-24 2008-10-21 Agere Systems Inc. Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method
JP2007266491A (ja) * 2006-03-29 2007-10-11 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
US7629676B2 (en) 2006-09-07 2009-12-08 Infineon Technologies Ag Semiconductor component having a semiconductor die and a leadframe
US7754513B2 (en) * 2007-02-28 2010-07-13 International Business Machines Corporation Latch-up resistant semiconductor structures on hybrid substrates and methods for forming such semiconductor structures
US7818702B2 (en) * 2007-02-28 2010-10-19 International Business Machines Corporation Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates
KR20090051894A (ko) * 2007-11-20 2009-05-25 주식회사 동부하이텍 반도체 소자의 제조 방법
DE102008062693B4 (de) * 2008-12-17 2017-02-09 Texas Instruments Deutschland Gmbh Halbleiterbauelement und Verfahren zu dessen Herstellung
GB2479372B (en) 2010-04-07 2013-07-24 Ge Aviat Systems Ltd Power switches for aircraft
CN102270576A (zh) * 2011-09-01 2011-12-07 上海宏力半导体制造有限公司 Mos晶体管制造方法
KR101821413B1 (ko) * 2011-09-26 2018-01-24 매그나칩 반도체 유한회사 소자분리구조물, 이를 포함하는 반도체 소자 및 그의 소자분리 구조물 제조 방법
US8956938B2 (en) 2012-05-16 2015-02-17 International Business Machines Corporation Epitaxial semiconductor resistor with semiconductor structures on same substrate
US9076863B2 (en) * 2013-07-17 2015-07-07 Texas Instruments Incorporated Semiconductor structure with a doped region between two deep trench isolation structures
US10468484B2 (en) * 2014-05-21 2019-11-05 Analog Devices Global Bipolar transistor
CN104269413B (zh) 2014-09-22 2017-08-11 京东方科技集团股份有限公司 阵列基板及其制作方法、液晶显示装置
US9502283B2 (en) * 2015-02-20 2016-11-22 Qualcomm Incorporated Electron-beam (E-beam) based semiconductor device features
US9768218B2 (en) * 2015-08-26 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned back side deep trench isolation structure
US10128113B2 (en) * 2016-01-12 2018-11-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9825157B1 (en) * 2016-06-29 2017-11-21 Globalfoundries Inc. Heterojunction bipolar transistor with stress component
US9923083B1 (en) 2016-09-09 2018-03-20 International Business Machines Corporation Embedded endpoint fin reveal
CN110416152A (zh) * 2019-07-26 2019-11-05 上海华虹宏力半导体制造有限公司 深槽隔离结构及工艺方法
CN115166461A (zh) * 2022-06-30 2022-10-11 上海积塔半导体有限公司 测试器件结构单元、并行测试器件结构及晶圆

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JPH07335774A (ja) * 1994-06-03 1995-12-22 Sony Corp ＢｉＭＯＳ半導体装置及びその製造方法
US5731623A (en) * 1993-10-07 1998-03-24 Kabushiki Kaisha Toshiba Bipolar device with trench structure
JPH118326A (ja) * 1997-06-18 1999-01-12 Mitsubishi Electric Corp 半導体装置の製造方法
US5960272A (en) * 1995-10-16 1999-09-28 Kabushiki Kaisha Toshiba Element-isolating construct of a semiconductor integrated circuit having an offset region between impurity doped regions, and process of manufacturing the construct
US6043130A (en) * 1999-05-17 2000-03-28 National Semiconductor Corporation Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base
US6177717B1 (en) * 1998-06-05 2001-01-23 Stmicroelectronics, S.A. Low-noise vertical bipolar transistor and corresponding fabrication process
JP2001118858A (ja) * 1999-10-18 2001-04-27 Nec Corp 半導体装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266504A (en) * 1992-03-26 1993-11-30 International Business Machines Corporation Low temperature emitter process for high performance bipolar devices
US5731623A (en) * 1993-10-07 1998-03-24 Kabushiki Kaisha Toshiba Bipolar device with trench structure
JPH07335774A (ja) * 1994-06-03 1995-12-22 Sony Corp ＢｉＭＯＳ半導体装置及びその製造方法
US5960272A (en) * 1995-10-16 1999-09-28 Kabushiki Kaisha Toshiba Element-isolating construct of a semiconductor integrated circuit having an offset region between impurity doped regions, and process of manufacturing the construct
JPH118326A (ja) * 1997-06-18 1999-01-12 Mitsubishi Electric Corp 半導体装置の製造方法
US6177717B1 (en) * 1998-06-05 2001-01-23 Stmicroelectronics, S.A. Low-noise vertical bipolar transistor and corresponding fabrication process
US6043130A (en) * 1999-05-17 2000-03-28 National Semiconductor Corporation Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base
JP2001118858A (ja) * 1999-10-18 2001-04-27 Nec Corp 半導体装置

Also Published As

Publication number Publication date
US20100055860A1 (en) 2010-03-04
CN1507656A (zh) 2004-06-23
EP1384258A1 (en) 2004-01-28
WO2002091463A1 (en) 2002-11-14
JP2009141375A (ja) 2009-06-25
KR100918716B1 (ko) 2009-09-24
SE0103036D0 (sv) 2001-09-13
KR20030092097A (ko) 2003-12-03
US20050020003A1 (en) 2005-01-27
JP2005509273A (ja) 2005-04-07

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Granted publication date: 20070725

Termination date: 20170429