CN1318208A - 具有栅电极和场板电极的横向薄膜绝缘体上硅器件 - Google Patents

具有栅电极和场板电极的横向薄膜绝缘体上硅器件 Download PDF

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CN1318208A
CN1318208A CN00801247A CN00801247A CN1318208A CN 1318208 A CN1318208 A CN 1318208A CN 00801247 A CN00801247 A CN 00801247A CN 00801247 A CN00801247 A CN 00801247A CN 1318208 A CN1318208 A CN 1318208A
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gate electrode
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CN1175496C (zh
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M·辛普森
T·莱塔维克
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Koninklijke Philips NV
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Abstract

横向薄膜绝缘体上硅(SOI)器件包括半导体衬底，在衬底上的埋层绝缘层，以及埋层绝缘层之上的SOI层中的晶体管，形成在与第一导电类型相反的第二导电类型的体区内并具有第一导电类型的源区。设置与体区邻接的第一导电类型的横向漂移区，以及设置有通过漂移区与体区横向分开的第一导电类型的漏区。栅电极设置在部分体区之上，操作期间在体区中形成沟道区，并且栅电极延伸超过与体区邻接的部分漂移区，至少通过绝缘区使体区和漂移区基本绝缘。为了提高击穿特性，介电层是设置至少在部分绝缘区和栅电极之上，以及场板电极是设置至少在部分介电层之上，介电层是直接与绝缘区接触，通过场板电极与横向晶体管器件的电极相连。

Description

具有栅电极和场板电极的横向 薄膜绝缘体上硅        器件
本发明属于绝缘体上半导体(SOI)器件领域，尤其是涉及适用于高压应用的横向SOI器件。
制造高压功率器件中，一般要对如击穿电压、体积、“ON”阻抗和工艺简单性以及可靠性等方面进行权衡和综合考虑。常常改善一种参数，如击穿电压，将导致另一个参数的退化，如“ON”阻抗。理想地，这种器件具有最小的操作和制造缺点，在各个方面都具有优越的特性。
横向薄膜SOI器件的一个突出优点的形状包括半导体衬底，在衬底上的埋层绝缘层，和在埋层绝缘层上的SOI层中的横向晶体管器件，该横向晶体管器件，如MOSFET，包括在埋层绝缘层上的半导体表面层、和具有形成在与第一导电类型相反的第二导电类型体区中的第一导电类型的源区、至少在体区的沟道区上的完全绝缘并与体区绝缘的栅电极、第一导电类型的横向漂移区、和通过漂移区与沟道区横向分离的第一导电类型的漏区。
图1中示出的这种类型的器件相关于美国专利US5,246,870(说明方法)和US5,412,241(说明器件)，作为共知的已有申请，在此将直接引用。前述专利图1示出的器件是具有各种特性的横向SOI MOSFET器件，如具有线性横向掺杂区和覆盖其上的场板的薄SOI层，从而提高操作。一般来说，这种器件是n沟道或NMOS晶体管、具有n型源区和漏区，利用常规的例如NMOS技术制造。
为了提高SOI功率器件的高电压和大电流性能参数，更先进的技术已在序列号为No.08/998,048的美国专利申请中说明，此申请是CIP，申请日是1997年12月24日，作为共知的已有申请，在此将直接引用。然而为了改进SOI器件的性能，另一种技术是形成混合器件，这种器件将器件结构的多种类型结合成单一结构。因此，例如申请日为1998年7月24日序列号为No.09/122,407的美国专利申请，作为共知的已有申请，在此将直接的引用，公开了包括相同结构的横向DMOS晶体管和LIGB晶体管的SOI器件。
因此，为了提高功率半导体器件的性能，显然采用了许多的技术和方法，在不断的努力以获得例如击穿电压、尺寸、电流输运能力和制造简单性这些参数的近乎最佳的结合。当所有的上述结构在器件性能方面提供了改善的不同标准时，没有任何一种器件或结构能完全使对于高电压、大电流操作的所有设计要求达到最佳。
因此，在高电压、大电流环境下具有高性能的晶体管器件结构是需要的，在该器件的操作参数中，特别是击穿电压，需要进一步的优化。
因而本发明的一个目的是提供在高电压、大电流环境下具有高性能的晶体管器件结构。本发明的进一步目的是提供一种操作参数如击穿电压提高的晶体管器件结构。
根据本发明，这些目的是通过前面所述类型的横向薄膜SOI器件结构获得的，在该器件中，介质层至少设置在绝缘区和栅电极的一部分上，场板电极至少设置在与绝缘区直接接触的介质层的一部分上，场板电极与横向晶体管器件的电极连接。
在本发明的优选实施例中，介质层加上绝缘区的总厚度(即总的“顶”绝缘厚度)大约等于埋层绝缘层的厚度。典型地，介质层加上绝缘区的总厚度，以及埋层绝缘的厚度，每个至少在2微米以上，最好至少是大约3微米。
在本发明的进一步优选实施例中，栅电极延伸超过横向漂移区的大约一半，并且场板电极与横向晶体管的栅电极或源电极之一连接。
根据本发明可以获得这样的横向薄膜SOI器件，其在良好性能特性的结合方面取得了显著的改善，使器件适合于高电压、大电流环境，特别是高击穿电压。
本发明的各个方面将参照对以下实施例的描述阐述清楚。
本发明可以参照以下的描述完全被理解，并结合相应的附图阅读，在附图中：
图1示出现有技术中横向薄膜SOI器件的简明剖面图；
图2示出根据本发明的优选实施例的横向薄膜SOI器件的简明剖面图；以及
图3示出根据本发明的横向薄膜SOI器件的进一步的优选实施例的简明剖面图。
在附图中，具有相同导电类型的半导体区通常在剖面图中采用同一方向的阴影线示出，并且应理解图形未按比例画出。
在图1的简明剖面图中，横向薄膜器件，此处为SOI MOS晶体管20，包括半导体衬底22、埋层绝缘层24、和在其中制作器件的半导体表面SOI层26。MOS晶体管包括一种导电类型的源区28、相反导电类型的第二体区30、第一导电类型的横向漂移区32和同样为第一导电类型的漏区34。构成了通过栅电极36基本的简化器件结构，可以看出通过氧化绝缘区38，栅电极36完全与下层的半导体表面层26绝缘，虽然应认识到对于JFET的器件，在器件的其它绝缘栅电极和下层的半导体栅极区之间将形成电连接。本发明的范围内，MOS晶体管作为本发明的起点可以有不同的性能提高的特点，例如有台阶的氧化区38A、38B，形成场板部分36A、36B的延伸栅电极结构，和薄横向漂移区部分32A，都在前述的现有技术中有详细说明，或其它所需性能提高的特点，并未脱离本发明的精神和范围。此外，MOS晶体管20同样可以包括与源区28接触的表面接触区40，源区28位于体区30中，具有与体区相同的导电类型但是更高地掺杂。图1的现有技术结构完全通过介质层42，在该介质层之上设置有金属接触层44，此处示出通过介质层42中的孔与栅电极36接触，栅电极典型为多晶硅。应注意的是在现有技术的器件中，金属接触层44位于整个栅电极36之上，因而金属接触层44不能作为相对于器件的基底部分的场板电极。
应当理解由图中示出简化的有代表性的器件描绘典型的器件结构，但在本发明的范围内使用的器件的几何尺寸和结构可以在宽范围内不同，此外，本发明可以并具有在本领域中公知的不同的基底结构的高电压薄层SOI器件的各种不同类型，例如LDMOS晶体管、LIGB晶体管和JEFT器件。
虽然之前已描述的与图1相关的现有技术的结构一般具有好的操作特性，但在最大可以获得的击穿电压比率方面仍然有限。这是因为可最大获得击穿电压是依据SOI层的厚度以及埋层绝缘层和覆盖其上或“顶”绝缘区两者的厚度。由于通常的击穿电压范围在大约600-700伏，埋层绝缘层将具有大约为2-3微米的厚度，为了最佳性能，该厚度将通过大致相同厚度的上(场氧化)绝缘区平衡。然而，假如仍然需要较高的击穿电压，需要SOI层的厚度必须降低或者绝缘区的厚度必须增加。因为降低SOI层的厚度将严重降低器件的on态特性，因此作为进一步改善击穿电压的实践，要求绝缘区的厚度增加。
虽然成本限制、制造困难以及热考虑，目前限制了实际厚度达到大约这个数值，但是利用公知的技术可完成将埋层绝缘层的厚度增加到大约4-5微米。为了最佳性能，埋层绝缘层的厚度应当通过顶绝缘区例如沿着SOI层的任何横向位置平衡或匹配，绝缘材料(介质层加上顶绝缘区，以下将讨论)的总厚度将导致在SOI层的表面出现垂直的电场，该电场大约等于或小于在相邻埋层绝缘层的SOI层的底部的垂直电场。利用用于各种绝缘和介质层的常规材料，作为以下讨论，将得到一种结构，该结构中介质层和顶绝缘区的总厚度大约等于埋层绝缘层的厚度。然而，因为顶绝缘区是通过热氧化产生的，所以对于这一层可以获得的厚度的实际上限大约为2微米。这是因为控制热氧化的化学工艺的固有的物理局限性。由于氧化厚度增加，达到削弱转折(diminishing returns)点，以至增加氧化时间和/或温度氧化厚度不在出现显著地增加。这种现象就是公知的Deal-Grove氧化率定律，也是众所周知的现有技术中的那些常规技术。因此，为了获得较厚的顶绝缘区，必须采用一些其它技术。
图2示出的器件结构中，正如以下所述，通过器件上表面结构的变化，在器件的相关部分中，主要是指漂移区的漏侧区之上的那部分，获得此较厚的顶绝缘区。将在以下描述。
图2示出的器件中，在图l中形成场板的延伸栅电极结构的部分36A、36B在横向短，在漂移区32的中心部分之上终止，因此栅电极延伸超过漂移区的大约一半，而不像图1中那样延伸超过了漂移区的大部分。介质层42设置在栅电极和顶绝缘区的目前暴露部分之上，即在氧化区38B。介质层42可以是有利于淀积的介质，例如TEOS(原硅酸四乙脂)或氮化硅。
参照图1现有技术的结构，在图2的结构中，栅电极金属接触层44不防碍栅电极36的缩短，而进一步横向延伸到右边如图2所示超过栅电极36的横向端部，并下降到在漂移区32的右手侧之上的顶绝缘区38的右手侧之上的介质层42上。栅电极金属接触层44的此延伸部分，图2中标明为44A，适于形成场板电极，该场板电极提高器件的高电压性能。
依据本发明，介质层42的准备有两个因素的考虑。首先，它为栅电极36提供上绝缘层，如现有技术中一样，其次，它适于增加场板电极部分44A和下基底漂移区32之间绝缘材料的总厚度。这样就依次允许基底埋层绝缘层24制得更厚，提供在漂移区之上的绝缘材料的总厚度使其大约等于漂移区之下的绝缘材料的厚度，由此在现有技术不能实现的方式下，为高压操作优化器件结构。场板是通过栅电极36的延伸部分36A形成，延伸部分延伸超过漂移区的大部分，延伸距离通过热氧化的厚度单独地确定。由于该热氧化限定在它的最大可获得厚度，如上面提及，最有利的物理结构，称作较厚的埋层绝缘层和具有总厚度大约等于埋层绝缘层的厚度的上绝缘区，将不能获得。
同时应认识到许多不同的结构和选择落在本发明的范围内是可以预期的，埋层绝缘层的厚度以及介质层和绝缘区的总厚度每个应至少在2微米之上，并且优选为至少大约3微米。利用目前可利用的技术，并考虑到实际因素例如成本限制、制造困难、和热处理的考虑，每个都采用现有技术，上下漂移区的整个绝缘厚度能增加到大约4-5微米，虽然应清楚地认识到本发明并不限定此厚度。还应认识到由于绝缘区38，在其最厚部分38B，不仅可以形成大约2微米的厚度，为了获得用于某特定应用的所需的上绝缘层的总厚度，上绝缘区的所需总厚度的保留部分将从介质层42形成。
本发明的另一个应用在图3的简明剖面图中示出。因为图3所示的器件结构的较低部分完全与图2所示的器件结构的那一部分相同，由相同的附图标记标明相同的元件，器件的这部分将不在此进行详细的描述。图3的结构与图2中所示的不同之处在于，场板电极44而并非栅电极36，场板电极44不仅延伸到右边(44A)而且延伸到左边(44B)并穿过基底层中的孔往下延伸到SOI层26从与源区28和表面接触区40接触。这种结构具有降低结构的Miller电容的附加优点，并且应注意到在这种结构中，栅电极和场板电极电独立，在图1的现有技术结构中不能获得，由于场板是栅电极的整体延伸因此不能形成电独立。
在上述的方法中，本发明提供一种在高电压、大电流环境下具有高性能并且提高操作参数特别是击穿电压的晶体管器件结构。
在参照几个优选实施例己对本发明进行了详细的展示和描述的同时，还应当理解，通过本领域的普通技术，在形式和细节上进行的各种变化并未脱离本发明的精神和范围。在本申请中，应理解前述器件的词“一种”或者“一个”并不排除多个元件的情况，并且词“包含”并不排除存在不同于说明书和权利要求中的其它元件和步骤的情况。

Claims (11)

1．一种横向薄膜绝缘体上硅(SOI)器件包含半导体衬底(22)，在所述衬底上的埋层绝缘层(24)，和在所述埋层绝缘层上的SOI层(26)中的横向晶体管器件并具有第一导电类型的源区(28)、该源区形成在与第一导电类型相反的第二导电类型的体区(30)内、所述第一导电类型的横向漂移区(32)与所述体区邻接、所述第一导电类型的漏区(34)通过所述横向漂移区与所述体区横向分离，以及所述体区的一部分上的栅电极(36)，操作期间在体区中形成的沟道区、并且该沟道区在与所述体区邻接的所述横向漂移区的一部分之上延伸，所述栅电极通过绝缘区(38,38A)至少与所述体区和漂移区完全绝缘，进一步包含在所述绝缘区和所述栅电极的至少一部分之上的绝缘层(42)，以及在所述介质层的至少一部分之上的场板电极(44,44A)、所述介质层直接与所述绝缘区接触，所述场板电极与所述横向晶体管器件的电极(36,28)连接。
2．如权利要求1所述的横向薄膜绝缘体上硅(SOI)器件，其特征在于：所述介质层和所述绝缘区的总厚度大约等于所述埋层绝缘层的厚度。
3．如权利要求2所述的横向薄膜绝缘体上硅(SOI)器件，其特征在于：每个所述总厚度和所述厚度至少在大约2微米之上。
4．如权利要求2所述的横向薄膜绝缘体上硅(SOI)器件，其特征在于：所述栅电极延伸超过所述横向漂移区的大约一半。
5．如权利要求2所述的横向薄膜绝缘体上硅(SOI)器件，其特征在于：所述场板电极(44)与所述横向晶体管器件的栅电极(36,36A)连接。
6．如权利要求2所述的横向薄膜绝缘体上硅(SOI)器件，其特征在于：所述场板电极(44)与所述横向晶体管器件的源电极(28)连接。
7．如权利要求2所述的横向薄膜绝缘体上硅(SOI)器件，其特征在于：所述栅电极由多晶硅组成，所述场板电极由金属组成，所述绝缘区由热氧化组成以及所述介质层由淀积的介质组成。
8．如权利要求2所述的横向薄膜绝缘体上硅(SOI)器件，其特征在于：所述的横向晶体管器件由LDMOS组成。
9．如权利要求2所述的横向薄膜绝缘体上硅(SOI)器件，其特征在于：所述的横向晶体管器件由LIGB组成。
10．如权利要求2所述的横向薄膜绝缘体上硅(SOI)器件，其特征在于：所述的横向晶体管器件由JFET组成。
11．如权利要求1所述的横向薄膜绝缘体上硅(SOI)器件，其特征在于：所述介质层和所述绝缘区的总厚度以及所述埋层绝缘层的厚度可以选择以至，在沿着SOI层的任意横向位置，在SOI层的表面的垂直电场将大约等于或小于与埋层绝缘层邻接的SOI层的底部的垂直电场。
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