WO2012003657A1 - Soi高压功率器件的制备方法 - Google Patents

Soi高压功率器件的制备方法 Download PDF

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WO2012003657A1
WO2012003657A1 PCT/CN2010/076667 CN2010076667W WO2012003657A1 WO 2012003657 A1 WO2012003657 A1 WO 2012003657A1 CN 2010076667 W CN2010076667 W CN 2010076667W WO 2012003657 A1 WO2012003657 A1 WO 2012003657A1
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region
oxide layer
voltage power
power device
high voltage
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PCT/CN2010/076667
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English (en)
French (fr)
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程新红
王中健
俞跃辉
何大伟
徐大伟
夏超
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中国科学院上海微系统与信息技术研究所
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Priority to US13/133,871 priority Critical patent/US8460976B2/en
Publication of WO2012003657A1 publication Critical patent/WO2012003657A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0886—Shape

Definitions

  • the invention relates to a method for preparing a SOI device, in particular to a method for preparing a SOI high voltage power device. Background technique
  • Power ICs sometimes called high-voltage integrated circuits, are an important branch of modern electronics, providing high-speed, highly integrated, low-power, and radiation-resistant new circuits for a variety of power conversion and energy processing devices. Control systems, automotive electronics, display device drivers, communications and lighting, and other important areas of defense and aerospace. The rapid expansion of its application range has placed higher demands on the high-voltage components of its core parts.
  • SOI silicon-on-insulator
  • IC products integrating SOI high voltage power devices above 600V are widely used in fluorescent lamps, switching power supply control and other fields.
  • conventional SOI high voltage devices prevent the depletion layer from spreading toward the substrate due to the presence of a dielectric buried layer (BOX), and the vertical breakdown voltage is low.
  • BOX dielectric buried layer
  • the design of SOI high voltage devices of 200V and below is relatively easy, and the design of products above 600V is difficult.
  • the thickness of the top silicon of the SOI material is generally greater than 1 micron.
  • a local oxidation thinning technique that is, a LOCOS process, is employed in the process.
  • the problem with the current technology is that it takes a long time to perform local oxidation to form a field oxide layer of about 2 microns, and the field oxide layer is formed to be nearly 1 micron higher than the top plane of the silicon wafer, as shown in Fig. 1, on the SOI substrate. (It includes bottom silicon 11, oxide interlayer 12 and top Layered silicon 13)
  • the oxide layer 14 is formed in a localized region that is significantly higher than the upper surface of the SOI substrate.
  • An object of the present invention is to provide a method for fabricating a S0I high voltage power device to avoid problems such as a decrease in lithography precision due to an oxide layer being higher than an SOI substrate.
  • the present invention provides a method for preparing a SOI high voltage power device, comprising the steps of: 1) forming a first oxide layer in a partial region of a surface of a SOI substrate including a bottom layer, an oxide interlayer, and a top silicon layer to thin the SOI; The top silicon thickness of the corresponding portion of the substrate; 2) removing the first oxide layer to expose the top silicon portion under the first oxide layer, thereby forming a recessed region at a corresponding portion of the surface of the SOI substrate; 3) Forming a second oxide layer in the recessed region to keep the surface of the second oxide layer flush with the surface of the SOI substrate; 4) performing photolithography on the structure on which the second oxide layer has been formed Doping treatment to form a P-type region and an N-type region as drain and source of the high-voltage power device, and a gate region as a gate, respectively; 5) Structure in which a P-type region and an N-type region have been formed Depositing a third
  • the metal sub-region contacting the gate region is a metal field plate, one end of the metal field plate is close to a metal sub-region contacting the drain region; and the other end is in contact with the gate region. .
  • the material of the gate region may be polysilicon.
  • the formed P-type region may include: a p-well body region, an ohmic contact region, and a P-type body contact region sequentially formed after doping the top layer of the SOI substrate; the formed N-type region may be It is an ohmic contact zone.
  • the high voltage power device formed by the above method is a lateral device, such as a lateral double diffusion field effect transistor or a lateral insulated gate bipolar transistor.
  • the method for preparing the SOI high voltage power device of the present invention can produce a field oxide layer substantially flush with the top of the SOI substrate by two-step local oxidation, and after the photolithography, a certain thickness of the oxide layer is deposited. Above the drift region, the thickness of the oxide layer above and below the top silicon of the thinned SOI substrate is substantially equal, forming a symmetrical structure, which can effectively avoid the problem that the accuracy of the lithography is affected by the unevenness of the top, and at the same time, the formed High voltage power devices can withstand 700V Above pressure resistance.
  • Figure 1 is a schematic diagram of the existing LOCOS process.
  • FIGS. 2a-2d are schematic diagrams showing the process flow of a method for preparing a S0I high voltage power device of the present invention.
  • FIG. 3 is a schematic diagram showing potential distribution of devices and the like formed by the method for fabricating the S0I high voltage power device of the present invention.
  • the method for preparing the SOI high voltage power device of the present invention can mainly include the following steps:
  • a first oxide layer 24 is formed on a portion of the surface of the SOI substrate including the underlayer 21, the oxidized interlayer 22, and the top silicon 23 to thin the top silicon thickness of the corresponding portion of the SOI substrate, as shown in FIG. 2a, forming a first
  • the method of oxidizing layer 24 may employ a thermal oxidation method. Of course, other methods may be employed, which are known to those skilled in the art and will not be described in detail herein.
  • the underlayer 21 may be an n-type heavily doped substrate or a p-type heavily doped substrate.
  • the first oxide layer 24 is removed to expose the top silicon portion under the first oxide layer 24, thereby forming a recess region 25 at a corresponding portion of the surface of the SOI substrate, as shown in FIG. 2b.
  • a second oxide layer 26 is formed in the recess region 25 so that the surface of the second oxide layer 26 is flush with the surface of the SOI substrate, as shown in Fig. 2c. Since the first silicon oxide surface is exposed after the first oxide layer 24 is removed, the oxidation rate is relatively accelerated, and the finally formed second oxide layer top is substantially flush with the top silicon.
  • the N-type region is an ohmic contact region 27, and the P-type region includes a p-well body region 281, an ohmic contact region 282, and a p-type body contact region 283, the gate region 30
  • the material can be polysilicon.
  • a third oxide layer 29 is deposited over the drift region of the structure in which the P-type region and the N-type region have been formed, so that the sum of the thicknesses of the third oxide layer 29 and the second oxide layer 26 (ie, 26+)
  • the thickness of 29 is approximately the same as the thickness of the oxidized interlayer 22 in the SOI substrate. Since the structure formed by the above steps (ie, the L0C0S structure) is thin, the polysilicon cannot be directly elongated, otherwise the breakdown voltage will be low, so after completing several important lithography, it is in L0C0S.
  • a portion of the oxide layer i.e., the third oxide layer
  • respective metal sub-regions 284, 271 and 301 which are in contact with the P-type region, the N-type region and the gate region 30, respectively, are formed on the structure in which the third oxide layer has been formed, thereby forming a high voltage power device.
  • the metal sub-region 301 in contact with the gate region 30 is a metal field plate, and one end of the metal field plate is close to the metal sub-region 271 in contact with the drain region 27; The gate region 30 is in contact.
  • the equipotential line distribution of the resulting high-voltage power device is shown in Figure 3.
  • the 50- ⁇ m drift region can withstand 700V (as the device formed in this embodiment can withstand 720V) and has more withstand voltage than conventional devices. Low on-state resistance.
  • a lateral device such as a lateral double diffused field effect transistor (LDM0S) or a lateral insulated gate bipolar transistor (LIGBT).
  • LDM0S lateral double diffused field effect transistor
  • LIGBT lateral insulated gate bipolar transistor
  • the method for preparing the SOI high voltage power device of the present invention can form an oxide layer substantially flush with the top of the SOI substrate by a two-step partial oxidation method, and then deposit after performing the subsequent several steps of the photolithography process.
  • a certain thickness of the oxide layer is above the drift region, so that the thickness of the oxide layer above and below the thinned top layer silicon is substantially equal, forming a symmetrical structure; in order to effectively regulate the charge in the drift region, and then extending the metal field plate above the oxide layer, Therefore, the formed high-voltage power device can withstand the withstand voltage of 700V or more, effectively avoiding the problems in the prior art that the oxide layer is higher than the top of the SOI substrate and affecting the subsequent lithography precision.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

提供一种SOI高压功率器件的制备方法，首先在SOI基板表面的部分区域形成第一氧化层（24），再去除所述第一氧化层（24）以便形成凹陷区（25），然后在凹陷区（25）形成第二氧化层（26），以便使第二氧化层（26）的表面与SOI基板表面保持平齐，再在包含第二氧化层（26）的结构上进行包括光刻、掺杂在内的处理以分别形成作为高压功率器件漏极和源极的P型区域（281，282，283）和N型区域（27）、以及作为栅极的栅极区域（30），随后在已形成P型区域（281，282，283）和N型区域（27）的结构的漂移区上方淀积第三氧化层（29），使第三氧化层（29）和第二氧化层（26）的厚度之和与SOI基板中的氧化夹层（22）的厚度接近一致，最后再生成分别与P型区域（281，282，283）、N型区域（27）及栅极区域（30）相接触的各金属子区域（284，271，301），由此形成耐高压的高压功率器件。

Description

SOI高压功率器件的制备方法 技术领域
本发明涉及一种 S0I器件的制备方法， 特别涉及一种 S0I高压功率器件的制备方法。 背景技术
功率集成电路有时也称高压集成电路， 是现代电子学的重要分支， 可为各种功率变换 和能源处理装置提供高速、 高集成度、 低功耗和抗辐照的新型电路， 广泛应用于电力控制 系统、 汽车电子、 显示器件驱动、 通信和照明等日常消费领域以及国防、 航天等诸多重要 领域。 其应用范围的迅速扩大， 对其核心部分的高压器件也提出了更高的要求。
由于功率集成电路常常结合了高压功率晶体管、控制转换器以及单片逻辑功能器件等， 因此高压器件和低压逻辑器件必须集成在一块芯片上。 绝缘体上硅 （SOI ) 作为一种理想 的介质隔离材料， 可以有效地实现高、 低功率模块， 以及高、 低电压器件之间的隔离， 彻 底消除电干扰， 简化器件的结构设计， 而且 SOI隔离区面积较结隔离小， 大大节约了管芯 面积， 减小了寄生电容， 可以方便地集成不同的电路和器件。 因此， SOI技术应用于高压 器件及功率集成电路具有明显的优势， 有着广泛的应用前景。
集成 600V以上 SOI高压功率器件的 IC产品广泛应用于荧光灯， 开关电源控制等领 域。 与体硅 SOI高压器件相比， 常规 SOI高压器件由于其介质埋层 （BOX) 的存在， 阻 止了耗尽层向衬底扩展， 其纵向击穿电压较低。 通常 200V及其以下 SOI高压器件的设计 相对比较容易， 而 600V以上产品的设计难度较大。
考虑 SOI顶层硅厚度对临界击穿电场的影响， 当硅膜厚度较大时（通常大于 1微米）， 随其厚度增加,纵向击穿电压增大； 当硅膜厚度较小时 （通常小于 1微米） ， 随其厚度减 小， 纵向击穿电压增大。 目前采用超薄顶层硅 （0.2~0.5微米）， 利用缩短电离积分路径来 提高硅的纵向临界击穿电场， 并采用线性漂移区掺杂实现均匀分布电场， 是制造 600V以 上 SOI高压器件最有效方法。
然而， 由于现有工艺的限制， SOI材料顶层硅厚度一般大于 1 微米， 为实现 0.2~0.5 微米薄硅层， 工艺上采用局部氧化减薄技术， 即 LOCOS工艺。 目前的技术存在的问题是 需要较长时间进行局部氧化以形成 2微米左右的场氧化层， 并且场氧化层形成后明显高出 硅片顶部平面近 1微米， 如图 1所示， 在 SOI基底 （其包括底层硅 11、 氧化夹层 12和顶 层硅 13) 局部区域制作出的氧化层 14， 其明显高出 SOI基底上表面。 虽然可以在其上直 接延长多晶硅栅以调控漂移区电场， 但是高出部分对后续光刻过程的精度容易造成较大影 响。 因此， 如何解决这一问题实已成为本领域技术人员亟待解决的技术课题。 发明内容
本发明的目的在于提供一种 S0I高压功率器件的制备方法， 以避免因氧化层高出 SOI 基底而导致光刻精度降低等问题。
为了达到上述目的及其他目的， 本发明提供的 S0I高压功率器件的制备方法， 包括步 骤： 1 ) 在包含底层、 氧化夹层和顶层硅的 S0I 基板表面的部分区域形成第一氧化层以减 薄 S0I 基板的相应部分的顶层硅厚度； 2) 去除所述第一氧化层以便使处于所述第一氧化 层下方的顶层硅部分暴露， 从而在所述 S0I 基板表面的相应部位形成凹陷区； 3) 在所述 凹陷区形成第二氧化层， 以便使所述第二氧化层的表面与所述 S0I基板表面保持平齐； 4) 在已形成所述第二氧化层的结构上进行包括光刻、 掺杂在内的处理以分别形成作为高压功 率器件漏极和源极的 P型区域和 N型区域、 以及作为栅极的栅极区域； 5) 在已形成 P型 区域和 N型区域的结构的漂移区上方淀积第三氧化层， 使所述第三氧化层和所述第二氧化 层的厚度之和与所述 S0I基板中的氧化夹层的厚度接近一致； 以及 6) 在已形成第三氧化 层的结构上生成分别与所述 P型区域、 N型区域及栅极区域相接触的各金属子区域， 由此 形成高压功率器件。
较佳的， 与所述栅极区域相接触的金属子区域为金属场板， 所述金属场板一端接近与 所述漏极区域相接触的金属子区域； 另一端与所述栅极区域接触。
其中， 所述栅极区域的材料可为多晶硅。
较佳的， 所形成的 P型区域可包括： 对所述 S0I基板的顶层硅掺杂后依序形成的 p阱 体区、 欧姆接触区和 P型体接触区； 所形成的 N型区域可为欧姆接触区。
此外， 上述方法所形成的高压功率器件为横向器件， 例如为横向双扩散场效应管或横 向绝缘栅双极晶体管等。
综上所述，本发明的 S0I高压功率器件的制备方法通过两步局部氧化，可制作出与 S0I 基板顶部基本平齐的场氧化层， 而且光刻后， 再淀积一定厚度的氧化层在漂移区上方， 使 减薄后的 S0I基板的顶层硅上方和下方的氧化层厚度大致相等， 形成对称结构， 可有效避 免因顶部不平齐而影响光刻的精度等问题， 同时可使所形成的高压功率器件能承受 700V 以上耐压。 附图说明
图 1为现有 LOCOS工艺示意图。
图 2a-2d为本发明的 S0I高压功率器件的制备方法的工艺流程示意图。
图 3为本发明的 S0I高压功率器件的制备方法所形成的器件等势线分布示意图。
具体实施方式
以下将结合附图对本发明的 S0I高压功率器件的制备方法进行详细描述。
本发明的 S0I高压功率器件的制备方法主要可包括以下步骤：
首先， 在包含底层 21、氧化夹层 22和顶层硅 23的 S0I基板表面的部分区域形成第一 氧化层 24， 以减薄 S0I基板的相应部分的顶层硅厚度， 如图 2a所示， 形成第一氧化层 24 的方法可采用热氧化法， 当然， 也可采用其他方法， 此为本领域技术人员所知悉， 故在此 不再详述。 此外， 如果制备的 S0I高压功率器件为横向双扩散场效应管， 则底层 21可以 是 n型重掺杂衬底， 也可以是 p型重掺杂衬底。
接着，去除所述第一氧化层 24以便使处于所述第一氧化层 24下方的顶层硅部分暴露， 从而在所述 S0I基板表面的相应部位形成凹陷区 25， 如图 2b所示。
接着， 在所述凹陷区 25形成第二氧化层 26， 以便使所述第二氧化层 26的表面与所述 S0I基板表面保持平齐， 如图 2c所示。 由于去除第一步氧化层 24后， 使顶层硅表面裸露 出来， 从而氧化速度相对加快， 并且最终形成的第二氧化层顶部与顶层硅基本平齐。
接着， 在已形成所述第二氧化层 26 的结构上进行包括光刻、 掺杂、 生长在内的处理 以分别形成作为高压功率器件漏极和源极的 P型区域和 N型区域、 以及作为栅极的栅极区 域 30。 如图 2d所示， 在本实施例中， N型区域为欧姆接触区 27， P型区域包括 p阱体区 281、 欧姆接触区 282和 p型体接触区 283， 所述栅极区域 30的材料可以为多晶硅。
接着， 在已形成 P型区域和 N型区域的结构的漂移区上方淀积第三氧化层 29， 使所述 第三氧化层 29和所述第二氧化层 26的厚度之和 （即 26+29的厚度） 与所述 S0I基板中的 氧化夹层 22的厚度接近一致。 由于上述步骤所形成的结构 （即 L0C0S结构） 厚度较薄， 不能直接拉长多晶硅，否则会导致击穿电压较低， 因此在完成几步重要光刻后，再在 L0C0S 上方淀积部分氧化层 （即第三氧化层）， 使其与第二氧化层 26 组合后形成和氧化夹层 22 的对称。
最后， 在已形成第三氧化层的结构上生成分别与所述 P型区域、 N型区域及栅极区域 30相接触的各金属子区域 284、 271和 301， 由此形成高压功率器件。 如图 2d所示， 与所 述栅极区域 30相接触的金属子区域 301为金属场板， 所述金属场板一端接近与所述漏极 区域 27相接触的金属子区域 271 ; 另一端与所述栅极区域 30接触。 最终形成的高压功率 器件的等势线分布如图 3所示， 50微米漂移区长度下即可承受 700V (如本实施例所形成 的器件能承受 720V) 以上耐压， 并具备比传统器件更低的开态电阻。
采用上述步骤可以形成横向器件， 例如横向双扩散场效应管 （LDM0S) 或横向绝缘栅 双极晶体管 （LIGBT) 等。
需要说明的是， 上述各步骤所采用的工艺手段及条件等都已为本领域技术人员所知 悉， 故在此不再详述。
综上所述，本发明的 S0I高压功率器件的制备方法采用两步局部氧化法可制作出与 S0I 基片顶部基本平齐的氧化层， 并在完成后续几步光刻过程后， 再淀积一定厚度的氧化层在 漂移区上方， 使减薄后的顶层硅上方和下方的氧化层厚度大致相等， 形成对称结构； 为了 对漂移区电荷进行有效调控， 再在氧化层上方延展金属场板， 由此可使所形成的高压功率 器件能承受 700V以上耐压， 有效避免现有技术中因氧化层高出 S0I基片顶部而影响后续 光刻精度等问题。
上述实施例仅列示性说明本发明的原理及功效， 而非用于限制本发明。 任何熟悉此项 技术的人员均可在不违背本发明的精神及范围下， 对上述实施例进行修改。 因此， 本发明 的权利保护范围， 应如权利要求书所列。

Claims

权利 要 求 书
1. 一种 SOI高压功率器件的制备方法， 其特征在于包括步骤：
1 ) 在包含底层、 氧化夹层和顶层硅的 S0I基板表面的部分区域形成第一氧化层以减 薄 S0I基板的相应部分的顶层硅厚度；
2) 去除所述第一氧化层以便使处于所述第一氧化层下方的顶层硅部分暴露， 从而在 所述 S0I基板表面的相应部位形成凹陷区；
3) 在所述凹陷区形成第二氧化层， 以便使所述第二氧化层的表面与所述 S0I基板表 面保持平齐；
4) 在已形成所述第二氧化层的结构上进行包括光刻、 掺杂、 生长在内的处理以分别 形成作为高压功率器件漏极和源极的 P型区域和 N型区域、 以及作为栅极的栅极 区域；
5) 在已形成 P型区域和 N型区域的结构的漂移区上方淀积第三氧化层， 使所述第三 氧化层和所述第二氧化层的厚度之和与所述 S0I基板中的氧化夹层的厚度接近一 致；
6) 在已形成第三氧化层的结构上生成分别与所述 P型区域、 N型区域及栅极区域相 接触的各金属子区域， 由此形成高压功率器件。
2. 如权利要求 1所述的 S0I高压功率器件的制备方法， 其特征在于： 与所述栅极区域相 接触的金属子区域为金属场板，所述金属场板一端接近与所述漏极区域相接触的金属 子区域； 另一端与所述栅极区域接触。
3. 如权利要求 1所述的 S0I高压功率器件的制备方法， 其特征在于： 所述栅极区域的材 料为多晶硅。
4. 如权利要求 1所述的 S0I高压功率器件的制备方法， 其特征在于： 所形成的 P型区域 包括： 对所述 S0I基板的顶层硅掺杂后依序形成的 p阱体区、欧姆接触区和 p型体接 触区。
5. 如权利要求 1所述的 S0I高压功率器件的制备方法， 其特征在于： 所形成的 N型区域 为欧姆接触区。
6. 如权利要求 1所述的 S0I高压功率器件的制备方法， 其特征在于： 步骤 6)所形成的 高压功率器件为横向器件。
7. 如权利要求 6所述的 S0I高压功率器件的制备方法， 其特征在于： 所述横向器件为横 向双扩散场效应管和横向绝缘栅双极晶体管中的一种。
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Publication number Priority date Publication date Assignee Title
US9570437B2 (en) * 2014-01-09 2017-02-14 Nxp B.V. Semiconductor die, integrated circuits and driver circuits, and methods of maufacturing the same
CN106684136A (zh) * 2017-02-27 2017-05-17 电子科技大学 一种soi横向绝缘栅双极晶体管
CN106847882A (zh) * 2017-02-27 2017-06-13 电子科技大学 一种soi‑ligbt器件
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CN106847883A (zh) * 2017-02-27 2017-06-13 电子科技大学 可抑制Snapback现象的SOI‑LIGBT器件及其制造方法
CN106981505A (zh) * 2017-03-30 2017-07-25 电子科技大学 一种半薄硅层结构的横向高压器件
CN106981518A (zh) * 2017-03-30 2017-07-25 电子科技大学 一种具有超结结构的soi横向高压器件
CN107068736B (zh) * 2017-03-30 2020-07-10 电子科技大学 一种soi横向高压器件
US10522388B1 (en) 2018-08-24 2019-12-31 Tower Semiconductor Ltd. Method of forming high-voltage silicon-on-insulator device with diode connection to handle layer
CN111244178B (zh) * 2020-01-15 2020-10-16 合肥晶合集成电路有限公司 扩散型场效应晶体管的形成方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0549042A2 (en) * 1991-12-20 1993-06-30 Koninklijke Philips Electronics N.V. Improved high voltage thin film transistor having a drift region with a linear doping profile and a field plate
CN1318208A (zh) * 1999-06-30 2001-10-17 皇家菲利浦电子有限公司 具有栅电极和场板电极的横向薄膜绝缘体上硅器件
CN1507662A (zh) * 2001-09-10 2004-06-23 �ձ�������ʽ���� 半导体器件及其制造方法
CN101944505A (zh) * 2010-07-06 2011-01-12 中国科学院上海微系统与信息技术研究所 具有沟槽结构的soi高压功率器件芯片的制备方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100854077B1 (ko) * 2002-05-28 2008-08-25 페어차일드코리아반도체 주식회사 웨이퍼 본딩을 이용한 ｓｏｉ 기판 제조 방법과 이 ｓｏｉ기판을 사용한 상보형 고전압 바이폴라 트랜지스터 제조방법
US6661059B1 (en) * 2002-09-30 2003-12-09 Koninklijke Philips Electronics N.V. Lateral insulated gate bipolar PMOS device
CN100568534C (zh) * 2008-01-29 2009-12-09 电子科技大学 具有栅极场板的薄膜soi厚栅氧功率器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0549042A2 (en) * 1991-12-20 1993-06-30 Koninklijke Philips Electronics N.V. Improved high voltage thin film transistor having a drift region with a linear doping profile and a field plate
CN1318208A (zh) * 1999-06-30 2001-10-17 皇家菲利浦电子有限公司 具有栅电极和场板电极的横向薄膜绝缘体上硅器件
CN1507662A (zh) * 2001-09-10 2004-06-23 �ձ�������ʽ���� 半导体器件及其制造方法
CN101944505A (zh) * 2010-07-06 2011-01-12 中国科学院上海微系统与信息技术研究所 具有沟槽结构的soi高压功率器件芯片的制备方法

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