CN108321116A - 具有半导体元件的集成电路结构及其制造方法 - Google Patents

具有半导体元件的集成电路结构及其制造方法 Download PDF

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CN108321116A
CN108321116A CN201710036189.3A CN201710036189A CN108321116A CN 108321116 A CN108321116 A CN 108321116A CN 201710036189 A CN201710036189 A CN 201710036189A CN 108321116 A CN108321116 A CN 108321116A
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substrate
area
ultra
deep groove
groove isolation
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徐尉伦
巩永谦
叶铭琮
刘彦秀
吕安泰
许尧壁
龚吉富
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201710036189.3A priority Critical patent/CN108321116A/zh
Priority to US15/427,512 priority patent/US10529715B2/en
Publication of CN108321116A publication Critical patent/CN108321116A/zh
Priority to US16/697,800 priority patent/US10784261B2/en
Priority to US16/995,941 priority patent/US11417654B2/en
Priority to US17/741,123 priority patent/US11916075B2/en
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Abstract

本发明公开一种具有半导体元件的集成电路结构及其制造方法。该集成电路结构包括：一基板，具有相对的一顶表面和一底表面，且基板具有多个区域；多个半导体元件形成于基板，且分别位于不同区域内，和一超深沟槽隔离结构，形成于基板内且围绕各个区域的周围，以隔离位于不同区域的该些半导体元件。其中超深沟槽隔离结构自基板的顶表面延伸至底表面而穿过基板。

Description

具有半导体元件的集成电路结构及其制造方法
技术领域
本发明涉及一种集成电路结构及其制造方法，且特别是涉及一种具有半导体元件的集成电路结构及其制造方法。
背景技术
对半导体科技来说，持续缩小集成电路结构的尺寸、改善速率、增进效能、提高密度及降低成本等等，都是重要的发展目标。即使集成电路结构的尺寸缩小或是如何发展，半导体元件的电子特性都必须至少维持或是加以改善，以符合市场对电子产品的要求。集成电路结构的各层与所属半导体元件如有缺陷或损伤，将会对结构的电性表现造成无法忽视的影响。
举例来说，制造传统集成电路结构时，基板的低压区域(low-side region)和高压区域(high-side region)中，各区域包括至少一侧向扩散型金属氧化物半导体晶体管，一般需要在低压区域和高压区域之间，需具有足够宽的间距(一般超过100微米以上)，以承受大幅度的压降和维持集成电路结构的电子特性；然而，此宽间距的存在也限制了集成电路结构可缩小的尺寸。
发明内容
本发明是有关于一种具有半导体元件的集成电路结构及其制造方法，形成于基板的不同区域内的半导体元件是以一超深沟槽隔离结构(an ultra-deep(UD)trenchisolation structure)隔离。
根据一实施例，提出一种集成电路结构，包括：一基板，具有相对的一顶表面和一底表面，且基板具有多个区域；多个半导体元件形成于基板，且分别位于不同区域内，和一超深沟槽隔离结构，形成于基板内且围绕各个区域的周围，以隔离位于不同区域的该些半导体元件。其中超深沟槽隔离结构自基板的顶表面延伸至底表面而穿过基板。
根据一实施例，提出一种集成电路结构的制造方法，包括：提供一基板，且基板具有多个预定区域；形成一超深沟槽隔离结构于该基板内且围绕该些预定区域的周围，其中超深沟槽隔离结构自基板的顶表面向下延伸；和研磨基板的背面，直到超深沟槽隔离结构的下表面暴露于基板的底表面，其中基板的底表面相对于顶表面。
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合所附附图，作详细说明如下。然而，本发明的保护范围应以所附的权利要求所界定的为准。
附图说明
图1A为本发明一实施例的集成电路结构的一基板的上视图；
图1B为沿着图1A的剖面线1B-1B所绘制的基板的剖面示意图；
图2为本发明一实施例的基板与形成于基板区域内的半导体元件的剖面示意图；
图3为本发明另一实施例的基板与形成于基板区域内的半导体元件的剖面示意图；
图4为本发明又一实施例的基板与形成于基板区域内的半导体元件的剖面示意图；
图5A-图5B为本发明一实施例的集成电路结构的制造方法示意图。
符号说明
10、10’：基板
10a：基板的顶表面
10b：基板的底表面
102：N型基板
104：N型外延层
106：P型体区
HVPW：高压P型阱
HVNW：高压N型阱
N-drift：N型飘移区
P-drift：P型飘移区
D：漏极区
S、108：源极区
110：栅极氧化物
112、113：栅极
114：水平通道
115：绝缘层
Tch：垂直沟槽
12：超深沟槽隔离结构
12a：超深沟槽隔离结构的上表面
12b：超深沟槽隔离结构的下表面
TUD：超深沟槽隔离结构的深度
WUD：超深沟槽隔离结构的宽度
AHS：高压区域
ALS：低压区域
A1：第一区域
A2：第二区域
ALC：逻辑区域
具体实施方式
根据本发明的实施例，提出一种具有半导体元件的集成电路结构及其制造方法，其中形成于基板的不同区域内的多个半导体元件以一超深沟槽隔离结构(an ultra-deep(UD)trench isolation structure)隔离。根据实施例，超深沟槽隔离结构穿过基板，亦即自基板的顶表面延伸至基板的底表面。对于应用的集成电路结构来说，实施例设计提出的超深沟槽隔离结构对于基板不同区域内的半导体元件提供了一个优异的隔离方式。再者，应用具超深沟槽隔离结构的实施例设计可缩小集成电路结构的尺寸，进而节省制造成本。另外，一些实施例中，部分区域例如邻近于高压区域AHS的第一区域A1和/或邻近于低压区域ALS的第二区域A2包括垂直式侧向扩散型金属氧化物半导体(vertical double-diffusedmetal oxide semiconductor，VDMOS)晶体管做为区域内的半导体元件，可有效增进半导体元件的热散逸，进而提升半导体元件的稳定度和延长集成电路结构的使用寿命。
以下参照所附附图详细叙述本发明的其中多个实施态样，以描述集成电路结构和形成于基板不同区域内的半导体元件的相关构型。相关的结构细节例如相关层别和空间配置等内容如下面实施例内容所述。然而，但本发明并非仅限于所述态样，本发明并非显示出所有可能的实施例。实施例中相同或类似的标号用以标示相同或类似的部分。再者，未于本发明提出的其他实施态样也可能可以应用。相关领域者可在不脱离本发明的精神和范围内对实施例的结构加以变化与修饰，以符合实际应用所需。而附图已简化以利清楚说明实施例的内容，附图上的尺寸比例并非按照实际产品等比例绘制。因此，说明书和图示内容仅作叙述实施例之用，而非作为限缩本发明保护范围之用。
再者，说明书与权利要求中所使用的序数例如”第一”、”第二”、”第三”等的用词，以修饰请求项的元件，其本身并不意含及代表该请求元件有任何之前的序数，也不代表某一请求元件与另一请求元件的顺序、或是制造方法上的顺序，该些序数的使用仅用来使具有某命名的一请求元件得以和另一具有相同命名的请求元件能作出清楚区分。
图1A为本发明一实施例的集成电路结构的一基板的上视图。图1B为沿着图1A的剖面线1B-1B所绘制的基板的剖面示意图。在一实施例中，一集成电路(IC)结构的基板10具有多个区域，以及数个半导体元件(例如金属氧化物半导体元件或类似物)分别形成于基板10的不同区域内。如图1A所示，一超深沟槽隔离结构(an ultra-deep(UD)trench isolationstructure)12形成于基板10内且围绕各个区域的周围。如图1B所示，超深沟槽隔离结构12自基板10的顶表面10a延伸至底表面10b而穿过基板10。根据实施例，超深沟槽隔离结构12结构性地(和物理性地)隔离位于基板10不同区域的该些半导体元件。
由于实施例的超深沟槽隔离结构12穿过基板10，因此对于基板不同区域内的半导体元件提供了一个优异的隔离方式。根据实施例，超深沟槽隔离结构12的深度TUD实质上等于基板10的厚度TS。一实施例中，超深沟槽隔离结构12的深度TUD至少60μm或更深，例如是在60μm至65μm范围之间。再者，一实施例中，超深沟槽隔离结构12的宽度WUD至少1μm或更大，例如在2μm至3μm范围之间。
再者，如图1B所示，超深沟槽隔离结构12具有位置相对的一上表面(uppersurface)12a和一下表面(lower surface)12b，其中下表面12b暴露于基板10的底表面10b，上表面12b暴露于基板10的顶表面10a。再者，在一实施例中，超深沟槽隔离结构12的上表面12a实质上齐平于基板10的顶表面10a，下表面12b实质上齐平于基板10的底表面10b。另外，超深沟槽隔离结构12包括一绝缘材料，例如是含有氮化物、氧化物或包括两者的绝缘材料，如氮化硅或氧化硅等等。然而，本发明并不受限于上述提及的数值与材料。
在应用例的一集成电路结构中，基板10包括至少一高压区域(high-side region)AHS和一低压区域(low-side region)ALS，相邻的高压区域AHS和低压区域ALS以实施例的超深沟槽隔离结构12相隔开来。如图1A所示，高压区域AHS和低压区域ALS的周围被实施例的超深沟槽隔离结构12所包围。此实施例中，如图1A所示，以高压区域AHS、低压区域ALS、第一区域A1、第二区域A2和逻辑区域ALC为例说明基板10所包含区域的其中一种安排设置方式。然而，本发明的基板10区域的安排设置并不限制于如图1A所示的方式，具有半导体元件的基板10区域的范围大小、相对位置和可设置的区域数目等，可依照实际应用时的需求而决定或调整。
图2为本发明一实施例的基板与形成于基板区域内的半导体元件的剖面示意图。图2所绘示的基板例如是沿着图1A的剖面线2-2而绘制，以显示位于高压区域AHS、低压区域ALS、和逻辑区域ALC中的半导体元件的剖面示意图。其中这些区域包括金属氧化物半导体(MOS)晶体管(i.e.做为基板区域内的半导体元件)，具有源极区S和漏极区D位于栅极112两侧。高压区域AHS、低压区域ALS和逻辑区域ALC中的MOS晶体管结构可依实际应用所需做适当调整与修饰，并不限制于如图2所绘示的MOS晶体管结构。
如图2所示，高压区域AHS和低压区域ALS中各包括至少一互补式金属氧化物半(CMOS)(由一P型金属氧化物半(PMOS)晶体管和一N型金属氧化物半(NMOS)晶体管组合而成)晶体管，例如由一高压(HV)PMOS晶体管和一高压NMOS晶体管组合而成做实施例的示例说明。以一NMOS晶体管为例，如图2所示，一NMOS晶体管包括一N型基板(例如是注入有N++掺杂物的基板)102、N型外延层(EPI)104于N++基板102上、高压P型阱(HVPW)、一N型飘移区(N-drift region)位于高压P型阱内、N+源极区S和漏极区D、栅极(ex:N+多晶硅)112和栅极氧化物110位于N+多晶硅栅极112的下方，其中一水平通道(horizontal channel)114从邻近栅极112的源极区S/漏极区D边缘扩散。邻近于NMOS晶体管的一PMOS晶体管具有与NMOS相似的构型，除了PMOS晶体管包括了高压N型阱(HVNW)位于N型外延层104内、源极区S/漏极区D包括P型掺杂物、以及P型飘移区(P-drift region)。
如图1A所示，实施例的其中一种安排设置方式的基板10还包括第一区域A1和第二区域A2。第一区域A1邻近于高压区域AHS且与高压区域AHS电连接，第二区域A2邻近于低压区域ALS且与低压区域ALS电连接。于一实施例中，第一区域A1的周围被超深沟槽隔离结构12所包围，而使第一区域A1可因实施例的超深沟槽隔离结构12的设置而和高压区域AH相互隔离。类似地，第二区域A2的周围被超深沟槽隔离结构12所包围，而使第二区域A2可因实施例的超深沟槽隔离结构12的设置而和低压区域ALS相互隔离。由于实施例的超深沟槽隔离结构12的存在，基板10的该些区域(其中形成有半导体元件)在设置安排上可尽可能地彼此靠近而减少基板10所需的总面积；例如，两相邻区域之间的最小距离可以等于实施例的超深沟槽隔离结构12的宽度WUD。于一实施例中，超深沟槽隔离结构12的宽度WUD在2μm至3μm范围之间。虽然，图1A所绘示的多个相关区域安排是在区域之间设置实施例的超深沟槽隔离结构12以大幅缩小基板10所需的总面积，但应用本发明的实施例时并不仅限于如图1A所示的区域安排。值得注意的是，基板10的区域的安排设置不限于图1A的示例，区域的大小范围、彼此之间的相对位置以及设置区域的数目…等等实可依照应用时的条件所需而定或作相应调整。根据一实施例，至少一个垂直式侧向扩散型金属氧化物半导体(vertical double-diffused metal oxide semiconductor，VDMOS)晶体管形成于第一区域A1和第二区域A2至少其中之一做为区域内的半导体元件(亦即，在第一区域A1或第二区域A2，会包括一个VDMOS)。再者，此VDMOS晶体管可具有一平面式结构(planar structure)或是具有一沟槽式栅极结构(trench-gate structure)。
图3为本发明另一实施例的基板与形成于基板区域内的半导体元件的剖面示意图，其所绘示的基板沿着图1A的剖面线3-3所绘制，以显示位于高压区域AHS、第一区域A1、第二区域A2和低压区域ALS中的半导体元件的剖面示意图，其中以于第一区域A1和第二区域A2中分别包括至少一个具有平面式结构的VDMOS晶体管为例做为区域内半导体元件的其中一种构型示例的说明。如图3所示，在第一区域A1和第二区域A2中，一具平面式结构的VDMOS晶体管包括一N型基板(N++substrate，例如是注入有N++掺杂物)102并做为一漏极区、一N型外延层104于N++基板102(/漏极区)上、一P型体区(P-body region)106、N+源极区108形成于P型体区106内、栅极(ex:N+多晶硅)112和栅极氧化物110位于栅极112下方，其中一水平通道(horizontal channel)114从邻近栅极112的N+源极区108边缘扩散。
图4为本发明又一实施例的基板与形成于基板区域内的半导体元件的剖面示意图，其沿着图1A的剖面线3-3绘制以显示位于高压区域AHS、第一区域A1、第二区域A2和低压区域ALS中的半导体元件的剖面示意图，其中以于第一区域A1和第二区域A2中分别包括至少一个具有沟槽式栅极结构的VDMOS晶体管为例做为区域内半导体元件的其中一种构型示例的说明。如图4所示，一具沟槽式栅极结构的VDMOS晶体管(包括栅极和垂直通道)可包括N型基板(N++，做为一漏极区)102、N型外延层104于N++基板102(/漏极区)上、P型体区106、N+源极区108形成于P型体区106内、栅极氧化物110和栅极结构。栅极结构自基板10的顶表面10a向下延伸，且栅极结构包括位于一垂直沟槽(vertical trench)Tch的栅极113以及包围垂直沟槽Tch内的栅极113部分的一绝缘层115(i.e.例如是氧化物以做为栅极绝缘层)以控制电流传递。由于垂直沟槽Tch内的栅极113构型，如图4中所示的栅极113一般又被称为沟槽栅极(trench gate)，其中沟槽Tch的深度决定了栅极113的长度。沟槽Tch的深度大小例如是足以跨过在基板10的顶表面10a之下所形成的P型体区106。与水平通道不同，具沟槽式栅极结构的VDMOS晶体管存在有自邻近栅极113的源极区108边缘扩散的一垂直通道(verticalchannel)，且是垂直地导通电流。
根据实施例，位于基板10的第一区域A1和/或第二区域A2中的VDMOS晶体管，不论是平面式结构或是沟槽式栅极结构的VDMOS晶体管，其源极区和漏极区(例如108和102)分别位于基板10的顶表面10a和底表面10b处，因此可有效增进晶体管的热散逸。于一实施例中，可进一步设置(/贴附)一散热片(heat sink)于漏极区以直接移除VDMOS晶体管(/半导体元件)所产生的热。
另外，在一实施例中，逻辑区域ALC(与高压区域AHS和低压区域ALS相距)的周围被超深沟槽隔离结构12所包围，而使逻辑区域ALC可因实施例的超深沟槽隔离结构12的设置而和高压区域AH和低压区域ALS物理性地相隔开离仅超深沟槽隔离结构12的宽度WUD的距离，以缩小占据基板10的空间，进而减少应用的IC结构所需的总面积。再者，至少一低压(LV)MOS晶体管形成于逻辑区域ALC中，但本发明并不以图2所示的MOS晶体管结构为限。
注意的是，基板各区域(例如高压区域AHS、低压区域ALS、第一区域A1、第二区域A2和逻辑区域ALC等等)的半导体元件的构型，并不限制在如图2、图3、图4所示的MOS晶体管或VDMOS晶体管的形态。在其他实施例中，高压区域AHS和低压区域ALS中也可能包括其他半导体元件的构型。再者，基板的第一区域A1和第二区域A2的半导体元件例如是包括VDMOS晶体管，其形态可以是平面式结构或是沟槽式栅极结构或是其他结构的VDMOS晶体管，视实际应用的需求而定。因此，本发明并不限制在如图所绘示的结构型态。
有许多方式可以制得实施例的超深沟槽隔离结构12。例如，在一实际制造流程中，超深沟槽隔离结构12可以自基板10(晶片)的顶表面10a向下延伸到基板10内一个非常深的位置；形成IC结构所需的半导体元件后，以背面研磨(backside lapping)进行基板/晶片的薄化，以完成超深沟槽隔离结构12的下表面12b暴露于基板10的底表面的构型，并达到实际应用所要求的基板10厚度。请参照简绘5A-图5B，其为本发明一实施例的集成电路结构的制造方法示意图。如图5A所示，提供一晶片例如基板10’并于基板10’内形成超深沟槽隔离结构12，且超深沟槽隔离结构12围绕基板的预定区域(ex:高压区域AHS/低压区域ALS/第一区域A1/第二区域A2/逻辑区域ALC)的周围，此时超深沟槽隔离结构12尚未贯穿基板10’。图5A-图5B绘示高压区域AHS、低压区域ALS和第一区域A1为例做说明。之后，对基板10’进行晶背研磨，直到超深沟槽隔离结构12的下表面12b暴露出来为止，如图5B所示，下表面12b暴露于基板10的底表面10b，此时超深沟槽隔离结构12贯穿基板10。而于基板预定区域中不同区域内形成IC结构所需的半导体元件(未显示于图5B)则可于研磨步骤之前或之后进行(i.e.可在形成如图5A的超深沟槽隔离结构12之前，或形成如图5A的超深沟槽隔离结构12之后与图5B的研磨步骤之间，或于图5B的研磨步骤结束之后形成半导体元件)。因此对于一最终产品而言，实施例的超深沟槽隔离结构12是穿过基板10的，即从基板10的顶表面10a延伸至底表面10b(图5B，其下表面12b暴露于基板10的底表面10b)。再者，实施例的超深沟槽隔离结构12可以是在制作浅沟槽隔离环(STI loop)之前形成(即，在形成MOS/VDMOS之前先形成)，或是在制作浅沟槽隔离环之后形成(即，在形成MOS/VDMOS之后再形成)，本发明并不特别对此或其余制作流程细节进行限制。只要在不影响半导体元件特性的情况下，通过晶背研磨的方式可制得超深沟槽隔离结构12的方式皆可应用。
根据上述，实施例的IC结构具有许多优点，对于应用实施例设计的IC结构，超深沟槽隔离结构12穿过基板10(亦即，超深沟槽隔离结构12的深度TUD实质上等于基板10的厚度TS)，对于基板10不同区域内的半导体元件提供了一个优异的隔离方式。再者，应用具超深沟槽隔离结构的实施例设计可使相邻区域之间的间距大幅缩短(例如，超深沟槽隔离结构12的宽度WUD可以是2μm至3μm范围之间)，以节省基板10所需的面积，进而缩小置放半导体元件的集成电路结构的尺寸与降低制造成本。另外，当基板10的部分区域例如第一区域A1和/或第二区域A2内的半导体元件是应用垂直式侧向扩散型金属氧化物半导体(VDMOS)晶体管时(即晶体管的源极区和漏极区分别位于基板的顶表面和底表面处)，可有效增进半导体元件的热散逸，进而提升半导体元件的稳定度和延长集成电路结构的使用寿命。此外，实施例的超深沟槽隔离结构12的制法与现有制作工艺相容，因此也十分适合量产。
其他实施例，例如半导体元件的已知构件有不同的设置与排列等，也可能可以应用，视应用时的实际需求与条件而可作适当的调整或变化。因此，说明书与附图中所示的结构仅作说明之用，并非用以限制本发明欲保护的范围。另外，相关技术者当知，实施例中构成部件的形状和位置也并不限于图示所绘的态样，也是根据实际应用时的需求和/或制造步骤在不悖离本发明的精神的情况下而可作相应调整。
综上所述，虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明。本发明所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作各种的更动与润饰。因此，本发明的保护范围应以附上的权利要求所界定的为准。

Claims (16)

1.一种集成电路结构，包括：
基板，具有相对的一顶表面(top surface)和一底表面(bottom surface)，且该基板具有多个区域；
多个半导体元件形成于该基板，且分别位于不同的该些区域内，和；
超深沟槽隔离结构(an ultra-deep(UD)trench isolation structure)，形成于该基板内且围绕各个该些区域的周围，以隔离位于该些区域中不同区域的该些半导体元件；
其中该超深沟槽隔离结构自该基板的该顶表面延伸至该底表面而穿过该基板。
2.如权利要求1所述的集成电路结构，其中该超深沟槽隔离结构的一深度实质上等于该基板的一厚度。
3.如权利要求1所述的集成电路结构，其中该超深沟槽隔离结构包括含有氮化物、氧化物或两者的一绝缘材料。
4.如权利要求1所述的集成电路结构，其中该些区域包括高压区域(high-sideregion)和低压区域(low-side region)以该超深沟槽隔离结构相隔开来，且该高压区域和该低压区域的周围被该超深沟槽隔离结构包围。
5.如权利要求4所述的集成电路结构，其中该些区域还包括第一区域(first region)邻近于该高压区域且与该高压区域电连接，且该第一区域的周围被该超深沟槽隔离结构包围。
6.如权利要求5所述的集成电路结构，其中该第一区域中形成有一高压垂直式侧向扩散型金属氧化物半导体(high voltage-vertical double-diffused metal oxidesemiconductor，HV-VDMOS)晶体管。
7.如权利要求4所述的集成电路结构，其中该些区域还包括第二区域(second region)邻近于该低压区域且与该低压区域电连接，且该第二区域的周围被该超深沟槽隔离结构包围。
8.如权利要求7所述的集成电路结构，其中该第二区域中形成有一低压垂直式侧向扩散型金属氧化物半导体晶体管。
9.如权利要求1所述的集成电路结构，其中该些区域还包括第一区域，邻近于该高压区域且与该高压区域电连接，和第二区域，邻近于该低压区域且与该低压区域电连接，其中该第一区域和该第二区域至少一者包括一垂直式侧向扩散型金属氧化物半导体晶体管，其一源极区(source region)和一漏极区(drain region)分别位于该基板的该顶表面和该底表面处。
10.如权利要求9所述的集成电路结构，其中该垂直式侧向扩散型金属氧化物半导体晶体管具有平面式结构(a planar structure)，且该垂直式侧向扩散型金属氧化物半导体晶体管包括一栅极氧化物位于该基板的该顶表面，一栅极位于该栅极氧化物上，以及从邻近该栅极的该源极区边缘扩散的一水平通道(horizontal channel)。
11.如权利要求9所述的集成电路结构，其中该垂直式侧向扩散型金属氧化物半导体晶体管具有沟槽式栅极结构(a trench-gate structure)，且该垂直式侧向扩散型金属氧化物半导体晶体管包括栅极结构自该基板的该顶表面向下延伸，且该栅极结构包括位于一垂直沟槽(vertical trench)的一栅极，和位于该垂直沟槽内且包围部分该栅极的一绝缘层，其中自邻近该栅极的该源极区边缘扩散而形成一垂直通道(vertical channel)。
12.如权利要求1所述的集成电路结构，其中该超深沟槽隔离结构的一深度至少60μm或更深。
13.如权利要求1所述的集成电路结构，其中该超深沟槽隔离结构的一宽度至少1μm或更大。
14.一种集成电路结构的制造方法，包括：
提供一基板，且该基板具有多个预定区域；
形成一超深沟槽隔离结构于该基板内且围绕该些预定区域的周围，其中该超深沟槽隔离结构自该基板的顶表面向下延伸；和
研磨该基板的背面，直到该超深沟槽隔离结构的下表面暴露于该基板的底表面，其中该基板的该底表面相对于该顶表面。
15.如权利要求14所述的制造方法，在研磨步骤之前，还包括：
形成多个半导体元件于该基板，且分别位于该些预定区域中不同区域内，
其中研磨该基板后该超深沟槽隔离结构自该基板的该顶表面延伸至该底表面而穿过该基板，且该超深沟槽隔离结构隔离位于该些预定区域中不同区域的该些半导体元件。
16.如权利要求14所述的制造方法，在研磨步骤之后，还包括：
形成多个半导体元件于该基板，且分别位于该些预定区域内，
其中研磨该基板后该超深沟槽隔离结构自该基板的该顶表面延伸至该底表面而穿过该基板，且该超深沟槽隔离结构隔离位于该些预定区域中不同区域的该些半导体元件。
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