CN1292470C - 在低介电常数材料层中形成开口的方法 - Google Patents
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Abstract
一种在低介电常数材料层中形成开口的方法。依序在具有金属线的基底上形成盖层、第一介电层、蚀刻阻挡层、第二介电层、CMP阻挡层、金属硬罩幕层、硬罩幕层、以及BARC层,在定义硬罩幕层以及金属硬罩幕层以形成一第一开口以后,在硬罩幕层上形成一种液态充填材料层并填满第一开口,用一层定义过的光阻层作为罩幕定义充填材料层以及低介电常数介电层,以得到一个第二开口,将光阻层随着充填材料一并移除以后,利用金属硬罩幕层以及硬罩幕层作为罩幕,盖层为蚀刻阻挡层,以形成一个镶嵌开口。
Description
技术领域
本发明是有关于一种制作半导体元件的方法,且特别是有关于一种在低介电常数材料层中形成开口的方法。
背景技术
在半导体的制作过程中,当芯片上的元件尺寸变小时,内连线间距的密度就会增加,因为广泛的使用到具有高介电常数的氧化硅介电层,就很容易造成高RC延迟,因此在高速IC中的内金属介电层(IMD),便用低介电常数(low-k)的介电材料来取代。使用低介电常数的介电材料的优点像是可以降低内连线的寄生电容,连带降低RC延迟,或是缓和金属线之间的干扰,因此可以改善操作的速度,所以低介电常数的介电材料是一种非常普遍的用于高速IC中的IMD材料。
低介电常数材料包括像是HSQ(氢化硅倍半氧化物)、FSG(掺氟的氧化硅)以及CORAL(掺碳的氧化硅)的无机材料,以及像是flare(聚芳香烯醚)、SILK(芳香族碳氢化合物)以及二甲苯塑料等有机材料。
在一种传统用来形成镶嵌开口的工艺是先形成介层洞,如图1所示,此方法会在预先提供的基底100之间的内连线(未显示)上形成一层盖氮化物层,之后依序在盖氮化物层上形成第一低介电常数介电层104、阻挡层106、第二低介电常数介电层108、化学机械研磨阻挡层110、以及底部抗反射涂布(BARC)层(未显示),然后在底部抗反射涂布层上形成一层定义过的第一光阻层用来定义介层洞;用第一光阻层当作罩幕,而盖氮化物层作为一层蚀刻阻挡层,进行第一道非等向性蚀刻工艺,穿过这些结构层而形成介层洞开口。
在移除第一光阻层以后,进行一道填满间隙的步骤,用聚合物材料层填满介层洞,借以保护盖氮化物层;在聚合物材料层上形成一层定义过的第二光阻层以后,进行第二到非等向性蚀刻工艺,以阻挡层作为蚀刻阻挡层,定义出一沟渠,图1即为用上述工艺制作的一种公知镶嵌开口结构。
但是,如图1所示,覆盖在介层洞开口的聚合物材料层会在开口120上端周围形成一个栅栏状的外观,这是因为聚合物材料层阻碍了蚀刻,结果会造成第二低介电常数介电层108的不完全移除。
此外,当第二光阻层接着被像是氮/氧的等离子抛磨工艺或是氮/氢的等离子工艺之类的光阻移除工艺剥除时,使用的光阻移除工艺通常会损害到第二介电层108的侧壁107,导致低介电常数材料层的介电常数有变动。再者,受损侧壁107的低介电常数介电材料会有吸收水气的倾向,会造成后续金属化工艺的品质退化。
发明内容
有鉴于此,本发明的目的之一在于提供一种在低介电常数材料层中形成开口的方法,用等离子剥除光阻的缺点可以被改善,且不会形成栅栏状的外观,因此更适合用于在低介电常数材料层中形成开口的工艺上,特别是在含有金属导线或内连线的低介电常数材料层上。
为达本发明的上述与其它目的,本发明提供一种在低介电常数材料层中形成开口的方法,依序在具有金属线的基底上形成盖层、第一介电层、蚀刻阻挡层、第二介电层、CMP阻挡层、金属硬罩幕层、硬罩幕层、以及BARC层,其中第一与第二介电层是低介电常数的介电层。之后,在BARC层形成一层定义过的第一光阻层,用来定义BARC层、硬罩幕层以及金属硬罩幕层,以形成一第一开口;接着将第一光阻层随着BARC层移除,而后形成一层新的BARC层作为一层BARC并填满第一开口,用形成在此BARC层上的一层定义过的第二光阻层作为罩幕,定义出一个第二开口,将第二光阻层随着BARC层移除,利用金属硬罩幕层以及硬罩幕层作为罩幕以形成一个镶嵌开口,之后移除盖层,便完成双重镶嵌的内连线结构。
通过沿着填满间隙的BARC材料层使用定义过的硬罩幕层以及定义过的金属硬罩幕层作为罩幕,可以保护低介电常数介电材料层,使其不被剥除光阻时使用的等离子损伤,当第二开口的侧壁可能在光阻剥除的过程中受到损害,也可以在接下来的非等向性蚀刻工艺中加以移除,因此可以避免品质退化。
另外,在制作介层洞开口期间不需要间隙填充过程,因此可以避免栅栏状的外观。
附图说明
图1为一种公知的镶嵌开口结构,是用公知一种先形成介层洞来制作镶嵌开口的方法制作形成;
图2A-图2I为依照本发明一较佳实施例的一种在低介电常数材料层中形成镶嵌开口的方法的工艺剖面图。
100,200:基底 201:金属导线
104,108,204,208:低介电常数介电层
202:盖层 106,206:阻挡层
107:开口侧壁 110,210:CMP阻挡层
120,222:开口
212,212a:金属硬罩幕层 214,214a:硬罩幕层
216,216a:BARC层 220,230:光阻层
224:BARC材料层 234:镶嵌开口
232,234b:介层洞开口 234a:沟渠开口
具体实施方式
图2A-图2I为依照本发明一较佳实施例的一种在低介电常数材料层中形成镶嵌开口的方法的工艺剖面图。
请参照图2A,提供一个有金属导线201形成于其中的半导体基底200,在基底200与金属导线201上形成一层盖层202,盖层比如为氮化物层,其厚度约为400-700埃,较适当的厚度为500埃。接着,依序在盖氮化层202上形成一层第一介电层204、一层蚀刻阻挡层206与一层第二介电层208,第一与第二介电层204,208为低介电常数介电层,比如是用含有硅的无机聚合物,像是CORALTM或是BlackDiamondTM等,第一与第二介电层204,208比如用CVD形成,其厚度约为2000-3000埃,介电层的厚度可以随着在基底200上形成的结构做调整;而蚀刻阻挡层206比如为氮化硅层或是碳化硅层,其厚度约为400-700埃,较适当的厚度为500埃。
接着,依序在第二介电层208上形成一层化学机械研磨(CMP)阻挡层210、一层金属硬罩幕层212、一层硬罩幕层214以及一层底部抗反射涂布(BARC)层216,其中化学机械研磨阻挡层210比如为氮化硅层或是碳化硅层,其厚度约为400-700埃,较佳为500埃;金属硬罩幕层212的材料包括钽、氮化坦、钨、氮化钨、氮化钛以及钛,比如用CVD或是溅镀法形成,金属硬罩幕层212的厚度约为100-300埃,较佳为200埃;硬罩幕层214比如为氮化硅层或是碳化硅层,其厚度约为1000-2000埃,较佳为1500埃;金属硬罩幕212与硬罩幕214的形成是本发明的优点之一。
之后,在BARC层216上形成一层定义过的第一光阻层220。
请参照图2B,把定义过的光阻层220作为罩幕,移除部份的BARC层216、硬罩幕层214以及金属硬罩幕层212,直到暴露出CMP阻挡层210为止,所以会在BARC层216a、硬罩幕层214a以及金属硬罩幕层212a之中形成开口222。
请参照图2C,用等离子作为清除剂,移除第一光阻层220,因为BARC层216的材质与光阻层220的材质相似,所以BARC层216a会随着第一光阻层220一并被除去,而因为介电层202,208会被CMP阻挡层保护住而不会暴露在等离子下,因此可以避免受到等离子的损害。
请参照图2D,比如利用旋涂法在定义过的硬罩幕层214a上形成一层BARC材料层224,并填满开口222,BARC材料层224的材料比如为液态的有机聚合物,与光阻材料相似但不具有感旋光性;此BARC材料层224可以作为BARC并填满开口,之后再于此BARC材料层224上形成一层第二光阻层230。
请参照图2E,用第二光阻层230作为罩幕,进行第一道非等向性蚀刻工艺,以移除BARC层224、CMP阻挡层210、第二介电层208以及蚀刻阻挡层206,以形成一个介层洞开口232,此介层洞开口232的深度可以随着工艺的需要做调整;也就是说非等向性蚀刻在碰到蚀刻阻挡层206之前、当时或之后停止均可,并不会暴露出盖层202与金属导线。
请参照图2F,进行等离子工艺以移除第二光阻层230,因为BARC材料层224的材质与光阻材料230的材质相近,所以BARC材料层224会随着第二光阻层230一并被移除。
请参照图2G,以硬罩幕层214a与金属硬罩幕层212a作为罩幕,进行第二道非等向性蚀刻工艺,以形成一个镶嵌开口234,此镶嵌开口234包括一个沟渠开口234a与一个介层洞开口234b,通过控制介层洞开口232的深度与蚀刻条件,沟渠开口234a会被蚀刻直到暴露出蚀刻阻挡层206为止,此时介层洞开口234b的形成则是用盖层202作为蚀刻阻挡层。
虽然在剥除光阻时,介层洞开口232的侧壁会暴露在等离子中而受到破坏,但是受到破坏的介层洞开口232侧壁会在第二道非等向性蚀刻步骤中被移除。
请参照图2H,移除盖层202以暴露出下层在基底200中的金属导线201,盖层202被移除的方法可以是干蚀刻或是湿蚀刻,假如硬罩幕214a层用的材质与盖层202相同,比如都是用氮化硅,那么硬罩幕层214a就会随着盖层202一并被移除。
之后,形成一层导电层(未显示)以填满镶嵌开口234,导电层的材料包括用溅镀或是CVD法形成的铝、铜或其它的金属。接着用CMP对导电层进行平坦化的步骤,以CMP阻挡层210作为研磨阻挡层,借以在开口234内形成内连线236,如图2I所示,其中金属硬罩幕层212a与CMP阻挡层210会在CMP过程中一并被移除。
接下来的工艺步骤为本领域技术人员熟知,所以将不在此赘述。
通过使用定义过的硬罩幕层以及定义过的金属硬罩幕层沿着填充间隙的BARC材料层用来作为罩幕,可以保护低介电常数介电层不会受到剥除光阻时使用等离子造成的破坏,此外在介层洞的开口形成中不需要有填充间隙的步骤,因此可以避免有栅栏状的外观出现。
Claims (20)
1.一种在低介电常数材料层中形成开口的方法,其特征是,该方法包括下列步骤:
提供一基底,含有一金属导线;
依序在具有该基底上形成一盖层、一第一介电层、一第一阻挡层、一第二介电层、一第二阻挡层、一金属硬罩幕层、一硬罩幕层、以及一抗反射层,其中该第一与该第二介电层为低介电常数的介电层;
形成一定义过的第一光阻层于该抗反射层上,以定义该抗反射层、该硬罩幕层以及该金属硬罩幕层,因而形成一第一开口以暴露出该第二阻挡层;
移除该第一光阻层与该抗反射层;
形成一充填材料层于该硬罩幕层上并填满该第一开口;
形成一定义过的第二光阻层于该充填材料层上,用以定义该充填材料层、该第二阻挡层、该第二介电层以及该第一阻挡层,因而形成一第二开口而暴露出该第一介电层;
移除该第二光阻层与该充填材料层;
以该金属硬罩幕层以及该硬罩幕层作为一罩幕,进行一非等向性蚀刻步骤,以形成一个镶嵌开口,其中该镶嵌开口会暴露出该盖层;以及
移除暴露的该盖层,以暴露出下层的该金属导线。
2.如权利要求1所述的方法,其特征是,该镶嵌开口包括一沟渠开口以及一介层洞开口,而该第一阻挡层与该盖层分别用来作为形成该沟渠开口与该介层洞开口的蚀刻阻挡层。
3.如权利要求1所述的方法,其特征是,形成该第一与该第二介电层的材料包括含有硅的无机聚合物。
4.如权利要求1所述的方法,其特征是,该抗反射层为一底部抗反射涂布层。
5.如权利要求1所述的方法,其特征是,该充填材料层为用液态的有机聚合物组成的一底部抗反射涂布层。
6.如权利要求1所述的方法,其特征是,该金属硬罩幕层所用的材料选自钽、氮化钽、钛、氮化钛、钨以及氮化钨其中之一。
7.如权利要求1所述的方法,其特征是,该第一阻挡层可以是一氮化硅层或是一碳化硅层。
8.如权利要求1所述的方法,其特征是,该第二阻挡层可以是一氮化硅层或是一碳化硅层。
9.如权利要求1所述的方法,其特征是,该硬罩幕层可以是一氮化硅层或是一碳化硅层。
10.如权利要求1所述的方法,其特征是,进一步包括在移除暴露的该盖层以后,于该镶嵌开口中形成一双重镶嵌内连线结构。
11.如权利要求10所述的方法,其特征是,于该镶嵌开口中形成该双重镶嵌内连线结构的步骤包括:
形成一导电层填入该镶嵌开口;以及
以该第二阻挡层作为一研磨阻挡层,利用化学机械研磨平坦化该导电层以在该镶嵌开口中形成该双重镶嵌内连线结构。
12.一种在低介电常数材料层中形成开口的方法,其特征是,该方法包括下列步骤:
提供一基底,至少包括一金属导线,其中有一盖层与一低介电常数介电层依序形成于该基底上;
形成一金属硬罩幕层与一硬罩幕层于该低介电常数介电层上;
定义该硬罩幕层以及该金属硬罩幕层,以形成一第一开口;
形成一充填材料层于该定义过的硬罩幕层上并填满该第一开口;
形成一定义过的光阻层于该充填材料层上;
用该定义过的光阻层作为一罩幕,以蚀刻该充填材料层与该低介电常数介电层,其中该低介电常数介电层会被蚀刻到不会暴露出该盖层的一预定深度;
移除该光阻层与该充填材料层;
以定义过的该金属硬罩幕层以及该硬罩幕层作为一罩幕,而该盖层用以作为一蚀刻阻挡层,来蚀刻该低介电常数介电层以形成一个镶嵌开口;
移除暴露于该镶嵌开口中的该盖层;
形成一导电层填满该镶嵌开口;以及
利用化学机械研磨平坦化该导电层以在该镶嵌开口中形成该双重镶嵌内连线结构。
13.如权利要求12所述的方法,其特征是,在该低介电常数介电层中进一步包括一阻挡层,且其中该阻挡层可以在该低介电常数介电层被蚀刻到不会暴露出该盖层的一预定深度时用来作为一蚀刻阻挡层。
14.如权利要求12所述的方法,其特征是,在该低介电常数介电层与该金属硬罩幕层之间进一步包括一硬层,此硬层可以在该金属硬罩幕层以及该硬罩幕层被定义的时候用来作为一蚀刻阻挡层。
15.如权利要求12所述的方法,其特征是,该镶嵌开口包括一沟渠开口以及一介层洞开口,而该第一阻挡层与该盖层分别用来作为形成该沟渠开口与该介层洞开口的蚀刻阻挡层。
16.如权利要求12所述的方法,其特征是,该充填材料层为用液态的有机聚合物组成的一底部抗反射涂布层。
17.如权利要求12所述的方法,其特征是,该金属硬罩幕层所用的材料选自钽、氮化钽、钛、氮化钛、钨以及氮化钨其中之一。
18.如权利要求12所述的方法,其特征是,该硬罩幕层可以是一氮化硅层或是一碳化硅层。
19.如权利要求13所述的方法,其特征是,该阻挡层可以是一氮化硅层或是一碳化硅层。
20.如权利要求14所述的方法,其特征是,该硬罩幕层可以是一氮化硅层或是一碳化硅层。
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2002
- 2002-01-10 US US10/044,322 patent/US6638871B2/en not_active Expired - Lifetime
- 2002-07-11 CN CNB021410232A patent/CN1292470C/zh not_active Expired - Lifetime
- 2002-11-13 US US10/291,911 patent/US6972259B2/en not_active Expired - Lifetime
-
2004
- 2004-12-23 US US11/021,411 patent/US20050110152A1/en not_active Abandoned
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CN103296078A (zh) * | 2012-02-23 | 2013-09-11 | 宜普电源转换公司 | 具有栅极隔离物的增强型GaN高电子迁移率晶体管器件及其制备方法 |
CN103296078B (zh) * | 2012-02-23 | 2017-01-18 | 宜普电源转换公司 | 具有栅极隔离物的增强型GaN高电子迁移率晶体管器件及其制备方法 |
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CN1433062A (zh) | 2003-07-30 |
US20030129844A1 (en) | 2003-07-10 |
US20030129842A1 (en) | 2003-07-10 |
US20050110152A1 (en) | 2005-05-26 |
US6972259B2 (en) | 2005-12-06 |
US6638871B2 (en) | 2003-10-28 |
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