US20050110152A1 - Method for forming openings in low dielectric constant material layer - Google Patents

Method for forming openings in low dielectric constant material layer Download PDF

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Publication number
US20050110152A1
US20050110152A1 US11/021,411 US2141104A US2005110152A1 US 20050110152 A1 US20050110152 A1 US 20050110152A1 US 2141104 A US2141104 A US 2141104A US 2005110152 A1 US2005110152 A1 US 2005110152A1
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layer
dielectric
nitride
opening
dielectric layer
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US11/021,411
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Chih-Jung Wang
Tong-Yu Chen
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United Microelectronics Corp
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United Microelectronics Corp
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Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, TONG-YU, WANG, CHIH-JUNG
Publication of US20050110152A1 publication Critical patent/US20050110152A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Definitions

  • the present invention relates to a method for manufacturing semiconductor devices. More particularly, the present invention relates to a method for forming openings in dielectric material layers.
  • low dielectric constant (low-k) dielectric material is used instead as an inter-metal dielectric (IMD) in high speed ICs.
  • IMD inter-metal dielectric
  • the low k dielectric materials include inorganic materials, such as HSQ, FSG and CORAL, and organic materials, such as flare, SILK and parylene.
  • a cap nitride layer 102 is formed over metal interconnects (not shown) within a provided substrate 100 .
  • a first low-k dielectric layer 104 , a stop layer 106 , a second low-k dielectric layer 108 , a chemical mechanical polishing (CMP) stop layer 110 and a bottom anti-reflection coating (BARC) layer are formed in sequence on the cap nitride layer.
  • CMP chemical mechanical polishing
  • BARC bottom anti-reflection coating
  • a patterned first photoresist layer is formed on the BARC layer for defining vias.
  • FIG. 1 shows a prior-art damascene opening structure manufactured by the cited above process.
  • the polymer material layer covering the via opening provokes a fence profile 110 around top of the opening 120 , as shown in FIG. 1 . It is because the polymer material layer hinders the etching, resulting in incomplete removal of the second low-k dielectric layer 108 .
  • the performed photoresist removal process usually damages the side walls 107 of the second dielectric layer 108 , leading to dielectric constant shift of the low-k dielectric layer.
  • the low-k dielectric material of the damaged sidewalls 107 tends to absorb moisture, resulting in degradation in the follow-up metallization process.
  • the disadvantage of photoresist striping by plasma is improved, and no fence profile is provoked. Therefore, it is more advantageous for the fabrication for forming openings in low-k material layers, especially the low-k material layers containing metal wires or interconnects.
  • the invention is directed towards a method for forming openings in a dielectric layer and a structure with an opening in the dielectric layer.
  • a dielectric layer is formed over the provided substrate, and the dielectric layer can be a single layer or comprises stack dielectric layers of different dielectric materials.
  • the dielectric layer is a low-k dielectric layer.
  • a mask layer comprising at least a metal hard mask layer and a hard mask layer and a first anti-reflection layer are formed on the dielectric layer.
  • a stop layer can be further included in the mask layer. The usage of the metal hard mask layer and the hard mask layer is one of the advantageous features of the present invention.
  • a second anti-reflection layer is formed. Using a patterned second photoresist layer formed on the second anti-reflection layer as a mask, a via opening is defined. After removing the second photoresist layer along with the second anti-reflection layer, a damascene opening is formed by using the mask layer as a mask.
  • the resultant structure with a damascene opening at least comprising: the substrate, the dielectric layer with the damascene opening and the patterned mask layer that includes at least one metal hard mask layer and one or more hard mask layers on the dielectric layer.
  • the structure for forming the opening further includes an anti-reflection layer on the mask layer.
  • the dielectric layer is protected from plasma damage.
  • FIG. 1 shows a prior art damascene opening structure manufactured by the conventional via-first process for forming damascene openings
  • FIGS. 2A-2I are cross-sectional views of the process steps for forming a damascene opening in low-k material layers according to one preferred embodiment of this invention.
  • FIGS. 3A-3H are cross-sectional views of the process steps for forming an opening in a dielectric layer according to another preferred embodiment of this invention.
  • FIGS. 2A-2I are cross-sectional views of the process steps for forming a damascene opening in low-k material layers according to one preferred embodiment of this invention.
  • a semiconductor substrate 200 having metal wires 201 formed thereon is provided.
  • a cap layer 202 is formed over the substrate 200 and the metal wires 201 .
  • the cap layer is, for example, a nitride layer with a thickness of about 400-700 ⁇ , preferably 500 ⁇ .
  • a first dielectric layer 204 , an etch stop layer 206 and a second dielectric layer 208 are formed in sequence on the cap nitride layer 202 .
  • the first and second dielectric layers 202 , 208 are low-k dielectric layers made of, for example, an inorganic polymer containing silicon, such as CORALTM or Black DiamondTM.
  • the first and second dielectric layers 202 , 208 are formed by, for example, CVD with a thickness of about 2000 ⁇ to 3000 ⁇ .
  • the thickness of the dielectric layers is adjustable, depending on the structure formed on the substrate 200 .
  • the etch stop layer 206 is, for example, a silicon nitride layer or a silicon carbide layer with a thickness of about 400-700 ⁇ , preferably 500 ⁇ . Alternatively, the etch stop layer can be omitted.
  • a chemical mechanical polishing (CMP) stop layer 210 is, for example, a silicon nitride layer or a silicon carbide layer with a thickness of about 400-700 ⁇ , preferably 500 ⁇ .
  • Materials for forming the metal hard mask layer 212 includes tantalum, tantalum nitride, tungsten, tungsten nitride, titanium nitride and titanium, formed by, for example, CVD or sputtering.
  • the metal hard mask layer 212 has a thickness of about 100-300 ⁇ , preferably 200 ⁇ .
  • the hard mask layer 214 is, for example, a silicon nitride layer or a silicon carbide layer with a thickness of about 1000-2000 ⁇ , preferably 1500 ⁇ .
  • the formation of the metal hard mask layer and the hard mask layer is one of the advantageous features of the present invention.
  • a patterned first photoresist layer 220 is formed on the BARC layer 216 .
  • the BARC layer 216 , the hard mask layer 214 and the metal hard mask layer 212 are partially removed until the CMP stop layer 210 is exposed.
  • An opening 222 is thus formed within the BARC layer 216 a, the patterned hard mask layer 214 a and the metal hard mask layer 212 a.
  • the first photoresist layer 220 is removed. Because the material of the BARC layer 216 is similar to the material of the photoresist layer 220 , the BARC layer 216 a is removed along with the first photoresist layer 220 . Because the dielectric layers 202 , 208 are protected by the CMP stop layer and not exposed to plasma, damage is thus avoided.
  • a BARC material layer 224 is formed by, for example, spin-on, on the patterned hard mask layer 214 a and fill the opening 222 .
  • the material for the BARC material layer 224 can be, for example, fluid organic polymer, similar to the photoresist materials but without photosensitivity.
  • the BARC material layer can act as an anti-reflection layer and fill the opening.
  • a patterned second photoresist layer 230 is formed on the BARC material layer 224 .
  • a first anisotropic etching process is performed to remove the BARC material layer 224 , the CMP stop layer 210 , the second dielectric layer 208 and the etch stop layer 206 , forming a via opening 232 .
  • the depth of the via opening 232 is adjustable, depending on the process needs. That is, the anisotropic etching can stop before, right at or after the etch stop layer 206 , but without exposing the cap layer 202 and the metal wires.
  • a plasma process is performed to remove the second photoresist layer 230 . Because the material of the BARC material layer 224 is similar to the material of the photoresist layer 230 , the BARC material layer 224 is removed along with the second photoresist layer 230 .
  • a second anisotropic etching process is performed to form a damascene opening 234 .
  • the damascene opening 234 includes a trench opening 234 a and a via opening 234 b.
  • the trench opening 234 a is etched until the etch stop layer 206 is exposed, while the via opening 234 b is formed by using the cap layer 202 as an etch stop layer.
  • the damaged sidewalls of the via opening 232 is removed during the second anisotropic etching process.
  • the cap layer 202 is removed to expose the underlying metal wires 201 within the substrate 200 .
  • the cap layer 202 can be removed either by wet etching or dry etching. If the hard mask layer 214 a is made of the same material as the cap layer 202 , for example, silicon nitride, the hard mask layer 214 a is removed along with the cap layer 202 .
  • a conductive layer (not shown) is formed to fill the damascene opening 234 .
  • the material for forming the conductive layer includes aluminum, copper or other metals formed by sputtering or CVD.
  • the conductive layer is then planarized by CMP using the CMP stop layer 210 as a polishing stop layer, so that a damascene interconnect 236 is formed within the opening 234 , as shown in FIG. 2I .
  • the metal hard mask layer 212 a and the CMP stop layer 210 are removed during the CMP process.
  • the patterned hard mask layer and the patterned metal hard mask layer are protected from plasma damage for stripping the photoresist. Moreover, no gap filling process is required for the via opening, thus avoiding the fence profile.
  • FIGS. 3A-3H are cross-sectional views of the process steps for forming an opening in a dielectric layer according to another preferred embodiment of this invention.
  • a semiconductor substrate 300 is provided. If a metal wire 301 is included in the substrate 300 , a cap layer 302 is then formed on the substrate 300 and covering the metal wire 301 .
  • the cap layer is, for example, a nitride layer with a thickness of about 400-700 ⁇ , preferably 500 ⁇ .
  • a dielectric layer 304 is formed over the substrate 300 .
  • the dielectric layer 304 can be a single layer or comprises stack layers including a first dielectric layer and a second dielectric layer.
  • a stop layer (not shown) can be included between the first and the second dielectric layers.
  • the dielectric layer 304 is a low-k dielectric layer made of, for example, an inorganic polymer containing silicon, such as CORALTM or Black DiamondTM.
  • the dielectric layer 304 is formed by, for example, CVD with a thickness of about 2000 ⁇ to 3000 ⁇ .
  • the first and second dielectric layers can be made of different dielectric materials, for example.
  • the thickness of the dielectric layer is adjustable, depending on the structure formed on the substrate 300 .
  • a mask layer 306 is formed on the dielectric layer 304 .
  • the mask layer comprises at least a metal hard mask layer 310 and a hard mask layer 312 .
  • a chemical mechanical polishing (CMP) stop layer 308 is further included in the mask layer 304 .
  • An anti-reflection coating (ARC) layer 314 is formed on the mask layer 306 .
  • the CMP stop layer 308 is, for example, a silicon nitride layer or a silicon carbide layer with a thickness of about 400-700 ⁇ , preferably 500 ⁇ .
  • Materials for forming the metal hard mask layer 310 includes tantalum, tantalum nitride, tungsten, tungsten nitride, titanium nitride and titanium, formed by, for example, CVD or sputtering.
  • the metal hard mask layer 310 has a thickness of about 100-300 ⁇ , preferably 200 ⁇ .
  • the hard mask layer 312 is, for example, a silicon nitride layer or a silicon carbide layer with a thickness of about 1000-2000 ⁇ , preferably 1500 ⁇ .
  • the formation of the metal hard mask layer and the hard mask layer is one of the advantageous features of the present invention.
  • a patterned first photoresist layer 320 is formed on the ARC layer 314 .
  • the ARC layer 314 , the hard mask layer 312 and the metal hard mask layer 310 are partially removed until the CMP stop layer 308 is exposed. Therefore, the patterned mask layer 306 a (including the patterned hard mask layer 312 a and the metal hard mask layer 310 a ) is obtained with an opening 322 formed within.
  • the first photoresist layer 320 is removed. Because the material of the ARC layer 314 is similar to the material of the photoresist layer 320 , the ARC layer 314 a is removed along with the first photoresist layer 320 .
  • an ARC material layer 324 is formed by, for example, spin-on, on the patterned mask layer 306 a and fills the opening 322 .
  • the material for the ARC material layer 324 can be, for example, fluid organic polymer, similar to the photoresist materials but without photosensitivity.
  • the ARC material layer can act as an anti-reflection layer and fill the opening.
  • a patterned second photoresist layer 330 is formed on the ARC material layer 324 .
  • a first anisotropic etching process is performed to partially remove the ARC material layer 324 , the CMP stop layer 308 and the dielectric layer 304 , forming a via opening 332 .
  • the depth of the via opening 332 is adjustable, depending on the process needs. That is, the anisotropic etching can stop in a first predetermined depth, but without exposing the cap layer 202 and the metal wires.
  • a plasma process is performed to remove the second photoresist layer 330 . Because the material of the ARC material layer 324 is similar to the material of the photoresist layer 330 , the ARC material layer 324 is removed along with the second photoresist layer 330 .
  • a second anisotropic etching process is performed to form a damascene opening 334 .
  • the damascene opening 334 includes a trench opening 334 a and a via opening 334 b.
  • the trench opening 334 a is also etched to a second predetermined depth, while the via opening 334 b is formed by using the cap layer 302 as an etch stop layer.
  • the resultant structure with the damascene opening at least comprising: the substrate, the dielectric layer with the damascene opening and the patterned mask layer that includes at least one metal hard mask layer and one or more hard mask layers on the dielectric layer.
  • the structure for forming the opening further includes an anti-reflection layer on the mask layer.
  • the cap layer 302 is removed to expose the underlying metal wires 301 within the substrate 300 .
  • the cap layer 302 can be removed either by wet etching or dry etching. If the hard mask layer 312 is made of the same material as the cap layer 302 , for example, silicon nitride, the hard mask layer 312 a can be removed along with the cap layer 302 . Afterwards, an interconnect (not shown) can be formed within the opening 334 , as shown in FIG. 21 .
  • the following processes are well known to persons skilled in the art, and will not be further described therein.
  • opening described herein is not limited to a damascene opening.
  • Other types of openings including via openings, trench openings and contact openings are within the scope of the present invention.
  • the dielectric layer is protected from plasma damage.

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Abstract

The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a continuation-in-part of prior applications Ser. No. 10/044,322, filed Jan. 10, 2002.
    • BACKGROUND OF THE INVENTION
  • 1. Field of Invention
  • The present invention relates to a method for manufacturing semiconductor devices. More particularly, the present invention relates to a method for forming openings in dielectric material layers.
  • 2. Description of Related Art
  • In the semiconductor fabrication process, as the dimension of devices on a chip becomes smaller, the density of interconnect pitch becomes higher. Because widely used silicon oxide dielectric layers have high dielectric constants, it can easily result in high RC delay. Therefore, low dielectric constant (low-k) dielectric material is used instead as an inter-metal dielectric (IMD) in high speed ICs. To apply low k dielectric has the advantage such as reducing the interconnection parasitic capacitance, consequently reducing the RC delay, or mitigating the cross talk between metal lines, hence, the operation speed is improved. Hence, the low k dielectric material is a very popular IMD material used in high speed ICs.
  • The low k dielectric materials include inorganic materials, such as HSQ, FSG and CORAL, and organic materials, such as flare, SILK and parylene.
  • In the conventional via-first process for forming damascene opening, as shown in FIG. 1, a cap nitride layer 102 is formed over metal interconnects (not shown) within a provided substrate 100. Afterwards, a first low-k dielectric layer 104, a stop layer 106, a second low-k dielectric layer 108, a chemical mechanical polishing (CMP) stop layer 110 and a bottom anti-reflection coating (BARC) layer (not shown) are formed in sequence on the cap nitride layer. Then, a patterned first photoresist layer is formed on the BARC layer for defining vias. By using the first photoresist layer as a mask and the cap nitride layer is used as an etching stop layer, a first anisotropic etching process is performed through the layers to form a via opening.
  • After removing the first photoresist layer, a gap filling process is performed to fill the via with a polymer material layer to protect the cap nitride layer. After a patterned second photoresist layer is formed on the polymer material layer, a second anisotropic etching process is performed to define a trench, by using the stop layer as an etching stop layer. FIG. 1 shows a prior-art damascene opening structure manufactured by the cited above process.
  • However, the polymer material layer covering the via opening provokes a fence profile 110 around top of the opening 120, as shown in FIG. 1. It is because the polymer material layer hinders the etching, resulting in incomplete removal of the second low-k dielectric layer 108.
  • Furthermore, while the second photoresist layer is subsequently stripped by a photoresist removal process, such as a nitrogen/oxygen plasma ashing process or a nitrogen/hydrogen plasma process, the performed photoresist removal process usually damages the side walls 107 of the second dielectric layer 108, leading to dielectric constant shift of the low-k dielectric layer. Moreover, the low-k dielectric material of the damaged sidewalls 107 tends to absorb moisture, resulting in degradation in the follow-up metallization process.
    • SUMMARY OF THE INVENTION
  • It is therefore an object of the invention to provide a method for forming openings in the dielectric material layer. The disadvantage of photoresist striping by plasma is improved, and no fence profile is provoked. Therefore, it is more advantageous for the fabrication for forming openings in low-k material layers, especially the low-k material layers containing metal wires or interconnects.
  • To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method for forming openings in a dielectric layer and a structure with an opening in the dielectric layer. A dielectric layer is formed over the provided substrate, and the dielectric layer can be a single layer or comprises stack dielectric layers of different dielectric materials. Preferably, the dielectric layer is a low-k dielectric layer. A mask layer comprising at least a metal hard mask layer and a hard mask layer and a first anti-reflection layer are formed on the dielectric layer. A stop layer can be further included in the mask layer. The usage of the metal hard mask layer and the hard mask layer is one of the advantageous features of the present invention. After patterning the mask layer, a second anti-reflection layer is formed. Using a patterned second photoresist layer formed on the second anti-reflection layer as a mask, a via opening is defined. After removing the second photoresist layer along with the second anti-reflection layer, a damascene opening is formed by using the mask layer as a mask.
  • The resultant structure with a damascene opening at least comprising: the substrate, the dielectric layer with the damascene opening and the patterned mask layer that includes at least one metal hard mask layer and one or more hard mask layers on the dielectric layer. Before the mask layer is patterned, the structure for forming the opening further includes an anti-reflection layer on the mask layer.
  • By using the patterned mask layer comprising at least a metal hard mask layer as a mask along with the gap-filling anti-reflection layer, the dielectric layer is protected from plasma damage.
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
  • FIG. 1 shows a prior art damascene opening structure manufactured by the conventional via-first process for forming damascene openings;
  • FIGS. 2A-2I are cross-sectional views of the process steps for forming a damascene opening in low-k material layers according to one preferred embodiment of this invention; and
  • FIGS. 3A-3H are cross-sectional views of the process steps for forming an opening in a dielectric layer according to another preferred embodiment of this invention.
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIGS. 2A-2I are cross-sectional views of the process steps for forming a damascene opening in low-k material layers according to one preferred embodiment of this invention.
  • Referring to FIG. 2A, a semiconductor substrate 200 having metal wires 201 formed thereon is provided. A cap layer 202 is formed over the substrate 200 and the metal wires 201. The cap layer is, for example, a nitride layer with a thickness of about 400-700 Å, preferably 500 Å. Afterwards, a first dielectric layer 204, an etch stop layer 206 and a second dielectric layer 208 are formed in sequence on the cap nitride layer 202. The first and second dielectric layers 202, 208 are low-k dielectric layers made of, for example, an inorganic polymer containing silicon, such as CORAL™ or Black Diamond™. The first and second dielectric layers 202, 208 are formed by, for example, CVD with a thickness of about 2000 Å to 3000 Å. The thickness of the dielectric layers is adjustable, depending on the structure formed on the substrate 200. The etch stop layer 206 is, for example, a silicon nitride layer or a silicon carbide layer with a thickness of about 400-700 Å, preferably 500 Å. Alternatively, the etch stop layer can be omitted.
  • Afterwards, a chemical mechanical polishing (CMP) stop layer 210, a metal hard mask layer 212, a hard mask layer 214 and a bottom anti-reflection coating (BARC) layer 216 are formed in sequence on the second dielectric layer 208. The CMP stop layer 210 is, for example, a silicon nitride layer or a silicon carbide layer with a thickness of about 400-700 Å, preferably 500 Å. Materials for forming the metal hard mask layer 212 includes tantalum, tantalum nitride, tungsten, tungsten nitride, titanium nitride and titanium, formed by, for example, CVD or sputtering. The metal hard mask layer 212 has a thickness of about 100-300 Å, preferably 200 Å. The hard mask layer 214 is, for example, a silicon nitride layer or a silicon carbide layer with a thickness of about 1000-2000 Å, preferably 1500 Å. The formation of the metal hard mask layer and the hard mask layer is one of the advantageous features of the present invention.
  • Afterwards, a patterned first photoresist layer 220 is formed on the BARC layer 216.
  • Referring to FIG. 2B, using the patterned photoresist layer 220 as a mask, the BARC layer 216, the hard mask layer 214 and the metal hard mask layer 212 are partially removed until the CMP stop layer 210 is exposed. An opening 222 is thus formed within the BARC layer 216 a, the patterned hard mask layer 214 a and the metal hard mask layer 212 a.
  • Referring to FIG. 2C, using plasma as a clean agent, the first photoresist layer 220 is removed. Because the material of the BARC layer 216 is similar to the material of the photoresist layer 220, the BARC layer 216 a is removed along with the first photoresist layer 220. Because the dielectric layers 202, 208 are protected by the CMP stop layer and not exposed to plasma, damage is thus avoided.
  • Referring to FIG. 2D, a BARC material layer 224 is formed by, for example, spin-on, on the patterned hard mask layer 214a and fill the opening 222. The material for the BARC material layer 224 can be, for example, fluid organic polymer, similar to the photoresist materials but without photosensitivity. The BARC material layer can act as an anti-reflection layer and fill the opening. Afterwards, a patterned second photoresist layer 230 is formed on the BARC material layer 224.
  • Referring to FIG. 2E, using the second photoresist layer 230 as a mask, a first anisotropic etching process is performed to remove the BARC material layer 224, the CMP stop layer 210, the second dielectric layer 208 and the etch stop layer 206, forming a via opening 232. The depth of the via opening 232 is adjustable, depending on the process needs. That is, the anisotropic etching can stop before, right at or after the etch stop layer 206, but without exposing the cap layer 202 and the metal wires.
  • Referring to FIG. 2F, a plasma process is performed to remove the second photoresist layer 230. Because the material of the BARC material layer 224 is similar to the material of the photoresist layer 230, the BARC material layer 224 is removed along with the second photoresist layer 230.
  • Referring to FIG. 2G, using the hard mask layer 214 a and the metal hard mask layer 212 a as a mask, a second anisotropic etching process is performed to form a damascene opening 234. The damascene opening 234 includes a trench opening 234 a and a via opening 234 b. By controlling the depth of the via opening 232 and the etching conditions, the trench opening 234 a is etched until the etch stop layer 206 is exposed, while the via opening 234 b is formed by using the cap layer 202 as an etch stop layer.
  • Although sidewalls of the via opening 232 is exposed to plasma damage for stripping the photoresist, the damaged sidewalls of the via opening 232 is removed during the second anisotropic etching process.
  • Referring to FIG. 2H, the cap layer 202 is removed to expose the underlying metal wires 201 within the substrate 200. The cap layer 202 can be removed either by wet etching or dry etching. If the hard mask layer 214 a is made of the same material as the cap layer 202, for example, silicon nitride, the hard mask layer 214 a is removed along with the cap layer 202.
  • Afterwards, a conductive layer (not shown) is formed to fill the damascene opening 234. The material for forming the conductive layer includes aluminum, copper or other metals formed by sputtering or CVD. The conductive layer is then planarized by CMP using the CMP stop layer 210 as a polishing stop layer, so that a damascene interconnect 236 is formed within the opening 234, as shown in FIG. 2I. The metal hard mask layer 212 a and the CMP stop layer 210 are removed during the CMP process.
  • The following processes are well known to persons skilled in the art, and will not be further described therein.
  • By using the patterned hard mask layer and the patterned metal hard mask layer as a mask along with the gap-filling BARC material layer, the low-k dielectric layers are protected from plasma damage for stripping the photoresist. Moreover, no gap filling process is required for the via opening, thus avoiding the fence profile.
  • FIGS. 3A-3H are cross-sectional views of the process steps for forming an opening in a dielectric layer according to another preferred embodiment of this invention.
  • Referring to FIG. 3A, a semiconductor substrate 300 is provided. If a metal wire 301 is included in the substrate 300, a cap layer 302 is then formed on the substrate 300 and covering the metal wire 301. The cap layer is, for example, a nitride layer with a thickness of about 400-700 Å, preferably 500 Å. Afterwards, a dielectric layer 304 is formed over the substrate 300. The dielectric layer 304 can be a single layer or comprises stack layers including a first dielectric layer and a second dielectric layer. Optionally, a stop layer (not shown) can be included between the first and the second dielectric layers. The dielectric layer 304 is a low-k dielectric layer made of, for example, an inorganic polymer containing silicon, such as CORAL™ or Black Diamond™. The dielectric layer 304 is formed by, for example, CVD with a thickness of about 2000 Å to 3000 Å. For the dielectric layer 304 comprising stack layers, the first and second dielectric layers can be made of different dielectric materials, for example. The thickness of the dielectric layer is adjustable, depending on the structure formed on the substrate 300. Afterwards, a mask layer 306 is formed on the dielectric layer 304. The mask layer comprises at least a metal hard mask layer 310 and a hard mask layer 312. If needed, a chemical mechanical polishing (CMP) stop layer 308 is further included in the mask layer 304. An anti-reflection coating (ARC) layer 314 is formed on the mask layer 306. The CMP stop layer 308 is, for example, a silicon nitride layer or a silicon carbide layer with a thickness of about 400-700 Å, preferably 500 Å. Materials for forming the metal hard mask layer 310 includes tantalum, tantalum nitride, tungsten, tungsten nitride, titanium nitride and titanium, formed by, for example, CVD or sputtering. The metal hard mask layer 310 has a thickness of about 100-300 Å, preferably 200 Å. The hard mask layer 312 is, for example, a silicon nitride layer or a silicon carbide layer with a thickness of about 1000-2000 Å, preferably 1500 Å. The formation of the metal hard mask layer and the hard mask layer is one of the advantageous features of the present invention.
  • Afterwards, a patterned first photoresist layer 320 is formed on the ARC layer 314.
  • Referring to FIG. 3B, using the patterned photoresist layer 320 as a mask, the ARC layer 314, the hard mask layer 312 and the metal hard mask layer 310 are partially removed until the CMP stop layer 308 is exposed. Therefore, the patterned mask layer 306 a (including the patterned hard mask layer 312 a and the metal hard mask layer 310 a) is obtained with an opening 322 formed within.
  • Referring to FIG. 3C, using plasma as a clean agent, the first photoresist layer 320 is removed. Because the material of the ARC layer 314 is similar to the material of the photoresist layer 320, the ARC layer 314 a is removed along with the first photoresist layer 320.
  • Referring to FIG. 3D, an ARC material layer 324 is formed by, for example, spin-on, on the patterned mask layer 306 a and fills the opening 322. The material for the ARC material layer 324 can be, for example, fluid organic polymer, similar to the photoresist materials but without photosensitivity. The ARC material layer can act as an anti-reflection layer and fill the opening. Afterwards, a patterned second photoresist layer 330 is formed on the ARC material layer 324.
  • Referring to FIG. 3E, using the second photoresist layer 330 as a mask, a first anisotropic etching process is performed to partially remove the ARC material layer 324, the CMP stop layer 308 and the dielectric layer 304, forming a via opening 332. The depth of the via opening 332 is adjustable, depending on the process needs. That is, the anisotropic etching can stop in a first predetermined depth, but without exposing the cap layer 202 and the metal wires.
  • Referring to FIG. 3F, a plasma process is performed to remove the second photoresist layer 330. Because the material of the ARC material layer 324 is similar to the material of the photoresist layer 330, the ARC material layer 324 is removed along with the second photoresist layer 330.
  • Referring to FIG. 3G, using the patterned mask layer 306 a (i.e. the hard mask layer 312 a and the metal hard mask layer 310 a) as a mask, a second anisotropic etching process is performed to form a damascene opening 334. The damascene opening 334 includes a trench opening 334 a and a via opening 334 b. By controlling the depth of the via opening 332 and the etching conditions, the trench opening 334 a is also etched to a second predetermined depth, while the via opening 334 b is formed by using the cap layer 302 as an etch stop layer.
  • The resultant structure with the damascene opening at least comprising: the substrate, the dielectric layer with the damascene opening and the patterned mask layer that includes at least one metal hard mask layer and one or more hard mask layers on the dielectric layer. Before the mask layer is patterned, the structure for forming the opening further includes an anti-reflection layer on the mask layer.
  • Referring to FIG. 3H, the cap layer 302 is removed to expose the underlying metal wires 301 within the substrate 300. The cap layer 302 can be removed either by wet etching or dry etching. If the hard mask layer 312 is made of the same material as the cap layer 302, for example, silicon nitride, the hard mask layer 312 a can be removed along with the cap layer 302. Afterwards, an interconnect (not shown) can be formed within the opening 334, as shown in FIG. 21. The following processes are well known to persons skilled in the art, and will not be further described therein.
  • However, the opening described herein is not limited to a damascene opening. Other types of openings, including via openings, trench openings and contact openings are within the scope of the present invention.
  • By using the patterned mask layer as a mask along with the gap-filling ARC material layer, the dielectric layer is protected from plasma damage.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (24)

1-27. (canceled)
28. A structure for forming an opening on a substrate, comprising:
a first dielectric layer on the substrate;
a second dielectric layer on the dielectric layer;
a plurality of mask layers at least comprising a metal mask layer on the second dielectric layer; and
an anti-reflection layer on the plurality of mask layers.
29. The structure as claimed in claim 28, wherein materials for forming the first and second dielectric layers include inorganic polymer containing silicon.
30. The structure as claimed in claim 28, wherein the anti-reflection layer is a bottom anti-reflection coating layer made of fluid organic polymer.
31. The structure as claimed in claim 28, wherein the metal mask layer is made of one of the following materials selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten and tungsten nitride.
32. The structure as claimed in claim 28, wherein the mask layer is a silicon nitride layer or a silicon carbide layer.
33. A structure for forming an opening on a substrate, comprising:
a first dielectric layer on the substrate;
a first stop layer on the first dielectric layer;
a second dielectric layer on the first stop layer;
a third dielectric layer on the second dielectric layer;
a plurality of mask layers at least comprising a metal mask layer on the third dielectric layer; and
an anti-reflection layer on the plurality of mask layers.
34. The structure as claimed in claim 33, wherein materials for forming the first and second dielectric layers include inorganic polymer containing silicon.
35. The structure as claimed in claim 33, wherein the anti-reflection layer is a bottom anti-reflection coating layer made of fluid organic polymer.
36. The structure as claimed in claim 33, wherein the metal mask layer is made of one of the following materials selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten and tungsten nitride.
37. The structure as claimed in claim 33, wherein the mask layer is a silicon nitride layer or a silicon carbide layer.
38. The structure as claimed in claim 33, wherein the first stop layer is a silicon nitride layer or a silicon carbide layer.
39. The structure as claimed in claim 33, wherein the third dielectric layer is a second stop layer.
40. A structure for forming an opening on a substrate, comprising:
a dielectric layer on the substrate;
a plurality of mask layers at least comprising a metal mask layer on the dielectric layer; and
an anti-reflection layer on the plurality of mask layers.
41. The structure as claimed in claim 40, wherein materials for forming the dielectric layer include inorganic polymer containing silicon.
42. The structure as claimed in claim 40, wherein the anti-reflection layer is a bottom anti-reflection coating layer made of fluid organic polymer.
43. The structure as claimed in claim 40, wherein the metal mask layer is made of one of the following materials selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten and tungsten nitride.
44. The structure as claimed in claim 40, wherein the mask layer is a silicon nitride layer or a silicon carbide layer.
45. A structure for forming an opening on a substrate, comprising:
a first dielectric layer on the substrate;
a stop layer on the first dielectric layer;
a second dielectric layer on the stop layer;
a plurality of mask layers at least comprising a metal mask layer on the second dielectric layer; and
an anti-reflection layer on the plurality of mask layers.
46. The structure as claimed in claim 45, wherein materials for forming the first and second dielectric layers include inorganic polymer containing silicon.
47. The structure as claimed in claim 45, wherein the anti-reflection layer is a bottom anti-reflection coating layer made of fluid organic polymer.
48. The structure as claimed in claim 45, wherein the metal mask layer is made of one of the following materials selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten and tungsten nitride.
49. The structure as claimed in claim 45, wherein the mask layer is a silicon nitride layer or a silicon carbide layer.
50. The structure as claimed in claim 45, wherein the stop layer is a silicon nitride layer or a silicon carbide layer.
US11/021,411 2002-01-10 2004-12-23 Method for forming openings in low dielectric constant material layer Abandoned US20050110152A1 (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050170625A1 (en) * 2004-01-29 2005-08-04 Chartered Semiconductor Manufacturing Ltd. Novel method to control dual damascene trench etch profile and trench depth uniformity
US7064075B2 (en) * 2002-09-18 2006-06-20 Stmicroelectronics S.R.L. Method for manufacturing semiconductor electronics devices
US20080254204A1 (en) * 2007-04-16 2008-10-16 Infineon Technologies Ag Dielectric apparatus and associated methods
US20090023287A1 (en) * 2007-07-17 2009-01-22 United Microelectronics Corp. Interconnection process
US20130023122A1 (en) * 2011-07-20 2013-01-24 Nemani Srinivas D Method of multiple patterning of a low-k dielectric film
WO2014120576A1 (en) * 2013-01-29 2014-08-07 Applied Materials, Inc. Method of patterning a low-k dielectric film
US8802572B2 (en) * 2012-07-10 2014-08-12 Applied Materials, Inc. Method of patterning a low-k dielectric film
CN104505344A (en) * 2014-08-20 2015-04-08 上海华力微电子有限公司 Method for forming porous ultra-low dielectric material

Families Citing this family (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6831013B2 (en) * 2001-11-13 2004-12-14 United Microelectronics Corp. Method of forming a dual damascene via by using a metal hard mask layer
US6815820B2 (en) * 2002-05-09 2004-11-09 Freescale Semiconductor, Inc. Method for forming a semiconductor interconnect with multiple thickness
KR100457044B1 (en) * 2002-09-25 2004-11-10 삼성전자주식회사 Method for manufacturing semiconductor device
US20040219796A1 (en) * 2003-05-01 2004-11-04 Chih-Ning Wu Plasma etching process
US7052621B2 (en) * 2003-06-13 2006-05-30 Infineon Technologies Ag Bilayered metal hardmasks for use in Dual Damascene etch schemes
US7732326B2 (en) 2004-02-25 2010-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method
US20050184288A1 (en) * 2004-02-25 2005-08-25 Tien-I Bao Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method
JP2006024811A (en) * 2004-07-09 2006-01-26 Sony Corp Method for manufacturing semiconductor device
US7189635B2 (en) * 2004-09-17 2007-03-13 Hewlett-Packard Development Company, L.P. Reduction of a feature dimension in a nano-scale device
US7335980B2 (en) * 2004-11-04 2008-02-26 International Business Machines Corporation Hardmask for reliability of silicon based dielectrics
US7045464B1 (en) * 2004-11-15 2006-05-16 International Business Machines Corporation Via reactive ion etching process
KR100632658B1 (en) * 2004-12-29 2006-10-12 주식회사 하이닉스반도체 Method of forming metal line in semiconductor device
US20060148243A1 (en) * 2004-12-30 2006-07-06 Jeng-Ho Wang Method for fabricating a dual damascene and polymer removal
CN100353520C (en) * 2005-01-07 2007-12-05 联华电子股份有限公司 Method for making dual inlay structure and removing its remnant polymer
JP5186086B2 (en) * 2005-04-11 2013-04-17 アイメック Dual damascene patterning approach
DE102005020060B4 (en) * 2005-04-29 2012-02-23 Advanced Micro Devices, Inc. A method of patterning a low-k dielectric using a hardmask
US7192878B2 (en) * 2005-05-09 2007-03-20 United Microelectronics Corp. Method for removing post-etch residue from wafer surface
US7531448B2 (en) * 2005-06-22 2009-05-12 United Microelectronics Corp. Manufacturing method of dual damascene structure
US7857982B2 (en) * 2005-07-19 2010-12-28 Micron Technology, Inc. Methods of etching features into substrates
CN100423226C (en) * 2005-07-19 2008-10-01 联华电子股份有限公司 Method for producing double embedded structure
US20070066047A1 (en) * 2005-09-18 2007-03-22 Jianhui Ye Method of forming opening and contact
US20070099417A1 (en) * 2005-10-28 2007-05-03 Applied Materials, Inc. Adhesion and minimizing oxidation on electroless CO alloy films for integration with low K inter-metal dielectric and etch stop
US7514365B2 (en) * 2005-11-16 2009-04-07 United Microelectronics Corp. Method of fabricating opening and plug
US20070205507A1 (en) * 2006-03-01 2007-09-06 Hui-Lin Chang Carbon and nitrogen based cap materials for metal hard mask scheme
US20070249165A1 (en) * 2006-04-05 2007-10-25 Huang Chun-Jen Dual damascene process
US7704680B2 (en) * 2006-06-08 2010-04-27 Advanced Micro Devices, Inc. Double exposure technology using high etching selectivity
US7550377B2 (en) * 2006-06-22 2009-06-23 United Microelectronics Corp. Method for fabricating single-damascene structure, dual damascene structure, and opening thereof
US7423282B2 (en) * 2006-07-06 2008-09-09 Infineon Technologies Ag Memory structure and method of manufacture
WO2008047715A1 (en) * 2006-10-12 2008-04-24 Nissan Chemical Industries, Ltd. Method for manufacturing semiconductor device using quadruple-layer laminate
US7691754B2 (en) 2006-10-18 2010-04-06 United Microelectronics Corp. Method for removing photoresist layer and method of forming opening
US20080119040A1 (en) * 2006-11-21 2008-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a dual damascene structure
KR100799068B1 (en) * 2006-12-21 2008-01-29 동부일렉트로닉스 주식회사 The fabricating method of semiconductor device
KR100802226B1 (en) * 2006-12-21 2008-02-11 주식회사 하이닉스반도체 Method for forming dual damascene pattern
US20090093114A1 (en) * 2007-10-09 2009-04-09 Sean David Burns Method of forming a dual-damascene structure using an underlayer
KR100885620B1 (en) * 2007-12-21 2009-02-24 주식회사 동부하이텍 Method for fabricating semiconductor device
DE102008016425B4 (en) * 2008-03-31 2015-11-19 Advanced Micro Devices, Inc. A method of patterning a metallization layer by reducing degradation of the dielectric material caused by resist removal
US20090314743A1 (en) * 2008-06-20 2009-12-24 Hong Ma Method of etching a dielectric layer
CN101937868B (en) * 2009-06-30 2013-02-13 上海华虹Nec电子有限公司 Method for making through hole in integrated circuit
CN102082114B (en) * 2009-12-01 2013-03-27 中芯国际集成电路制造(上海)有限公司 Forming method of dual damascene structure
CN102420170A (en) * 2011-05-13 2012-04-18 上海华力微电子有限公司 Dual damascene process for trench-first metal hard mask of super-thick top-layer metal
CN102420171A (en) * 2011-05-13 2012-04-18 上海华力微电子有限公司 Dual damascene manufacturing process for super-thick top-layer metal
US8399359B2 (en) 2011-06-01 2013-03-19 United Microelectronics Corp. Manufacturing method for dual damascene structure
CN102412196A (en) * 2011-09-15 2012-04-11 上海华力微电子有限公司 Fabrication method for copper Damascus interconnected structure
CN102339793A (en) * 2011-10-29 2012-02-01 上海华力微电子有限公司 Manufacture method of semiconductor device
CN103165374B (en) * 2011-12-08 2017-05-10 中微半导体设备(上海)有限公司 Plasma processing device and edge ring applied to the same
CN103165576B (en) * 2011-12-13 2015-10-14 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacture method thereof
CN103296078B (en) * 2012-02-23 2017-01-18 宜普电源转换公司 Enhancement mode GaN HEMT device having grid spacer and method for fabricating GaN HEMT device
CN103426749B (en) * 2012-05-14 2015-11-25 中芯国际集成电路制造(上海)有限公司 The formation method of opening and stacked structure
CN103426745B (en) * 2012-05-24 2015-12-09 中芯国际集成电路制造(上海)有限公司 The formation method of semiconductor structure
US8735295B2 (en) 2012-06-19 2014-05-27 United Microelectronics Corp. Method of manufacturing dual damascene structure
CN102737983B (en) * 2012-07-05 2015-06-17 中微半导体设备(上海)有限公司 Method for forming semiconductor structure
CN102737984B (en) * 2012-07-06 2015-08-05 中微半导体设备(上海)有限公司 The formation method of semiconductor structure
US8647991B1 (en) 2012-07-30 2014-02-11 United Microelectronics Corp. Method for forming dual damascene opening
CN103681464A (en) * 2012-09-13 2014-03-26 中芯国际集成电路制造(上海)有限公司 Through hole and trench forming method
US8921226B2 (en) 2013-01-14 2014-12-30 United Microelectronics Corp. Method of forming semiconductor structure having contact plug
CN104051324A (en) * 2013-03-13 2014-09-17 中芯国际集成电路制造(上海)有限公司 Forming method of metal interconnection structure
US20140342553A1 (en) * 2013-05-14 2014-11-20 United Microelectronics Corp. Method for Forming Semiconductor Structure Having Opening
US8765546B1 (en) 2013-06-24 2014-07-01 United Microelectronics Corp. Method for fabricating fin-shaped field-effect transistor
CN103346119A (en) * 2013-06-27 2013-10-09 上海华力微电子有限公司 Method for decreasing critical size of copper-connection groove
US8962490B1 (en) 2013-10-08 2015-02-24 United Microelectronics Corp. Method for fabricating semiconductor device
CN104752355B (en) * 2013-12-31 2018-05-04 中芯国际集成电路制造(上海)有限公司 A kind of manufacture method of semiconductor devices
CN104979273B (en) * 2014-04-04 2018-02-16 中芯国际集成电路制造(上海)有限公司 The method for forming interconnection structure
CN111969104B (en) 2019-05-20 2023-09-12 联华电子股份有限公司 Semiconductor element and manufacturing method thereof
CN111128865A (en) * 2019-12-18 2020-05-08 华虹半导体(无锡)有限公司 Damascus interconnection process
CN113161284A (en) * 2020-01-07 2021-07-23 台湾积体电路制造股份有限公司 Method for manufacturing interconnection structure
US11289375B2 (en) 2020-03-23 2022-03-29 International Business Machines Corporation Fully aligned interconnects with selective area deposition

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6270392B1 (en) * 1998-06-19 2001-08-07 Nec Corporation Polishing apparatus and method with constant polishing pressure
US6323121B1 (en) * 2000-05-12 2001-11-27 Taiwan Semiconductor Manufacturing Company Fully dry post-via-etch cleaning method for a damascene process
US6352922B1 (en) * 1999-07-14 2002-03-05 Samsung Electronics Co., Ltd. Method of fabrication of a semiconductor device having a double layer type anti-reflective layer
US6696222B2 (en) * 2001-07-24 2004-02-24 Silicon Integrated Systems Corp. Dual damascene process using metal hard mask
US6790770B2 (en) * 2001-11-08 2004-09-14 Taiwan Semiconductor Manufacturing Co., Ltd Method for preventing photoresist poisoning
US6797647B2 (en) * 2001-06-19 2004-09-28 Matsushita Electric Industrial Co., Ltd. Method for fabricating organic thin film

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6017817A (en) * 1999-05-10 2000-01-25 United Microelectronics Corp. Method of fabricating dual damascene
US6197681B1 (en) * 1999-12-31 2001-03-06 United Microelectronics Corp. Forming copper interconnects in dielectric materials with low constant dielectrics
US6399478B2 (en) * 2000-02-22 2002-06-04 Sanyo Electric Co., Ltd. Method of making a dual damascene structure with modified insulation
US6444557B1 (en) * 2000-03-14 2002-09-03 International Business Machines Corporation Method of forming a damascene structure using a sacrificial conductive layer
US6350700B1 (en) * 2000-06-28 2002-02-26 Lsi Logic Corporation Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
US6372653B1 (en) * 2000-07-07 2002-04-16 Taiwan Semiconductor Manufacturing Co., Ltd Method of forming dual damascene structure
US6309955B1 (en) * 2001-02-16 2001-10-30 Advanced Micro Devices, Inc. Method for using a CVD organic barc as a hard mask during via etch
US6455409B1 (en) * 2001-02-28 2002-09-24 Advanced Micro Devices, Inc. Damascene processing using a silicon carbide hard mask

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6270392B1 (en) * 1998-06-19 2001-08-07 Nec Corporation Polishing apparatus and method with constant polishing pressure
US6352922B1 (en) * 1999-07-14 2002-03-05 Samsung Electronics Co., Ltd. Method of fabrication of a semiconductor device having a double layer type anti-reflective layer
US6323121B1 (en) * 2000-05-12 2001-11-27 Taiwan Semiconductor Manufacturing Company Fully dry post-via-etch cleaning method for a damascene process
US6797647B2 (en) * 2001-06-19 2004-09-28 Matsushita Electric Industrial Co., Ltd. Method for fabricating organic thin film
US6696222B2 (en) * 2001-07-24 2004-02-24 Silicon Integrated Systems Corp. Dual damascene process using metal hard mask
US6790770B2 (en) * 2001-11-08 2004-09-14 Taiwan Semiconductor Manufacturing Co., Ltd Method for preventing photoresist poisoning

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064075B2 (en) * 2002-09-18 2006-06-20 Stmicroelectronics S.R.L. Method for manufacturing semiconductor electronics devices
US20050170625A1 (en) * 2004-01-29 2005-08-04 Chartered Semiconductor Manufacturing Ltd. Novel method to control dual damascene trench etch profile and trench depth uniformity
US7247555B2 (en) * 2004-01-29 2007-07-24 Chartered Semiconductor Manufacturing Ltd. Method to control dual damascene trench etch profile and trench depth uniformity
US7635634B2 (en) * 2007-04-16 2009-12-22 Infineon Technologies Ag Dielectric apparatus and associated methods
US20080254204A1 (en) * 2007-04-16 2008-10-16 Infineon Technologies Ag Dielectric apparatus and associated methods
US20090023287A1 (en) * 2007-07-17 2009-01-22 United Microelectronics Corp. Interconnection process
US20090023283A1 (en) * 2007-07-17 2009-01-22 United Microelectronics Corp. Interconnection process
US7704870B2 (en) * 2007-07-17 2010-04-27 United Microelectronics Corp. Via-first interconnection process using gap-fill during trench formation
US20130023122A1 (en) * 2011-07-20 2013-01-24 Nemani Srinivas D Method of multiple patterning of a low-k dielectric film
US8940642B2 (en) * 2011-07-20 2015-01-27 Applied Materials, Inc. Method of multiple patterning of a low-K dielectric film
US8802572B2 (en) * 2012-07-10 2014-08-12 Applied Materials, Inc. Method of patterning a low-k dielectric film
WO2014120576A1 (en) * 2013-01-29 2014-08-07 Applied Materials, Inc. Method of patterning a low-k dielectric film
US8987139B2 (en) 2013-01-29 2015-03-24 Applied Materials, Inc. Method of patterning a low-k dielectric film
TWI610364B (en) * 2013-01-29 2018-01-01 應用材料股份有限公司 Method of patterning a low-k dielectric film
CN104505344A (en) * 2014-08-20 2015-04-08 上海华力微电子有限公司 Method for forming porous ultra-low dielectric material

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US20030129844A1 (en) 2003-07-10
US20030129842A1 (en) 2003-07-10
CN1292470C (en) 2006-12-27
US6972259B2 (en) 2005-12-06
US6638871B2 (en) 2003-10-28

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