CN102420171A - Dual damascene manufacturing process for super-thick top-layer metal - Google Patents
Dual damascene manufacturing process for super-thick top-layer metal Download PDFInfo
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- CN102420171A CN102420171A CN2011101236821A CN201110123682A CN102420171A CN 102420171 A CN102420171 A CN 102420171A CN 2011101236821 A CN2011101236821 A CN 2011101236821A CN 201110123682 A CN201110123682 A CN 201110123682A CN 102420171 A CN102420171 A CN 102420171A
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Abstract
The invention discloses a dual damascene manufacturing process for a super-thick top-layer metal. According to the dual damascene manufacturing process disclosed by the invention, the problems that the etched high aspect ratio and the size of a through hole cannot be controlled on the premise of no addition of process steps and no prolonging of the process period in the prior art are solved. A dielectric layer is subjected to dry method etching for multiple times, so that the quality of each etching is ensured, further the effective control over the high aspect ratio and the size of the through hole is realized, the production cost is reduced and the production period is shortened.
Description
Technical field
The present invention relates to a kind of dual damascene manufacturing process, relate in particular to a kind of metal mask dual damascene manufacturing process that is used for the first part groove of ultra thick metal.
Background technology
Damascus technics is that a kind of metal wire embeds technology, is meant that generally copper embeds technology; Reason is that copper is difficult for etching; Can only copper be embedded through electroplating processing (ECP) method through carving the figure that needs earlier, last cmp (CMP) grinds off unnecessary copper again.
For the manufacturing of ultra thick top-level metallic, if use traditional first through hole (Via) back groove (Trench) dual damascene manufacturing process, usually gash depth reach 3um or more than, the depth-to-width ratio of through hole surpasses 10:1, present etching technics is difficult to realize.
Processing step of the prior art is: the dielectric layer deposit, wherein, dielectric barrier layer: SIN, dielectric layer: SiO2; The spin coating photoresist, photoetching forms via hole image; The dry etching through hole, photoresist is removed in ashing; Depositing metal barrier layer (TaN/Ta) and copper seed layer; Through hole is filled up in electro-coppering; Cmp (CMP) is removed excess metal; On through hole, the dielectric layer deposit, wherein, dielectric barrier layer: SIN dielectric layer: SiO2; The spin coating photoresist, photoetching forms groove figure; The dry etching groove, photoresist is removed in ashing; Depositing metal barrier layer (TaN/Ta) and copper seed layer; Groove is filled up in electro-coppering; Cmp (CMP) is removed excess metal.
The industry common method is to do top layer through hole and ultra thick top-level metallic respectively with single Damascus technics at present.This has solved the problem of through hole high-aspect-ratio, but this can increase manufacturing technology steps, extends manufacture cycle.
Another kind method is with groove dual damascene manufacturing process (patent: US 7297629) after the first partial through holes.This can solve the problem of first through-hole approaches via etch high-aspect-ratio, but this method is difficult to the control clear size of opening.
Summary of the invention
The invention discloses a kind of dual damascene manufacturing process that is used for ultra thick top-level metallic, in order to solve the problem that can't be issued to control via etch high-aspect-ratio and clear size of opening control in the prior art in the prerequisite that does not increase processing step, prolongation process cycle.
Above-mentioned purpose of the present invention realizes through following technical scheme:
A kind of dual damascene manufacturing process that is used for ultra thick top-level metallic; Wherein, Deposit multilayer dielectric layer on the silicon chip, be equipped with dielectric barrier layer between the dielectric layer of the bottom and the said silicon chip and between any two adjacent dielectric layers, deposition has metal hard mask on the dielectric layer of top layer; Spin coating photoresist on said metal hard mask, photoetching forms groove figure; Carry out dry etching, open metal hard mask, remove photoresistance; Through the spin coating photoresist, photoetching forms via hole image; Through dry etch process repeatedly, make the bottom of through hole pass the dielectric layer of the bottom and the dielectric barrier layer between the said silicon chip, arrive said silicon chip, and the groove that forms terminates in the dielectric layer of the bottom; Depositing metal barrier layer and copper seed layer are filled up through hole and groove with electro-coppering; Carry out the cmp planarization, remove excess metal.
The aforesaid dual damascene manufacturing process that is used for ultra thick top-level metallic; Wherein, the order that on said silicon chip, carries out the deposition of said dielectric layer and said dielectric barrier layer is specially: precipitate one first dielectric barrier layer, one first dielectric layer, one second dielectric barrier layer, one second dielectric layer, one the 3rd dielectric barrier layer, one the 3rd dielectric layer and a metal hard mask on the silicon chip successively.
The aforesaid dual damascene manufacturing process that is used for ultra thick top-level metallic, wherein, said repeatedly dry etch process specifically comprises: the dry etching through hole, make through hole terminate in the 3rd dielectric barrier layer, remove photoresistance; Carry out dry etching, open the 3rd dielectric barrier layer of via bottoms; Carry out dry etching, etching groove terminates in the 3rd dielectric barrier layer, and through hole terminates in second dielectric barrier layer; Carry out dry etching, remove the 3rd dielectric barrier layer of channel bottom, open second dielectric barrier layer of via bottoms; Carry out dry etching, groove terminates in second dielectric barrier layer, and through hole terminates in first dielectric barrier layer; Carry out dry etching, open first dielectric barrier layer of via bottoms.
The aforesaid dual damascene manufacturing process that is used for ultra thick top-level metallic, wherein, also precipitating between the dielectric layer of the said the superiors and the said metal hard mask has a dielectric protection layer.
The aforesaid dual damascene manufacturing process that is used for ultra thick top-level metallic wherein, terminates in the 3rd dielectric barrier layer and step at the step through hole and opens between the 3rd dielectric barrier layer of via bottoms and also comprise: remove dielectric protection layer.
The aforesaid dual damascene manufacturing process that is used for ultra thick top-level metallic, wherein, said multilayer dielectric layer all forms through chemical vapor deposition silicon dioxide.
The aforesaid dual damascene manufacturing process that is used for ultra thick top-level metallic, wherein, the dielectric layer of the said bottom is a via dielectric layer.
The aforesaid dual damascene manufacturing process that is used for ultra thick top-level metallic, wherein, the dielectric layer except that the dielectric layer of the said bottom is the raceway groove dielectric layer.
The aforesaid dual damascene manufacturing process that is used for ultra thick top-level metallic, wherein, processing step: dry etching; Groove terminates in second dielectric barrier layer; Through hole terminates in first dielectric barrier layer and processing step: dry etching, etching groove terminate in the 3rd dielectric barrier layer, and through hole terminates in second dielectric barrier layer; Two processing steps all adopt the high selectivity etching technics, with the size of control through hole.
The aforesaid dual damascene manufacturing process that is used for ultra thick top-level metallic wherein, also comprises wet clean process in said repeatedly dry etch process, gather too much polymer with removal.
The aforesaid dual damascene manufacturing process that is used for ultra thick top-level metallic wherein, is saidly carried out the cmp planarization, removes in the processing step of excess metal to comprise the removal metal hard mask.
The aforesaid dual damascene manufacturing process that is used for ultra thick top-level metallic wherein, is saidly carried out the cmp planarization, removes in the processing step of excess metal to comprise the removal dielectric protection layer.
In sum; Owing to adopted technique scheme; The dual damascene manufacturing process that the present invention is used for ultra thick top-level metallic has solved the problem that prior art can't be issued to control via etch high-aspect-ratio and clear size of opening control in the prerequisite that does not increase processing step, prolong process cycle; Through repeatedly respectively dielectric layer being carried out dry etching, guaranteed the quality of each etching, and then realized effective control of size of high-aspect-ratio and the through hole of through hole; And reduced production cost, shortened the cycle of producing.
Description of drawings
Fig. 1 be the present invention's dual damascene manufacturing process of being used for ultra thick top-level metallic to carrying out post-depositional structure chart on the silicon chip;
Fig. 2 ~ Figure 11 is the process sequence diagram that the present invention is used for the dual damascene manufacturing process of ultra thick top-level metallic.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
A kind of dual damascene manufacturing process that is used for ultra thick top-level metallic; Wherein, Deposit multilayer dielectric layer on the silicon chip, be equipped with dielectric barrier layer between the dielectric layer of the bottom and the said silicon chip and between any two adjacent dielectric layers, deposition has metal hard mask on the dielectric layer of top layer; The number of plies of dielectric layer and dielectric barrier layer is to decide according to the thickness of ultra thick top-level metallic and process conditions, and the number of plies of dielectric layer and dielectric barrier layer is identical; Spin coating photoresist on said metal hard mask, photoetching forms groove figure; Dry etching is opened metal hard mask, and photoresistance is removed in ashing; The spin coating photoresist, photoetching forms via hole image; Through dry etch process repeatedly, make the bottom of through hole pass the dielectric layer of the bottom and the dielectric barrier layer between the said silicon chip, arrive said silicon chip, and the groove that forms terminates in the dielectric layer of the bottom; Depositing metal barrier layer and copper seed layer are filled up through hole and groove with electro-coppering; Carry out the cmp planarization, remove excess metal, whole dual damascene manufacturing process has also just been accomplished.
Fig. 1 be the present invention's dual damascene manufacturing process of being used for ultra thick top-level metallic to carrying out post-depositional structure chart on the silicon chip; See also Fig. 1; In one embodiment of the present of invention, the order that on said silicon chip 101, carries out the deposition of said dielectric layer and said dielectric barrier layer is specially: precipitate one first dielectric barrier layer 201, one first dielectric layer 301, one second dielectric barrier layer 202, one second dielectric layer 302, one the 3rd dielectric barrier layer 203, one the 3rd dielectric layer 303 and a metal hard mask 401 on the silicon chip 101 successively.
The complete step of this embodiment of the invention is: see also Fig. 2, and spin coating photoresist on said metal hard mask 401, photoetching forms groove figure, gets ready for subsequent etching forms groove; See also Fig. 3, adopt dry etch process, open metal hard mask 401, get ready for subsequent etching forms groove, and photoresistance is removed in ashing; See also Fig. 4, be etched at metal hard mask 401 and metal hard mask 401 and open spin coating photoresist on the 3rd dielectric layer 303 that is exposed, and photoetching forms via hole image; See also Fig. 5, form through hole through dry etching, and make through hole terminate in the 3rd dielectric barrier layer 203, photoresistance is removed in ashing; See also Fig. 6,, open the 3rd dielectric barrier layer 203 of via bottoms through dry etch process; See also Fig. 7, through dry etching, etching groove terminates in the 3rd dielectric barrier layer 203, and through hole terminates in second dielectric barrier layer 202; See also Fig. 8,, remove the 3rd dielectric barrier layer 203 of channel bottom, open second dielectric barrier layer 202 of via bottoms, make groove terminate in second dielectric layer 302, and make through hole terminate in first dielectric layer 301 through dry etching; See also Fig. 9, carry out dry etching, groove terminates in second dielectric barrier layer 202, and through hole terminates in first dielectric barrier layer 201; See also Figure 10, carry out dry etching, open first dielectric barrier layer 201 of via bottoms, make through hole finally terminate in silicon chip 101; See also Figure 11, depositing metal barrier layer and copper seed layer are filled up through hole and groove with electro-coppering; See also Figure 12, carry out the cmp planarization, remove excess metal.
The content that repeatedly dry etch process among the present invention specifically comprises has obtained embodying in above-mentioned complete step, so no longer give unnecessary details.
Also precipitate between the dielectric layer of the superiors among the present invention and the said metal hard mask dielectric protection layer is arranged.
Terminating in the 3rd dielectric barrier layer 203 and step at the step through hole among the present invention opens between the 3rd dielectric barrier layer 203 of via bottoms and also comprises: remove dielectric protection layer.
Multilayer dielectric layer among the present invention all forms through chemical vapor deposition silicon dioxide.
The dielectric layer of the bottom among the present invention is a via dielectric layer.
Dielectric layer among the present invention except that the dielectric layer of the said bottom is the raceway groove dielectric layer.
Processing step among the present invention: dry etching; Groove terminates in second dielectric barrier layer 202; Through hole terminates in first dielectric barrier layer 201 and the processing step: dry etching, etching groove terminate in the 3rd dielectric barrier layer 203, and through hole terminates in second dielectric barrier layer 202; Two processing steps all adopt the high selectivity etching technics, with the size of control through hole.
In said repeatedly dry etch process, also comprise wet clean process among the present invention, gather too much polymer with removal.
Dielectric barrier layer among the present invention and dielectric protection layer can be used chemical vapor deposition SiN, SiC, SiCN etc.
The manufacture craft of the metal hard mask among the present invention can be chosen CVD or PVD deposit TaN, Ta, TiN, Ti etc.
Ultra thick top-level metallic thickness among the present invention is generally 3 microns or thicker, at least 3 microns of multilayer raceway groove medium thickness sums.
In the method provided by the present invention; Need not to add step to reach the technique effect of removing metal hard mask, shown in figure 12, carry out the cmp planarization of the present invention; Comprise in the processing step of removal excess metal and remove metal hard mask 401; Promptly in the technical process of cmp planarization, metal hard mask 401 is ground removal together, need not to increase processing step.
Equally, carry out the cmp planarization among the present invention, comprise the removal dielectric protection layer in the processing step of removal excess metal, need not further to increase processing step.
In sum; Owing to adopted technique scheme; The dual damascene manufacturing process that the present invention is used for ultra thick top-level metallic has solved the problem that prior art can't be issued to control via etch high-aspect-ratio and clear size of opening control in the prerequisite that does not increase processing step, prolong process cycle; Through repeatedly respectively dielectric layer being carried out dry etching, guaranteed the quality of each etching, and then realized effective control of size of high-aspect-ratio and the through hole of through hole; And reduced production cost, shortened the cycle of producing.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (12)
1. dual damascene manufacturing process that is used for ultra thick top-level metallic; It is characterized in that; Deposit multilayer dielectric layer on the silicon chip; Be equipped with dielectric barrier layer between the dielectric layer of the bottom and the said silicon chip and between any two adjacent dielectric layers, deposition has metal hard mask on the dielectric layer of top layer; Spin coating photoresist on said metal hard mask, photoetching forms groove figure; Carry out dry etching, open metal hard mask, remove photoresistance; Through the spin coating photoresist, photoetching forms via hole image; Through dry etch process repeatedly, make the bottom of through hole pass the dielectric layer of the bottom and the dielectric barrier layer between the said silicon chip, arrive said silicon chip, and the groove that forms terminates in the dielectric layer of the bottom; Depositing metal barrier layer and copper seed layer are filled up through hole and groove with electro-coppering; Carry out the cmp planarization, remove excess metal.
2. the dual damascene manufacturing process that is used for ultra thick top-level metallic according to claim 1; It is characterized in that the order that on said silicon chip, carries out the deposition of said dielectric layer and said dielectric barrier layer is specially: precipitate one first dielectric barrier layer, one first dielectric layer, one second dielectric barrier layer, one second dielectric layer, one the 3rd dielectric barrier layer, one the 3rd dielectric layer and a metal hard mask on the silicon chip successively.
3. the dual damascene manufacturing process that is used for ultra thick top-level metallic according to claim 2 is characterized in that, said repeatedly dry etch process specifically comprises: the dry etching through hole, and make through hole terminate in the 3rd dielectric barrier layer, remove photoresistance; Carry out dry etching, open the 3rd dielectric barrier layer of via bottoms; Carry out dry etching, etching groove terminates in the 3rd dielectric barrier layer, and through hole terminates in second dielectric barrier layer; Carry out dry etching, remove the 3rd dielectric barrier layer of channel bottom, open second dielectric barrier layer of via bottoms; Carry out dry etching, groove terminates in second dielectric barrier layer, and through hole terminates in first dielectric barrier layer; Carry out dry etching, open first dielectric barrier layer of via bottoms.
4. the dual damascene manufacturing process that is used for ultra thick top-level metallic according to claim 1 is characterized in that, also precipitating between the dielectric layer of the said the superiors and the said metal hard mask has a dielectric protection layer.
5. the dual damascene manufacturing process that is used for ultra thick top-level metallic according to claim 3 is characterized in that, terminates in the 3rd dielectric barrier layer and step at the step through hole and opens between the 3rd dielectric barrier layer of via bottoms and also comprise: remove dielectric protection layer.
6. the dual damascene manufacturing process that is used for ultra thick top-level metallic according to claim 1 is characterized in that said multilayer dielectric layer all forms through chemical vapor deposition silicon dioxide.
7. the dual damascene manufacturing process that is used for ultra thick top-level metallic according to claim 1 is characterized in that the dielectric layer of the said bottom is a via dielectric layer.
8. the dual damascene manufacturing process that is used for ultra thick top-level metallic according to claim 1 is characterized in that the dielectric layer except that the dielectric layer of the said bottom is the raceway groove dielectric layer.
9. the dual damascene manufacturing process that is used for ultra thick top-level metallic according to claim 3 is characterized in that processing step: dry etching; Groove terminates in second dielectric barrier layer; Through hole terminates in first dielectric barrier layer and processing step: dry etching, etching groove terminate in the 3rd dielectric barrier layer, and through hole terminates in second dielectric barrier layer; Two processing steps all adopt the high selectivity etching technics, with the size of control through hole.
10. according to claim 1 or the 3 described dual damascene manufacturing process that are used for ultra thick top-level metallic, it is characterized in that, in said repeatedly dry etch process, also comprise wet clean process, gather too much polymer with removal.
11. the dual damascene manufacturing process that is used for ultra thick top-level metallic according to claim 1 is characterized in that, saidly carries out the cmp planarization, removes in the processing step of excess metal to comprise the removal metal hard mask.
12. the dual damascene manufacturing process that is used for ultra thick top-level metallic according to claim 4 is characterized in that, saidly carries out the cmp planarization, removes in the processing step of excess metal to comprise the removal dielectric protection layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011101236821A CN102420171A (en) | 2011-05-13 | 2011-05-13 | Dual damascene manufacturing process for super-thick top-layer metal |
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| CN2011101236821A CN102420171A (en) | 2011-05-13 | 2011-05-13 | Dual damascene manufacturing process for super-thick top-layer metal |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109755108A (en) * | 2017-11-07 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1420540A (en) * | 2001-11-20 | 2003-05-28 | 联华电子股份有限公司 | Method for mfg. double inlaid structure |
| US20030129842A1 (en) * | 2002-01-10 | 2003-07-10 | Chin-Jung Wang | Method for forming openings in low dielectric constant material layer |
| US20050029010A1 (en) * | 2003-08-04 | 2005-02-10 | Jeong-Hoon Ahn | Void-free metal interconnection steucture and method of forming the same |
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- 2011-05-13 CN CN2011101236821A patent/CN102420171A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1420540A (en) * | 2001-11-20 | 2003-05-28 | 联华电子股份有限公司 | Method for mfg. double inlaid structure |
| US20030129842A1 (en) * | 2002-01-10 | 2003-07-10 | Chin-Jung Wang | Method for forming openings in low dielectric constant material layer |
| US20050029010A1 (en) * | 2003-08-04 | 2005-02-10 | Jeong-Hoon Ahn | Void-free metal interconnection steucture and method of forming the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109755108A (en) * | 2017-11-07 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor devices |
| CN109755108B (en) * | 2017-11-07 | 2021-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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Application publication date: 20120418 |