CN102420170A - Dual damascene process for trench-first metal hard mask of super-thick top-layer metal - Google Patents
Dual damascene process for trench-first metal hard mask of super-thick top-layer metal Download PDFInfo
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- CN102420170A CN102420170A CN2011101236817A CN201110123681A CN102420170A CN 102420170 A CN102420170 A CN 102420170A CN 2011101236817 A CN2011101236817 A CN 2011101236817A CN 201110123681 A CN201110123681 A CN 201110123681A CN 102420170 A CN102420170 A CN 102420170A
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Abstract
The invention discloses a dual damascene process for a trench-first metal hard mask of a super-thick top-layer metal. The dual damascene process comprises the following steps of: sequentially depositing a dielectric barrier layer, a first dielectric layer, an intermediate dielectric barrier layer and a second dielectric layer on the finished front metal layer of a silicon chip; spin coating photoresist and photoetching to form a trench pattern; carrying out dry method etching on a trench to the first dielectric layer and removing the photoresist; depositing a metal hard mask as a through-hole etched hard mask; spin coating a bottom anti-reflecting coating and filling the trench; back etching the bottom anti-reflecting layer to the interior of the trench; spin coating the photoresist and photoetching to form a through-hole pattern; carrying out dry method etching and opening the metal hard mask and removing a residual photoresistor and the bottom anti-reflecting coating by ashing; carrying out dry method etching to form a through hole; depositing a metal barrier layer and a copper seed crystal layer; and electroplating copper for filling the through hole and the trench. According to the trench-first and through-hole-second dual damascene process using the metal mask, the aims of effectively controlling the high aspect ratio and the size of the through hole are achieved.
Description
Technical field
The present invention relates to a kind of dual damascene process, relate in particular to a kind of hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic.
Background technology
For the manufacturing of ultra thick top-level metallic, if use traditional first through hole (Via) back groove (Trench) dual damascene manufacturing process, usually gash depth reach 3um or more than, the depth-to-width ratio of through hole surpasses 10:1, present etching technics is difficult to realize.
The industry common method is to do top layer through hole and ultra thick top-level metallic respectively with single Damascus technics at present.This has solved the problem of through hole high-aspect-ratio, but this can increase manufacturing technology steps, extends manufacture cycle.
Processing step of the prior art is: the dielectric layer deposit, wherein, dielectric barrier layer: SIN, dielectric layer: SiO2; The spin coating photoresist, photoetching forms via hole image; The dry etching through hole, photoresist is removed in ashing; Depositing metal barrier layer (TaN/Ta) and copper seed layer; Through hole is filled up in electro-coppering; Cmp (CMP) is removed excess metal; On through hole, the dielectric layer deposit, wherein, dielectric barrier layer: SIN dielectric layer: SiO2; The spin coating photoresist, photoetching forms groove figure; The dry etching groove, photoresist is removed in ashing; Depositing metal barrier layer (TaN/Ta) and copper seed layer; Groove is filled up in electro-coppering; Cmp (CMP) is removed excess metal.
The industry common method is to do top layer through hole and ultra thick top-level metallic respectively with single Damascus technics at present.This has solved the problem of through hole high-aspect-ratio, but this can increase manufacturing technology steps, extends manufacture cycle.
Another kind method is with groove dual damascene manufacturing process (patent: US 7297629) after the first partial through holes, but this method is difficult to the control clear size of opening.
Summary of the invention
The invention discloses a kind of hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic, in order to solve the problem that can't be issued to control via etch high-aspect-ratio and clear size of opening control in the prior art in the prerequisite that does not increase processing step, prolongation process cycle.
Above-mentioned purpose of the present invention realizes through technical scheme once:
A kind of hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic; It is characterized in that deposit one dielectric barrier layer, one first dielectric layer, an interlevel dielectric barrier layer and one second dielectric layer successively on the completed anterior layer metal level of silicon chip; The spin coating photoresist, photoetching forms groove figure; Dry etching groove to the first dielectric layer is removed photoresist; The hard mask of depositing metal is as the hard mask of via etch; The spin coating bottom antireflective coating fills up groove; Return and carve bottom antireflective coating to groove; The spin coating photoresist, photoetching forms via hole image; Carry out dry etching, open metal hard mask, remove residue photoresistance and bottom antireflective coating; Carry out dry etching, form through hole; Depositing metal barrier layer and copper seed layer; Through hole and groove are filled up in electro-coppering; Carry out cmp, remove excess metal.
The aforesaid hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic is characterized in that, said first dielectric layer and said second dielectric layer all form through precipitated silica.
The aforesaid hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic is characterized in that, said dielectric barrier layer and said interlevel dielectric barrier layer all form through the deposition silicon nitride.
The aforesaid hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic is characterized in that the thickness of said second dielectric layer is more than or equal to 3 microns.
The aforesaid hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic; It is characterized in that the concrete forming process of said through hole is: after via hole image forms, through dry etching; Open metal hard mask, and remove photoresist and bottom antireflective coating; Dry etching forms through hole through the metal hard mask etching once more.
The aforesaid hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic; It is characterized in that; Said dry etching; Form in the processing step of through hole, said through hole passes said first dielectric layer and said dielectric barrier layer terminates on the completed anterior layer metal level of said silicon chip.
The hard mask dual damascene process of the first trench metal that is used for ultra thick top-level metallic as above is characterized in that, said cmp comprises the removal metal hard mask in the processing step of removal excess metal.
The aforesaid hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic is characterized in that, through dry etching, behind the formation groove, forms metal hard mask through the meteorological depositing technology of chemistry.
The aforesaid hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic is characterized in that, through dry etching, behind the formation groove, forms metal hard mask through the physical vapor depositing technology.
In sum; Owing to adopted technique scheme; The invention solves the problem that can't be issued to control via etch high-aspect-ratio and clear size of opening control in the prior art in the prerequisite that does not increase processing step, prolongation process cycle; Effectively advanced in controlling through through hole behind the first groove and the dual damascene manufacturing process of using metal mask with clear size of opening to through hole, and adopt technical scheme of the present invention to reach to reduce production costs the effect of shortening production cycle.
Description of drawings
Fig. 1 ~ Figure 11 is the block diagram that the present invention is used for the hard mask dual damascene process of first trench metal of ultra thick metal.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
A kind of hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic, wherein,
See also Fig. 1 ~ Figure 11; As shown in Figure 1; Deposit one dielectric barrier layer 201, one first dielectric layer 301, an interlevel dielectric barrier layer 202 and one second dielectric layer 302 successively on the completed anterior layer metal level 102 of silicon chip, wherein, anterior layer metal level 102 is embedded in the anterior layer dielectric layer 101; As shown in Figure 2, spin coating photoresist on second dielectric layer of the superiors forms groove figure through photoetching, for the subsequent etching groove is got ready; As shown in Figure 3, form groove through the dry etch process etching, groove terminates in first dielectric layer 301, and removes photoresist; As shown in Figure 4, the hard mask of depositing metal (Metal Hard Mask is called for short MHM) 401; Make the surface and the sidewall of metal hard mask 401 complete covering grooves; And cover the upper surface of second dielectric layer, metal hard mask 401 is as the hard mask of via etch, for follow-up via etch ready; As shown in Figure 5, spin coating bottom antireflective coating (BARC) fills up groove; As shown in Figure 6, return and carve bottom antireflective coating to groove, for follow-up spin coating photoresist, formation through hole are got ready; As shown in Figure 7, the spin coating photoresist, and through photoetching formation via hole image, wherein via hole image is formed on the bottom anti-reflective figure layer; As shown in Figure 8, carry out dry etching, open metal hard mask 401, through hole passes metal hard mask 401, terminates in first dielectric layer 301, and residue photoresistance and bottom antireflective coating are removed in ashing; As shown in Figure 9, carry out dry etching once more, in first dielectric layer 301, form through hole, and through hole passes on the completed anterior layer metal level 102 that dielectric barrier layer 201 terminates in silicon chip; Shown in figure 10, depositing metal barrier layer and copper seed layer; Through hole and groove are filled up in electro-coppering; Shown in figure 11, cmp (CMP) is removed excess metal, and in chemical mechanical milling tech, metal hard mask 401 is removed with metal barrier in the lump.
Through Fig. 1 ~ 11 processing steps shown in Figure 11; Disclosed hard mask 401 dual damascene process of first trench metal that are used for ultra thick top-level metallic of the present invention have just all been accomplished; Technical scheme through above-mentioned first groove (Trench) back through hole (Via); The present invention effectively solved available technology adopting first through hole (Via) back groove (Trench) technical scheme caused in etching process, is difficult to control the problem of the depth-to-width ratio of through hole; Effectively controlled the high-aspect-ratio of via etch and the size of through hole, and the technical scheme processing step that the present invention adopted is comparatively simple, with respect to prior art processes; Do not increase the processing step of making, can not prolong the cycle of production.
Between said first dielectric layer 301 and said second dielectric layer 302, be deposited with an interlevel dielectric barrier layer 202 among the present invention, can remove the step on deposition interlevel dielectric barrier layer 202 in process of production.
First dielectric layer 301 among the present invention all forms through precipitated silica with said second dielectric layer 302.
The thickness of second dielectric layer 302 among the present invention is more than or equal to 3 microns.
The concrete forming process of the through hole among the present invention is: after via hole image forms; As shown in Figure 8, through dry etching, open metal hard mask 401; Make the bottom of through hole terminate in first dielectric layer 301, and remove the bottom antireflective coating in photoresist and the groove; As shown in Figure 9, carry out time dry etching again, form through hole through metal hard mask 401 etchings.
Pass through dry etching among the present invention, form in the processing step of through hole, said through hole passes said first dielectric layer 301 and terminates on the completed anterior layer metal level 102 of said silicon chip with said dielectric barrier layer 201.
In the method provided by the present invention; Need not to add step to reach the technique effect of removing metal hard mask; Shown in figure 11, at cmp of the present invention, comprise in the processing step of removal excess metal and remove metal hard mask 401; Promptly in the chemical mechanical milling tech process, metal hard mask 401 is ground removal together.
Through dry etching, behind the formation groove, form metal hard mask 401 among the present invention through the meteorological deposition of chemistry (CVD) technology.
Through dry etching, behind the formation groove, form metal hard mask 401 among the present invention through physical vapor deposition (PVD) technology.
Metal hard mask among the present invention can be chosen materials such as TaN, Ta, TiN, Ti and come to form through physical vapor deposition or the meteorological deposition of chemistry.
Metal barrier among the present invention can adopt TaN also can adopt Ta.
In sum; Owing to adopted technique scheme; The invention solves the problem that can't be issued to control via etch high-aspect-ratio and clear size of opening control in the prior art in the prerequisite that does not increase processing step, prolongation process cycle; Effectively advanced in controlling through through hole behind the first groove and the dual damascene manufacturing process of using metal mask with clear size of opening to through hole, and adopt technical scheme of the present invention to reach to reduce production costs the effect of shortening production cycle.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (9)
1. hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic; It is characterized in that deposit one dielectric barrier layer, one first dielectric layer, an interlevel dielectric barrier layer and one second dielectric layer successively on the completed anterior layer metal level of silicon chip; The spin coating photoresist, photoetching forms groove figure; Dry etching groove to the first dielectric layer is removed photoresist; The hard mask of depositing metal is as the hard mask of via etch; The spin coating bottom antireflective coating fills up groove; Return and carve bottom antireflective coating to groove; The spin coating photoresist, photoetching forms via hole image; Carry out dry etching, open metal hard mask, remove residue photoresistance and bottom antireflective coating; Carry out dry etching, form through hole; Depositing metal barrier layer and copper seed layer; Through hole and groove are filled up in electro-coppering; Carry out cmp, remove excess metal.
2. the hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic according to claim 1 is characterized in that, said first dielectric layer and said second dielectric layer all form through precipitated silica.
3. the hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic according to claim 1 is characterized in that, said dielectric barrier layer and said interlevel dielectric barrier layer all form through the deposition silicon nitride.
4. the hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic according to claim 1 is characterized in that the thickness of said second dielectric layer is more than or equal to 3 microns.
5. the hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic according to claim 1; It is characterized in that; The concrete forming process of said through hole is: after via hole image forms; Through dry etching, open metal hard mask, and remove photoresist and bottom antireflective coating; Dry etching forms through hole through the metal hard mask etching once more.
6. the hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic according to claim 5; It is characterized in that; Said dry etching; Form in the processing step of through hole, said through hole passes said first dielectric layer and said dielectric barrier layer terminates on the completed anterior layer metal level of said silicon chip.
7. according to the hard mask dual damascene process of the first trench metal that is used for ultra thick top-level metallic under the claim 1, it is characterized in that said cmp comprises the removal metal hard mask in the processing step of removal excess metal.
8. the hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic according to claim 1 is characterized in that, through dry etching, behind the formation groove, forms metal hard mask through the meteorological depositing technology of chemistry.
9. the hard mask dual damascene process of first trench metal that is used for ultra thick top-level metallic according to claim 1 is characterized in that, through dry etching, behind the formation groove, forms metal hard mask through the physical vapor depositing technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101236817A CN102420170A (en) | 2011-05-13 | 2011-05-13 | Dual damascene process for trench-first metal hard mask of super-thick top-layer metal |
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| CN2011101236817A CN102420170A (en) | 2011-05-13 | 2011-05-13 | Dual damascene process for trench-first metal hard mask of super-thick top-layer metal |
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| CN102420170A true CN102420170A (en) | 2012-04-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3076658A1 (en) * | 2018-01-05 | 2019-07-12 | Stmicroelectronics (Crolles 2) Sas | METHOD FOR ETCHING A CAVITY IN A LAYER STACK |
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| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
| CN1493087A (en) * | 2000-12-26 | 2004-04-28 | ����Τ�����ʹ�˾ | Method for eliminating reaction between photoresist and organosilicate glass (OSG) |
| CN1754251A (en) * | 2003-03-07 | 2006-03-29 | 应用材料有限公司 | Method of improving interlayer adhesion |
| US20090137118A1 (en) * | 2007-11-22 | 2009-05-28 | Renesas Technology Corp. | Method of manufacturing semiconductor device |
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2011
- 2011-05-13 CN CN2011101236817A patent/CN102420170A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1493087A (en) * | 2000-12-26 | 2004-04-28 | ����Τ�����ʹ�˾ | Method for eliminating reaction between photoresist and organosilicate glass (OSG) |
| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
| CN1754251A (en) * | 2003-03-07 | 2006-03-29 | 应用材料有限公司 | Method of improving interlayer adhesion |
| US20090137118A1 (en) * | 2007-11-22 | 2009-05-28 | Renesas Technology Corp. | Method of manufacturing semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3076658A1 (en) * | 2018-01-05 | 2019-07-12 | Stmicroelectronics (Crolles 2) Sas | METHOD FOR ETCHING A CAVITY IN A LAYER STACK |
| US10770306B2 (en) | 2018-01-05 | 2020-09-08 | Stmicroelectronics (Crolles 2) Sas | Method of etching a cavity in a stack of layers |
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Application publication date: 20120418 |