CN103681464A - Through hole and trench forming method - Google Patents
Through hole and trench forming method Download PDFInfo
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- CN103681464A CN103681464A CN201210338683.2A CN201210338683A CN103681464A CN 103681464 A CN103681464 A CN 103681464A CN 201210338683 A CN201210338683 A CN 201210338683A CN 103681464 A CN103681464 A CN 103681464A
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- hole
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- interlayer dielectric
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000010410 layer Substances 0.000 claims abstract description 74
- 239000011229 interlayer Substances 0.000 claims abstract description 67
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 50
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000001039 wet etching Methods 0.000 claims abstract description 16
- 230000008569 process Effects 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 238000000059 patterning Methods 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052802 copper Inorganic materials 0.000 abstract description 7
- 239000010949 copper Substances 0.000 abstract description 7
- 239000007769 metal material Substances 0.000 abstract description 5
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 abstract description 4
- 230000000149 penetrating effect Effects 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000008901 benefit Effects 0.000 abstract description 2
- 230000004888 barrier function Effects 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 13
- 230000000630 rising effect Effects 0.000 description 12
- 238000004380 ashing Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000003993 interaction Effects 0.000 description 3
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000019771 cognition Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a through hole and trench forming method. The method includes the following steps: a semiconductor substrate is provided, and an interlayer layer dielectric (ILD) and a patterned metal hard mask for a trench are sequentially formed on the semiconductor substrate; graphical photoresist for a through hole is formed on the ILD and the metal hard mask for partial etching of the ILD, so as to form the through hole not thoroughly penetrating the ILD; the photoresist is stripped through the wet etching method; the ILD is etched in a manner that the hard metal mask serves as a barrier, so as to form the trench and the through hole thoroughly penetrating the ILD. The invention has the advantages that the wet etching method is adopted, and an NMP (N-Methyl Pyrrolidone) solution which does not react with the ILD is used for photoresist stripping, so as to prevent the dielectric constant of the ILD from increasing, avoid a capacitance increase of an interconnection formed by subsequent deposition of a copper metal material in the through hole, further avoid a larger RC (Resistive-Capacitive) delay of the interconnection, and improve the performance of an integrated circuit.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly the through hole in a kind of semiconductor integrated circuit manufacture process and the formation method of groove.
Background technology
Along with IC(Integrated Circuit, integrated circuit) size is more and more less, and metal wire has postponed to have replaced gradually the principal element that transistor self postpones and become the restriction IC speed of service as the RC that produced between intraconnections (interconnection).The speed that in circuit, signal transmits, is the product institute left and right that is subject to resistance R and capacitor C, and RC product is larger, and speed is just slower, and delay is just higher, otherwise RC product is less, and signaling rate just can be faster, postpones just lower.For intraconnections (as copper interconnects), its resistance R is decided by himself material character, and IC internal structure is very little on the impact of its resistance R; And the capacitor C of intraconnections is mainly subject to the spacing distance between intraconnections, the impact of interval insulant.Therefore, can by modes such as the spacing distance between change intraconnections, interval insulants, reduce the capacitor C of intraconnections, to reduce the RC of intraconnections, postpone, improve the speed of service of IC.Current, there is low-resistance copper metal and be widely used in already in the manufacture of IC as intraconnections and the dielectric layer material with ultralow dielectric (ultra low-k).
Interval insulant between intraconnections, as interlayer dielectric layer (ILD, Inter Layer Dielectric), there is low dielectric constant (low k), and in order to reach the effect of better its dielectric constant of reduction, and then the electric capacity of intraconnections is further reduced, at BEOL(back end ofline, rear line, in contact(contact) involved technique afterwards) operation stage, current adopted interlayer dielectric layer also adopts the advanced low-k materials of porous (porous) mostly.
A kind of formation through hole (via) in existing manufacture interconnecting process and groove (trench) process, be to have deposited interlayer dielectric layer having comprised on the semiconductor base that is formed with semiconductor device, and on described interlayer dielectric layer, be formed with the metal hard mask (Metal Hard Mask) for the patterning of groove; At this body structure surface, form bottom anti-reflection layer (BARC afterwards, Bottom Anti Reflective Coating) and photoresist (PR) photoresist is carried out to graphical for through hole, the patterned photoresist of take carries out partial etching to described interlayer dielectric layer as mask, to form through hole, through hole does not now penetrate whole interlayer dielectric layer and arrives semiconductor base, but between through hole and semiconductor base, leaves part interlayer dielectric layer; The means stripping photoresist of using plasma ashing subsequently, (plasma ashing); Again with described metal hard mask for stopping that etching interlayer dielectric layer, to form groove, forms in the process of groove in etching, the through hole before forming is also etched simultaneously and penetrates whole interlayer dielectric layer and arrives semiconductor base, and forms final through hole.Described through hole is arranged in described groove.
As mentioned above, in existing technical process, to peeling off of photoresist, be the means of using plasma ashing.In this process, plasma cognition enters and formerly forms in through hole, in stripping photoresist, between the sidewall of plasma and through hole (sidewall), can produce and interact.For the advanced low-k materials that forms the porous of interlayer dielectric layer, interaction between plasma and the advanced low-k materials of through-hole side wall, can cause the rising of dielectric constant of the material (being also inter-level dielectric layer material) at through-hole side wall place, have influence on subsequently in through hole the electric capacity of formed intraconnections after deposited copper metal material, and then the rising that causes the RC of intraconnections to postpone.
Summary of the invention
In view of this, the invention provides a kind of formation method of through hole and groove, the rising postponing with the RC of the intraconnections avoiding forming subsequently, and then promote performance of integrated circuits.
The application's technical scheme is achieved in that
A formation method for through hole and groove, comprising:
Semiconductor base is provided, on described semiconductor base, is formed with successively interlayer dielectric layer and for the metal hard mask of the patterning of groove;
On described interlayer dielectric layer and metal hard mask, form photoresist, described photoresist is carried out to graphical for through hole, and for stopping, described interlayer dielectric layer is carried out to partial etching with patterned photoresist, to form the through hole that does not penetrate described interlayer dielectric layer completely;
Adopt wet etching method to peel off described photoresist;
With described metal hard mask, for stopping, described interlayer dielectric layer is carried out to etching, to form groove and be arranged in described groove and penetrate described interlayer dielectric layer completely and arrive the through hole of described semiconductor base.
Further, described semiconductor base comprises the semiconductor device that is formed at wafer.
Further, form photoresist on described interlayer dielectric layer and metal hard mask before, also comprise:
On described interlayer dielectric layer and metal hard mask, deposit a bottom anti-reflection layer.
Further, adopt wet etching method to peel off in described photoresist process, utilize nmp solution to carry out wet etching, to peel off described photoresist.
Further, the concentration of described nmp solution is 50 ~ 100%, and temperature is 30 ~ 100 ℃.
From such scheme, can find out, the present invention is in forming the process of through hole and groove, peeling off of photoresist adopted to a kind of method of wet etching, utilize nmp solution to peel off photoresist, between the advanced low-k materials of the porous of this nmp solution and formation interlayer dielectric layer, can not produce interaction, and then can not cause the rising of the dielectric constant of interlayer dielectric layer, and then can avoid the rising of formed intraconnections electric capacity after deposited copper metal material in through hole subsequently, and then the rising that postpones of the RC that can avoid intraconnections, promote the performance of integrated circuit.
Accompanying drawing explanation
Fig. 1 is the flow chart of the formation method of through hole of the present invention and groove;
Fig. 2 forms interlayer dielectric layer and for the structural representation after the metal hard mask of the patterning of groove on semiconductor base in the inventive method;
Fig. 3 forms the structural representation after the through hole that does not penetrate interlayer dielectric layer completely in the inventive method;
Fig. 4 adopts the structural representation after wet etching method stripping photoresist in the inventive method;
Fig. 5 is that the inventive method finally forms the structural representation after through hole and groove.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
As shown in Figure 1, the formation method of through hole of the present invention and groove comprises:
In step 3 wherein for utilizing NMP(N-methyl 2 pyrrolidones) solution carries out wet etching, to peel off described photoresist.
Below in conjunction with Fig. 2 to Fig. 5, the formation method of through hole of the present invention and groove is specifically described.
As shown in Figure 2, semiconductor substrate 1 is provided, this semiconductor base 1 has comprised that the basic semiconductor device that is formed at wafer (wafer) is as CMOS(Complementary Metal-Oxide-Semiconductor, complementary metal oxide semiconductors (CMOS)), on this semiconductor base 1, be formed with interlayer dielectric layer 2, and on interlayer dielectric layer 2, be formed with the metal hard mask (Metal Hard Mask) 3 for the patterning of groove.Interlayer dielectric layer 2 wherein can adopt the advanced low-k materials of porous (porous).The material of metal hard mask 3 can adopt titanium nitride (TiN) material etc.
As shown in Figure 3, at body structure surface shown in Fig. 2, first form bottom anti-reflection layer (BARC, Bottom Anti Reflective Coating) 4 and photoresist (PR) 5.Wherein, the effect of bottom anti-reflection layer 4 is to reduce subsequently reflection of light while exposing in graphical process.Photoresist 5 is carried out to graphical for through hole.Because formed through hole is arranged in groove, so when being prepared, before must being positioned at for the position of the opening of the photoresist 5 after through hole graphical among the opening of the formed metal hard mask 3 for groove figure.The patterned photoresist 5 of take carries out partial etching to interlayer dielectric layer 2 as mask, to form through hole 6, through hole 6 wherein does not penetrate whole interlayer dielectric layer 2 completely and arrives semiconductor base 1, but leave part interlayer dielectric layer 2 between through hole 6 and semiconductor base 1, continue this part interlayer dielectric layer 2 being left between corrosion through hole 6 and semiconductor base 1 when treating to form groove subsequently, to form the through hole 6 of arrival semiconductor base 1.
Structure after described photoresist 5 is peeled off as shown in Figure 4.In this step, utilize nmp solution to carry out wet etching to peel off described photoresist 5, the concentration of nmp solution is wherein 50 ~ 100%(mass percent concentration), temperature is 30 ~ 100 ℃, the etch period of wet method can be determined according to the thickness of photoresist 5, nmp solution concentration and nmp solution temperature, such as the thickness when photoresist 5 is
during left and right, can utilize that concentration is 100%, temperature is that the nmp solution of 65 ℃ is peeled off described photoresist 5 about 3 minutes in the time.Compare with the method for existing employing plasma ashing, in this step, while utilizing nmp solution to adopt the mode stripping photoresist 5 of wet etching, nmp solution can not produce and interact with the advanced low-k materials that forms the porous of interlayer dielectric layer 2, and then can not cause the rising of the dielectric constant of interlayer dielectric layer 2, and then can avoid the rising of formed intraconnections electric capacity after deposited copper metal material in through hole subsequently, and can avoid the rising of the RC delay of intraconnections, promote the performance of integrated circuit.
As shown in Figure 4 and Figure 5, because be, using described metal hard mask 3, as stopping, described interlayer dielectric layer 2 is carried out to etching, and before this step, in described interlayer dielectric layer 2, be formed with the through hole 6 that does not penetrate whole interlayer dielectric layer 2 completely, so this step is being carried out in the process of etching described interlayer dielectric layer 2, when interlayer dielectric layer 2 outside the through hole 6 in not penetrating whole interlayer dielectric layer 2 completely and that do not covered by metal hard mask 3 is being etched to form groove 7, in not penetrating the interlayer dielectric layer 2 of bottom of the through hole 6 of whole interlayer dielectric layer 2 completely, be also etched simultaneously, and then along with the carrying out of this step etching, make the described through hole whole interlayer dielectric layer 2 of 6 break-through and arrive base semiconductor substrate 1, and then complete the etching of through hole 6.The etching process of this step can adopt existing method to carry out as dry etching method.
The technical process and the technological parameter (as etching process of the deposition process of the forming process of semiconductor base, interlayer dielectric layer, through hole and groove etc.) that in the present invention, do not add detailed description, those skilled in the art all can realize according to the experiment of prior art and limited number of time, repeat no more herein.
Said method is in forming the process of through hole 6 and groove 7, peeling off of photoresist 5 adopted to the method for wet etching, utilize nmp solution to peel off photoresist 5, between the advanced low-k materials of the porous of this nmp solution and formation interlayer dielectric layer 2, can not produce interaction, and then can not cause the rising of the dielectric constant of interlayer dielectric layer 2, and then can avoid the rising of formed intraconnections electric capacity after deposited copper metal material in through hole 6 subsequently, and then the rising that postpones of the RC that can avoid intraconnections, promote the performance of integrated circuit.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (5)
1. a formation method for through hole and groove, comprising:
Semiconductor base is provided, on described semiconductor base, is formed with successively interlayer dielectric layer and for the metal hard mask of the patterning of groove;
On described interlayer dielectric layer and metal hard mask, form photoresist, described photoresist is carried out to graphical for through hole, and for stopping, described interlayer dielectric layer is carried out to partial etching with patterned photoresist, to form the through hole that does not penetrate described interlayer dielectric layer completely;
Adopt wet etching method to peel off described photoresist;
With described metal hard mask, for stopping, described interlayer dielectric layer is carried out to etching, to form groove and be arranged in described groove and penetrate described interlayer dielectric layer completely and arrive the through hole of described semiconductor base.
2. the formation method of through hole according to claim 1 and groove, is characterized in that: described semiconductor base comprises the semiconductor device that is formed at wafer.
3. the formation method of through hole according to claim 1 and groove, is characterized in that, before forming photoresist, also comprises on described interlayer dielectric layer and metal hard mask:
On described interlayer dielectric layer and metal hard mask, deposit a bottom anti-reflection layer.
4. according to the formation method of the through hole described in claims 1 to 3 any one and groove, it is characterized in that: adopt wet etching method to peel off in described photoresist process, utilize nmp solution to carry out wet etching, to peel off described photoresist.
5. the formation method of through hole according to claim 4 and groove, is characterized in that: the concentration of described nmp solution is 50 ~ 100%, and temperature is 30 ~ 100 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210338683.2A CN103681464A (en) | 2012-09-13 | 2012-09-13 | Through hole and trench forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210338683.2A CN103681464A (en) | 2012-09-13 | 2012-09-13 | Through hole and trench forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103681464A true CN103681464A (en) | 2014-03-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210338683.2A Pending CN103681464A (en) | 2012-09-13 | 2012-09-13 | Through hole and trench forming method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5853962A (en) * | 1996-10-04 | 1998-12-29 | Eco-Snow Systems, Inc. | Photoresist and redeposition removal using carbon dioxide jet spray |
| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
| CN1901156A (en) * | 2005-07-19 | 2007-01-24 | 联华电子股份有限公司 | Method for producing double embedded structure |
-
2012
- 2012-09-13 CN CN201210338683.2A patent/CN103681464A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5853962A (en) * | 1996-10-04 | 1998-12-29 | Eco-Snow Systems, Inc. | Photoresist and redeposition removal using carbon dioxide jet spray |
| CN1433062A (en) * | 2002-01-10 | 2003-07-30 | 联华电子股份有限公司 | Method of forming opening in low dielectric constant material |
| CN1901156A (en) * | 2005-07-19 | 2007-01-24 | 联华电子股份有限公司 | Method for producing double embedded structure |
Non-Patent Citations (1)
| Title |
|---|
| Q.T.LE等: ""Removal of post-etch photoresist and sidewall residues using organic solvent and additive combined with physical forces"", 《MICROELECTRONIC ENGINEERING》 * |
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