TW441003B - Structure of dielectric layer and method for making the same - Google Patents

Abstract

The present invention provides a structure of a dielectric layer and a method for making the same. The structure of the dielectric layer comprises a silicon oxide installed between two adjacent metal wires on a semiconductor chip. The two adjacent metal wires are formed by a dual damascene process. The structure of the dielectric layer according to the present invention comprises at least a trench installed on the surface of the dielectric layer, an insulation layer installed in the trench, and at least a void formed in the trench by using the insulation layer, in which the void is used to reduce the effective dielectric constant of the dielectric layer and the parasitic capacitance between the adjacent metal wires.

Description

441 0 U 3 i V. Description of the invention (l) The field of invention of i, i:! J! I The present invention provides a structure of a dielectric layer, in particular a method that can reduce the parasitic capacitance between metal and wires. Dielectric layer structure. … 丨!! 4 Scene Descriptions |

i II |! With the continuous reduction in the size of semiconductor components and the continuous increase in the density of the product circuit, the time delay (RC time ί: de 1 ay) between the metal wires has seriously affected the integrated circuit Operating efficiency, especially when the production | 丨 the line width (line width) is reduced to 0.25 microns' or even 0.1 5 microns or less!丨 The impact of time delay will be more obvious during semiconductor manufacturing.丨!

I Because the time delay between the metal interconnects is the product of the product of the resistance (R) of the metal wire | 丨 and the parasitic capacitance (c) of the dielectric layer between the metal wires. Therefore, to reduce the time caused by the metal interconnects of semiconductor wafers | i delay has two methods: the first method is to use a metal with a low resistance value | i is a metal wire 'the second method is to reduce the metal | Of the dielectric layer between the wires, parasitic capacitance.丨 ^ |.!;! I Therefore, the current use of aluminum-copper alloy (A 丨: Cu (0_ 5%)) as the main material | ΐΐ Multilevel metallizati〇n Process 6 丨 丨 Gradually unable to meet very large Integrated circuit Ultra large scale

441003 丨 V. Description of the invention (2) j: Design rule for I integrated circuits, ULSi circuits, ji (design rule), replaced by copper with pure copper as the wire material 丨 copper interconnect technology » Copper i itself has a lower resistivity (1 · 67 舡 Ω-cm) and can carry a higher current density of j I without causing electromigration of aluminum-copper alloy (electro!

Migration), so it can reduce the parasitic capacitance between the metal wires and the number of connection layers β of the metal wires. However, the copper connection technology alone is still not available. There are also some process problems in copper connection and 1-junction technology that need to be resolved. ί: i I Η The second method is to reduce the parasitic capacitance of the dielectric layer between the metal wires. Due to the parasitic capacitance of the dielectric layer and the dielectric constant of the dielectric layer

I (dielectric constant) is related, so the lower the dielectric constant of the dielectric layer; the lower the parasitic capacitance formed in the dielectric layer is, the lower is. Although there are currently some low-dielectric constant materials, such as polyimide (PI), HSQ (hydrogen silsesquioxane), etc., are used as inter-metal dielectric layer (inter-metal dielectric layer) , IMD layer), but most of these low dielectric constant materials have the disadvantages of poor adhesion and insufficient thermal stability. |: r j j

丨 Summary of the invention I ^! The main purpose of the present invention is to provide a method capable of reducing

Page 5 -441003 丨 V. Description of the invention (3)! The dielectric layer structure of the capacitor. j 丨 The present invention provides a structure of a dielectric layer. The dielectric layer structure is made of silicon oxide, and is located between two adjacent metal wires on a semiconductor chip. The two adjacent gold wires are made of a double entry (dual damascene) process. The || invented dielectric layer structure includes at least one trench provided on the dielectric | i-layer surface, 'an insulating layer provided in the trench', and at least one hole (v oid) formed using the insulating layer ) Is formed in the trench. The hole system | 丨 is used to reduce the effective dielectric constant of the dielectric layer and the parasitic capacitance 1 between the adjacent metal wires.

I The dielectric layer structure of the present invention has at least one trench having an aspect ratio greater than 3.5, and at least one hole is formed in the trench. Because the dielectric constant of: 1 contained in the hole is smaller than the dielectric constant of the dielectric layer, it can effectively reduce the effective dielectric constant of the dielectric layer between two adjacent metal wires ’, thereby reducing |

i low the parasitic capacitance between two adjacent metal wires and the time delay of I; caused by the parasitic capacitance. I | 丨 Detailed description of the invention 1 i i i j I Please refer to FIGS. 1 to 8. FIGS. 1 to 8 are fabricated on a semiconductor crystal and a dielectric layer capable of reducing parasitic capacitance between metal wires 92 and 92 and 93 is formed.

Page 6 441003 I. V. Description of the invention (4) | The semiconductor wafer 40 includes a silicon substrate (not shown), a dielectric layer 52 covers the surface of the silicon substrate, a plurality of metal conductive lines 61 are provided on the surface of the dielectric layer 52, and a silicon nitride layer 54 is covered on The dielectric layer 52 丨 and the surface of the plurality of metal wires 61, a stacked dielectric layer | 6 2 covers the silicon nitride layer 5 4. i

I; The dielectric layer 52 is formed by depositing silicon dioxide on the surface of the semiconductor wafer 40 with a plasma-enhanced chemical vapor deposition (PECVD) process. In addition, the dielectric layer 52 may also be composed of phosphosilicate glass (ipSG) or borophosphosi 1 i cate glass (BPSG) 1.

I

I! The metal wire 61 is made of copper or aluminum-copper alloy. The method of forming the metal wire 1 61 is to use a traditional yellow light process and an: anisotropic dry etching process before the dielectric: the electrical layer 5 2 defines the surface of the metal wire 61 The trench pattern is followed by a copper electro-deposition technique (Cu electro-deposition; technology) to deposit a copper metal layer on the surface of the dielectric layer 52 and the trench pattern. Finally, a chemical mechanical polishing (chemical mechanical ^ 〇1 丨 311 丨 1 ^, 〇 || 1?) Process is performed to complete the embedded copper metal wire 61 whose surface is approximately flush with the surface of the dielectric layer 52. Because copper ions (cupric ions) can easily expand in Shixi and Shijixi 441003 I. 5. Description of the invention (5) | scattered 'and copper is prone to oxidation, so after the completion of I A chemical vapor phase / CVD method is used on the surfaces of the metal wires 61 and the dielectric layer 52 to form a nitrided second layer 54 as a passivation layer. In addition, 'copper ions are less likely to diffuse into the dense silicon nitride layer 54 |', so the broken nitride layer 54 can effectively block the diffusion of copper ions. However, the high dielectric constant silicon nitride layer 5 4 will also increase the parasitic capacitance between the metal layers, so the silicon nitride layer should not be too thick.丨:!

. I

II! As shown in Figure 1, 'The surface of the stacked dielectric layer 62 has been pre-defined by the traditional yellow light process in the photoresist layer 4 2 to define the position of the via hole | i63, 6 4 and the position of the trench 7 and the stacked dielectric layer 6 2 has a similar | II Meiji structure (oxide-nitride-oxide, 0N0 structure),

i is an inter_metal ^ dielectric layer 'IMD Uyer structure commonly used in the copper-metal double entry process, which includes a silicon oxide layer 56 having a thickness of about 7000, and an etching of about 300 each. The stop layer 5 8 covers the Shi Xi oxide layer 56, and a dielectric layer 60 with a thickness of about 5000 Å is formed by the Shi Xi oxide j (silicon oxide); the etch stop layer 5 8 Above. Silicon oxide layer 5 6. Etch stop; 5 I dielectric layer 6. Both can be used conventional chemical vapor deposition (CVD ^ V ^ 58 and I;! I as shown in Figure 2) and then a dry etching process is used, using the photoresist layer 42 and the surface of the etching stop layer 58 as hard The mask (hard ^ 4) uses I and the end-point of the dry etching to transfer the pattern in the photoresist layer 42 into the dielectric layer 60. A dielectric layer will be formed on the surface of the dielectric layer 60 Figure of window

441003 i V. Description of the Invention (6) Cases 65 and 66, and a plurality of trenches 72 with aspect ratios greater than 3,5. The positions of the patterns 65 and 66 of the interlayer window are approximately above the metal wires 61. Next, a series of cleaning and drying procedures are performed on the surface of the semiconductor wafer 40 to remove the fine particles I and organic pollutants remaining on the surface of the semiconductor wafer 40 in the dry etching process. As shown in FIG. 3, a chemical vapor deposition method is subsequently performed to uniformly deposit an insulating layer 82 on the surface of the dielectric layer 60 and the dielectric window patterns 65, 66 and the trenches 172. The insulating layer 82 is made of a low-dielectric constant materials > such as silicon dioxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and fluorinated dioxide. It is composed of fluorinated silicon dioxide (FxSiOy), parylene, Teflon, or “amorphous carbon (aC: F)”. Due to the high height of the trench 72 The aspect ratio is greater than 3.5, so when performing a chemical vapor deposition process, using the process parameters of the chemical vapor deposition process to adjust the thickness of the film and the thickness of the film can produce an insulating layer with poor step coverage. || Further, overhangs (overver) are formed on the corners of the dielectric layer 60 near the opening of the trench 72 (coverner), and the opening of the trench 72 is closed to form a hole 73 in the trench 72 i. As shown in FIG. As shown in FIG. 4, a series of cleaning procedures are performed on the surface of the semiconductor i-chip 40 using an RCA standard cleaning solution, and the surface of the semiconductor wafer 40 is dried by using a dehydration step. Then, the surface is dried.

f 441 0 03 V. Description of the invention (7) A photoresist coating process' forms a positive (P-type) photoresist layer 44 on the surface of the semiconductor wafer 40. Wherein, after coating the photoresist layer 44, the semiconductor wafer 40 needs to go through a soft bake step of about 90 seconds to 90 ° to remove the solvent in the photoresist layer 44. Then, A yellow light process is used to define the trench pattern 43 of the metal wire in the photoresist layer 44. | As shown in Figure 5, 'Through fluoroforra (CHF 3) as the main | j reactive gas' for reactive ions The reactive ion etching (jRIE) process 'removes the insulating layer 82 and the dielectric layer 6 0' that are not covered by the photoresist layer 44 down to the surface of the etching stop layer 5 8 to remove the photoresist layer 4 4 The metal i-conductor trench pattern 43 is transferred to the dielectric layer 60, and at the same time, the trench pattern 67, 68, 69 of the metal conductive line is formed in the dielectric layer 60. The dielectric layer pattern originally formed in the dielectric layer; 60 65, 6 and 6 were transferred to Shi Xi in this dry process | the oxide layer 56 'and exposed the surface of the metal wire 61. Finally, the photoresist was peeled off in an oxygen plasma. (Ph〇t〇resist stripping) process to remove the photoresist layer 44. I Because of the intermediary in the process of double embedded copper connection line Layer window engraving and photoresistation 丨 In the peeling process, 'If the dry money engraving does not stop on the surface of the nitride layer 5 4 and etch directly to the surface of the metal wire 6 1', it will cause the copper metal wire 6 1 at the bottom I was sputtered to the side wall of the interlayer window to produce copper fluoride (cupric nuoride, CuF 2) and copper oxide (cupr oxi de, CuO) and other copper particles contaminated. I and subsequent photoresist removal The oxygen plasma used in the process will also oxidize the surface of copper | metal wires to copper oxide ', which greatly increases the contact resistance. Therefore,

Page 10 ^ 41〇〇3 I. Description of the invention (8) i The method of the present invention is to adjust the appropriate etching selection ratio, and the etching is stopped first. The layer 5 8 and the silicon oxide layer 5 6 are up to the silicon nitride layer. 5 4 surface. Next, a photoresist removal process and a post-etching cleaning step are performed to remove the photoresist layer 44 and high-resistance sub-residues. Finally, a soft etch is used to remove the nitrogen fragmentation layer 54 ′ at the bottom of the via window Transfer of the mesas pattern 65, 66. i As shown in FIG. 6, a copper metal layer 84 is deposited. As mentioned earlier, because copper easily diffuses in silicon or silicon dioxide, and the adhesion between copper and I | Shi Xi oxide layer 56 is not good, a metal barrier must be deposited before depositing a copper metal layer. Layer 90. The metal barrier layer 90 must have good diffusion j | barrier characteristics' and the metal barrier layer 90 and the silicon oxide layer 56 and the copper metal! Layer 8 4 must also have better adhesion. Currently, the materials commonly used as the barrier layer 90 are group metals (tantalum, a) or nitride group (tantalum nitride) (TaN). The tantalum barrier layer 90 is formed by a chemical vapor deposition method. The deposition reaction uses five gasification giants (TaC 15) and argon as the reaction gas. The reaction temperature is higher than 700C. A copper seed layer physical vapor deposition (PVD) process is subsequently performed to form a copper seed layer (not shown) on the surface of the barrier layer 90i, and then a wet copper is used. The electroplating and deposition process is used to deposit a copper metal layer 84 on the surface of the copper seed layer and completely fill the metal wire trench patterns 67, 68, 69 and the interlayer window patterns 65, | | 66. In the process of electroplating copper, the effect of bottom-up fill can be achieved by adding chemicals.

44 彳 Ο Ο 3 j V. Description of the invention (9) ~~~~ ———— ~~ 一-一 ^-一 ~ ^ 'TO j

丨 ’Make the copper at the bottom of the layer window higher than the copper deposition rate on the side wall. I I allows copper to selectively fill up the interlayer window and the trenches without causing i

j void or seam. I

II. As shown in FIG. 7, a surface planarization process, such as a CMP process, is then performed to form copper metal wires 91, 67, 68, 69 in the metal wire trench patterns 67, 66, and 66, 66, 66. 92, 93 and copper metal plugs 94, | 丨 95. j!

I The CMP process of the dual-embedding process of general steel connecting lines will encounter two problems: (1) the copper metal layer 8 4 is softer, so micro-scratch and shallow dish will be more like a dish. Severe; (2) There is a large difference in the grinding rate between the copper metal layer 84 and the barrier layer 90, which further aggravates the shallow dish phenomenon, and even leads to the surface of copper metal wires 9 and 92, 93. Erosion occurred. However, the method of the present invention can effectively solve the conventional problem β 1 because when the CMP process of the copper metal layer 8 4 is performed, we can increase the thickness of the insulating layer j 2 as a sacrificial layer, and further The copper metal layer 84 above the insulating layer | 丨: 8 2 is completely removed to greatly improve the shallow dishing phenomenon on the metal wires 91, 92, 9 3 ^ 丨 丨. II Finally, the first CMP process is performed 'as shown in Figure 8', removing the insulating layer 82 located above the dielectric layer 60 to complete the planarization of the steel connection process. I and metal wires 9 1, 9 Dielectric layer 60 structure between 2, 9 and 3.

'4 41 0 0 3 丨 V. Description of the invention (10)! 1 Due to the metal wires 9b 92, 9 formed by the dual-embedding process, the dielectric layer 60 between i is made of silicon with a low dielectric constant. Made of oxide, and the i dielectric layer 60 includes at least one trench 72 2 filled with an insulating layer 8 2, and at least one trench 73 formed using the insulating layer 8 2 is provided in the trench 72, | 丨Therefore, the effective dielectric constant of the dielectric layer 60 (effective! {Dielectric constant) can be greatly reduced, thereby reducing the interval between the metal wires 91, 92, and 93 丨

丨 parasitic capacitance. That is, the present invention first uses the trench 72 having an aspect ratio greater than 3.5 i to form the hole 73, and then the principle that the dielectric constant of the air contained in the hole 73 must be smaller than that of the dielectric layer 60 'Effective II | i reduces the effective dielectric constant between adjacent metal wires 9b 9 2, 9 3, to achieve! The purpose of reducing parasitic capacitance and time delay between adjacent metal wires 9b 9 2, 9 3 丨.

I

I | In the above-disclosed embodiment, I used the via-first dual-embedding process to make a detailed description, but the dielectric layer of the present invention: the structure can be applied to various dual-embedding processes. Metal wire (metal wire) * I can even be extended to the dielectric i | layer structure between any two adjacent conductors on a semiconductor wafer.丨

1 I ί!! J! I Compared with the conventional method to reduce the time delay between the metal interconnects, the present invention not only provides a dielectric that can reduce the parasitic capacitance j | between the metal wires 91, 92, and 93 The layer 60 structure and the manufacturing method thereof, and simultaneously solve the manufacturing problem of the dual-embedding process of the copper connection line.

: V. Description of the invention (11) | The above description is only a preferred embodiment of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the invention patent.

Page 14 441003 Brief description of the diagrams Brief description of the diagrams Figures 1 to 8 are schematic diagrams of the dielectric layer manufacturing process of the present invention. 0 Symbol descriptions 40 Semiconductor wafer 42 Photoresist layer 43 Channel pattern of metal wires 44 Photoresist layer 52 Dielectric layer 54 Silicon nitride layer 56 Silicon oxide layer 58 Carved stop layer 60 Dielectric layer 61 Metal wire 62 Stacked dielectric layer 63 Interlayer window position 64 Interlayer window position 65 Interlayer window pattern 66 Interlayer Window pattern 67 '68' 69 Metal wire trench pattern 71 Trench position 72 Trench 73 Hole 82 Insulation layer 90 Metal barrier layer 91 '92' 93 Copper metal wire 94, 95 Copper metal plug

Claims (1)

AA] 0 0 3 丨 VI. Patent scope! 1. A dielectric layer structure provided between two adjacent conductors j on a semiconductor wafer, including: | at least one trench ( trench) is provided on the surface of the dielectric layer; 1 an insulating layer is provided in the trench; and 1 at least one hole (v〇id) formed by using the insulating layer is provided in the trench;! wherein the hole is used for To reduce the effective dielectric constant I (effective dielectric constani;) 0 i of the dielectric layer; 2. For example, the dielectric layer structure of the first patent application range, wherein the dielectric layer | has an approximately flat surface, And the surface of the dielectric layer is approximately flush with the top surface of each of the! Conductors. 3. The dielectric layer structure according to item 2 of the patent application scope, wherein the dielectric layer 丨 is composed of silicon oxide (s i I i c ο η ο X i d e). Introduce the structure layer 0 of the electric current} 6 mediation Γ i of the W item 1 11a e e C Fan Lili exclusive guidance, please apply for Jinshenyi as the 4th body; 5. As for the 4th scope of the scope of patent application The dielectric layer structure, wherein the metal conductive line is formed by a dual damascene process. j 六 、 Application scope of patent ί II 7 · If the dielectric layer structure of the first scope of patent application, the insulating layer | is composed of a low-dielectric constant 丨 materials, ί | 8 'As in the dielectric layer structure of the 7th scope of the patent application, wherein the low dielectric constant material includes a dream of dioxide, phosphosilicate (g 1 ass, PSG), borophosphos i 1 i cate g 1 ass, j jBPSG) 'fiUQrinated silicon dioxide (FJiOy), paryiene, Teflon, or fluorocarbon (Amorphous carbon, aC: F). :; 9 · A dielectric layer structure provided between two adjacent metal wires (metal | wi re) on a semiconductor wafer, the metal wires are formed by a double embedding process: forming 'the dielectric layer contains a plurality of A void is used to reduce the parasitic capacitance between the two metal wires. ； I!] | 10 · If the dielectric layer structure of the patent application scope item 9, where the dielectric layer i is composed of silicon oxide "•! I!!; 11_ If the patent application scope item 9 The dielectric layer structure, wherein the dielectric layer | 丨 further includes a plurality of trenches having an aspect ratio greater than 3.5, and the plurality of holes i are formed in the plurality of trenches. Page 17i VI. Patent application scope I il2. The dielectric layer structure of item 11 of the patent application scope 'wherein the complex is formed | The method of forming several holes includes the following steps: | I perform a chemical vapor deposition (Chemical vapor deposition, CVD) | 丨 a process for depositing an insulating layer on the surfaces of the plurality of trenches; | | wherein the insulating layer forms overhangs at the openings of the plurality of trenches and closes the plurality of trenches Open up to form the holes!丨 hole.丨 I i; 1 3 • If the dielectric layer structure of item i 2 of the patent application scope, wherein the insulating layer 丨 is composed of a low dielectric constant material i ^ 4 · As described in the patent application scope of item 13 Electrical layer structure, where the low-dielectric constant material system includes silicon dioxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorine-containing silicon dioxide (FxSi〇y), Toluene polymer (parylene), Teflon, or fluorocarbon UC: F). Page 18