CN1260804C - 半导体晶片及其制造方法以及半导体器件及其制造方法 - Google Patents

半导体晶片及其制造方法以及半导体器件及其制造方法 Download PDF

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Publication number
CN1260804C
CN1260804C CNB021180431A CN02118043A CN1260804C CN 1260804 C CN1260804 C CN 1260804C CN B021180431 A CNB021180431 A CN B021180431A CN 02118043 A CN02118043 A CN 02118043A CN 1260804 C CN1260804 C CN 1260804C
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China
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mentioned
region
semiconductor substrate
semiconductor
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Expired - Fee Related
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CNB021180431A
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English (en)
Chinese (zh)
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CN1379464A (zh
Inventor
江头克
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Toshiba Corp
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Toshiba Corp
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Publication of CN1379464A publication Critical patent/CN1379464A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
CNB021180431A 2001-03-30 2002-03-29 半导体晶片及其制造方法以及半导体器件及其制造方法 Expired - Fee Related CN1260804C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001101514A JP2002299591A (ja) 2001-03-30 2001-03-30 半導体装置
JP101514/2001 2001-03-30

Publications (2)

Publication Number Publication Date
CN1379464A CN1379464A (zh) 2002-11-13
CN1260804C true CN1260804C (zh) 2006-06-21

Family

ID=18954811

Family Applications (1)

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CNB021180431A Expired - Fee Related CN1260804C (zh) 2001-03-30 2002-03-29 半导体晶片及其制造方法以及半导体器件及其制造方法

Country Status (6)

Country Link
US (1) US6593627B2 (https=)
EP (1) EP1246248A3 (https=)
JP (1) JP2002299591A (https=)
KR (1) KR100579780B1 (https=)
CN (1) CN1260804C (https=)
TW (1) TW533554B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102986011A (zh) * 2010-08-12 2013-03-20 富士电机株式会社 半导体器件的制造方法

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW536802B (en) * 2002-04-22 2003-06-11 United Microelectronics Corp Structure and fabrication method of electrostatic discharge protection circuit
FR2847077B1 (fr) * 2002-11-12 2006-02-17 Soitec Silicon On Insulator Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation
US6815714B1 (en) 2003-02-20 2004-11-09 National Semiconductor Corporation Conductive structure in a semiconductor material
US6812486B1 (en) * 2003-02-20 2004-11-02 National Semiconductor Corporation Conductive structure and method of forming the structure
DE102004005506B4 (de) 2004-01-30 2009-11-19 Atmel Automotive Gmbh Verfahren zur Erzeugung von aktiven Halbleiterschichten verschiedener Dicke in einem SOI-Wafer
DE102004005951B4 (de) * 2004-02-02 2005-12-29 Atmel Germany Gmbh Verfahren zur Herstellung von vertikal isolierten Bauelementen auf SOI-Material unterschiedlicher Dicke
JP2006041422A (ja) 2004-07-30 2006-02-09 Seiko Epson Corp 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法
JP2006073627A (ja) * 2004-08-31 2006-03-16 Toshiba Corp 半導体集積装置
US7141457B2 (en) * 2004-11-18 2006-11-28 International Business Machines Corporation Method to form Si-containing SOI and underlying substrate with different orientations
JP2006156867A (ja) 2004-12-01 2006-06-15 Seiko Epson Corp 半導体基板の製造方法および半導体装置の製造方法
FR2881273B1 (fr) * 2005-01-21 2007-05-04 St Microelectronics Sa Procede de formation d'un substrat semi-conducteur de circuit integre
JP2006253181A (ja) 2005-03-08 2006-09-21 Seiko Epson Corp 半導体装置および半導体装置の製造方法
JP4293193B2 (ja) 2005-03-09 2009-07-08 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
JP2006278632A (ja) 2005-03-29 2006-10-12 Seiko Epson Corp 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法
JP4029885B2 (ja) 2005-03-29 2008-01-09 セイコーエプソン株式会社 半導体装置の製造方法
JP2007027231A (ja) 2005-07-13 2007-02-01 Seiko Epson Corp 半導体装置の製造方法及び、半導体装置
US7459367B2 (en) * 2005-07-27 2008-12-02 International Business Machines Corporation Method of forming a vertical P-N junction device
JP4940797B2 (ja) 2005-10-03 2012-05-30 セイコーエプソン株式会社 半導体装置の製造方法
JP5130621B2 (ja) * 2005-11-24 2013-01-30 ソニー株式会社 半導体基板の製造方法
JP2007165676A (ja) 2005-12-15 2007-06-28 Seiko Epson Corp 半導体基板の製造方法及び半導体装置
JP2007194315A (ja) 2006-01-18 2007-08-02 Seiko Epson Corp 半導体装置および半導体装置の製造方法
US7666721B2 (en) 2006-03-15 2010-02-23 International Business Machines Corporation SOI substrates and SOI devices, and methods for forming the same
US7285480B1 (en) * 2006-04-07 2007-10-23 International Business Machines Corporation Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof
US7812367B2 (en) * 2008-10-15 2010-10-12 Semiconductor Components Industries, Llc Two terminal low capacitance multi-channel ESD device
JP2010141244A (ja) * 2008-12-15 2010-06-24 Mitsumi Electric Co Ltd 半導体装置
KR20130017914A (ko) 2011-08-12 2013-02-20 삼성전자주식회사 광전 집적회로 기판 및 그 제조방법
DE112012000210T5 (de) * 2012-02-23 2014-01-16 Fuji Electric Co., Ltd Verfahren zur Herstellung eines Halbleiterbauelements
JP6034268B2 (ja) * 2013-09-13 2016-11-30 株式会社東芝 半導体装置
JP6173988B2 (ja) * 2014-08-28 2017-08-02 株式会社ジャパンディスプレイ 電極基板の製造方法、電極基板、表示装置および入力装置
EP3742476B1 (en) * 2019-05-20 2024-11-06 Infineon Technologies AG Method of implanting an implant species into a substrate at different depths
CN111554186B (zh) * 2020-04-29 2022-05-17 昆山国显光电有限公司 离型层结构和显示面板的制备方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5102809A (en) * 1990-10-11 1992-04-07 Texas Instruments Incorporated SOI BICMOS process
JPH0685177A (ja) * 1992-08-31 1994-03-25 Hitachi Ltd 半導体集積回路装置
JP3191835B2 (ja) * 1993-05-17 2001-07-23 住友電気工業株式会社 光電子集積回路
US5364800A (en) * 1993-06-24 1994-11-15 Texas Instruments Incorporated Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate
JP3139904B2 (ja) * 1993-12-28 2001-03-05 新日本製鐵株式会社 半導体基板の製造方法および製造装置
JP2806286B2 (ja) * 1995-02-07 1998-09-30 日本電気株式会社 半導体装置
US5828112A (en) * 1995-09-18 1998-10-27 Kabushiki Kaisha Toshiba Semiconductor device incorporating an output element having a current-detecting section
US5708287A (en) * 1995-11-29 1998-01-13 Kabushiki Kaisha Toshiba Power semiconductor device having an active layer
JPH11163125A (ja) * 1997-12-01 1999-06-18 Hitachi Ltd Ｓｏｉ基板及びｓｏｉ基板の製造方法
JP2000164881A (ja) * 1998-11-30 2000-06-16 Seiko Instruments Inc 半導体装置とその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102986011A (zh) * 2010-08-12 2013-03-20 富士电机株式会社 半导体器件的制造方法

Also Published As

Publication number Publication date
EP1246248A3 (en) 2003-12-10
KR100579780B1 (ko) 2006-05-15
CN1379464A (zh) 2002-11-13
TW533554B (en) 2003-05-21
KR20020077158A (ko) 2002-10-11
US20020142507A1 (en) 2002-10-03
EP1246248A2 (en) 2002-10-02
US6593627B2 (en) 2003-07-15
JP2002299591A (ja) 2002-10-11

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