CN1832174A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN1832174A
CN1832174A CNA2006100041223A CN200610004122A CN1832174A CN 1832174 A CN1832174 A CN 1832174A CN A2006100041223 A CNA2006100041223 A CN A2006100041223A CN 200610004122 A CN200610004122 A CN 200610004122A CN 1832174 A CN1832174 A CN 1832174A
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CN100479163C (zh
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神田良
菊地修一
大竹诚治
畑博嗣
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Sanyo Electric Co Ltd
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Abstract

一种半导体装置，在现有的半导体装置中，存在为保护元件不受过电压影响而设置的N型扩散区域窄，击穿电流集中，保护用PN结区域被破坏的问题。在本发明的半导体装置中，在衬底(2)和外延层(3)上形成有P型埋入扩散层(4)。N型埋入扩散层(5)与P型埋入扩散层(4)重叠形成，且在元件形成区域的下方形成有过电压保护用的PN结区域(19)。PN结区域(19)的击穿电压比源－漏极间的击穿电压低。根据该结构，可防止击穿电流集中在PN结区域(19)，且可由过电压保护半导体元件。

Description

半导体装置
技术领域
本发明涉及保护电流元件不受过电压影响的半导体装置。
背景技术
在现有的半导体装置中，例如为形成N沟道型LDMOS晶体管，而在P型半导体衬底上堆积N型外延层。在外延层上形成有作为反向栅极区域使用的P型扩散区域。在P型扩散区域上形成有作为源极区域使用的N型扩散区域。另外，在外延层上形成有作为源极区域使用的N型扩散区域。而且，在位于漏极区域下方的半导体衬底和外延层上形成有N型埋入区域。此时，使由埋入区域和半导体衬底形成的PN结区域的击穿电压比LDMOS晶体管的源-漏极间的击穿电压低。根据该结构，即使在破坏LDMOS晶体管的过电压施加在漏极电极上的情况下，由埋入区域和半导体衬底形成的PN结区域也会被击穿。其结果是，可由上述过电压防止LDMOS晶体管被破坏(例如参照专利文献1)。
专利文献1：特表平10-506503号公报(第4-5、7页，第1-2图)
如上所述，在现有的半导体装置中，为了由施加在漏极区域上的过电压防止LDMOS晶体管被破坏，而在漏极区域下方形成有N型埋入区域。N型埋入区域具有与漏极区域的宽度大致相同的宽度。根据该结构，当过电压施加在漏极区域上，且N型埋入区域和P型半导体衬底的PN结区域击穿时，击穿电流集中在PN结区域。因此，存在PN结区域由电流集中的问题及该集中造成的热破坏的问题。
另外，在现有的半导体装置中，为防止在上述PN结区域的电流集中，也可以通过在宽的区域形成N型埋入区域来应对。在此，在现有的半导体装置中，以使用已知的RESURF原理提高元件的耐压特性为目的。因此，N型埋入区域在分离区域侧形成得较大。另一方面，N型埋入区域是为形成PN结区域而追加在LDMOS晶体管上的结构。即，当在宽阔的范围形成N型埋入区域时，漏极区域和分离区域之间增宽，未形成元件的无效区域增宽。因此，存在不能有效地相对芯片尺寸配置元件形成区域的问题。
发明内容
本发明是鉴于上述各问题而构成的，本发明提供半导体装置，在半导体衬底上堆积多层外延层，并将所述外延层作为半导体元件的形成区域使用，其特征在于，在所述半导体元件的形成区域下方形成一导电类型埋入扩散层和导出到所述一导电类型埋入扩散层上的反导电类型埋入扩散层，所述一导电类型埋入扩散层和所述反导电类型埋入扩散层的第一接合区域的击穿电压比形成于所述半导体元件的电流经路中的第二接合区域的击穿电压低。因此，在本发明中，当对半导体元件施加过电压时，第一接合区域比第二接合区域先被击穿。根据该结构，可防止因施加过电压而使半导体元件破坏。
另外，本发明提供半导体装置，其特征在于，所述反导电类型埋入扩散层将反导电类型第一埋入扩散层和反导电类型第二埋入扩散层连接形成，其中，第一埋入扩散层将所述一导电类型埋入扩散层和其形成区域重叠形成，第二埋入扩散层形成于所述一导电类型埋入扩散层的上方。因此，在本发明中，由一导电类型埋入扩散层和反导电类型第一埋入扩散层形成第一接合区域。根据该结构，容易地将第一接合区域的击穿电压调整为所希望的范围。
本发明提供半导体装置，其特征在于，所述半导体元件为NPN晶体管、PNP晶体管、N沟道型MOS晶体管、P沟道型MOS晶体管。因此，在本发明中，可相对形成于半导体元件形成区域的任意半导体元件实现过电压保护结构。
另外，本发明提供半导体装置，其特征在于，具有：一导电类型半导体衬底；反导电类型第一外延层，其形成于所述半导体衬底上；一导电类型埋入扩散层，其形成于所述半导体衬底和所述第一外延层上；反导电类型第一埋入扩散层，其形成于所述半导体衬底和所述第一外延层上，将所述一导电类型埋入扩散层和其形成区域重叠形成；反导电类型第二外延层，其形成于所述一导电类型埋入扩散层和所述反导电类型第一埋入扩散层的第一接合区域、和形成于所述第一外延层上；反导电类型第二埋入扩散层，其形成于所述第一及第二外延层上，与所述第一埋入扩散层连接；半导体元件，其形成于所述第二埋入扩散层上方，所述第一接合区域的击穿电压比形成于所述半导体元件的电流经路中的第二接合区域的击穿电压低。因此，在本发明中，在半导体衬底和第一外延层上形成一导电类型埋入扩散层及反导电类型第一埋入扩散层，且形成第一接合区域。在第一及第二外延层上形成反导电类型第二埋入扩散层，将反导电类型的第一及第二埋入扩散层连接。根据该结构，实现过电压保护结构。
在本发明中，在形成任意半导体元件的区域的下方将P型埋入扩散层和N型埋入扩散层重叠，形成PN结区域。使该PN结区域的击穿电压比形成于半导体元件的电流经路中的PN结区域的击穿电压低。根据该结构，可防止由过电压破坏半导体元件。
在本发明中，PN结区域形成于N型埋入扩散层上面的宽的区域。根据该结构，在PN结区域，击穿电流扩散，可防止PN结区域的破坏。
在本发明中，在元件形成区域下方形成N型埋入扩散层，且形成有PN结区域。根据该结构，可有效地配置N型埋入扩散层，且可降低无效区域。而且，在实际工作区域有效地配置半导体元件，可实现芯片尺寸的微细化。
另外，在本发明中，由P型埋入扩散层和与该P型埋入扩散层重叠形成的N型埋入扩散层的PN结区域形成过电压保护结构。根据该结构，PN结区域附近的P型埋入扩散层维持高浓度的杂质浓度，可容易地设定所希望的击穿电压。
附图说明
图1是说明本发明实施例的半导体装置的剖面图；
图2用于说明形成本发明实施例的过电压保护结构的区域的浓度曲线的图；
图3是用于说明本发明实施例的半导体装置的源-漏极间的电流值和源-漏极间的电压值的关系的图；
图4是说明本发明实施例的半导体装置的剖面图；
图5是说明本发明实施例的半导体装置的制造方法的剖面图；
图6是说明本发明实施例的半导体装置的制造方法的剖面图；
图7是说明本发明实施例的半导体装置的制造方法的剖面图；
图8是说明本发明实施例的半导体装置的制造方法的剖面图；
图9是说明本发明实施例的半导体装置的制造方法的剖面图；
图10是说明本发明实施例的半导体装置的制造方法的剖面图。
附图标记
1N沟道型LDMOS晶体管
2P型单晶硅衬底
3N型外延层
4P型埋入扩散层
5N型埋入扩散层
6N型外延层
7N型埋入扩散层
19PN结区域
20PN结区域
21NPN晶体管
22PNP晶体管
23CMOS晶体管
具体实施方式
下面，参照图1～图4详细说明本发明一实施例的半导体装置。图1是用于说明本实施例的半导体装置的剖面图。图2是形成作为过电压保护结构的PN结区域的浓度曲线的图。图3是具有过电压保护结构的半导体装置和没有过电压保护结构的半导体装置的元件特性的比较图。图4是用于说明本发明实施例的半导体装置的剖面图。
如图1所示，N沟道型LDMOS晶体管1主要由P型单晶硅衬底2、第一层N型外延层3、P型埋入扩散层4、N型埋入扩散层5、第二层N型外延层6、N型埋入扩散层7、P型扩散层8、作为漏极区域使用的N型扩散层9、10、作为反向栅极区域使用的P型扩散层11、12、作为源极区域使用的N型扩散层13、N型扩散层14、栅极氧化膜15、栅极电极16。
第一层N型外延层3堆积于P型单晶硅衬底2上面。
P型埋入扩散层4形成于衬底2及外延层3两个区域上。P型埋入扩散层4例如扩散硼(B)形成。图中，P型埋入扩散层4形成在整个衬底2上，但也可以在至少形成N型埋入扩散层5和PN结区域的区域形成。另外，本实施例中的P型埋入扩散层4与本发明的“一导电类型埋入扩散层”对应。
N型埋入扩散层5形成于衬底2及外延层3两个区域上。N型埋入扩散层5例如扩散锑(Sb)形成。如图所示，N型埋入扩散层5由分离区域17区分，在LDMOS晶体管1的形成区域形成。另外，由于杂质扩散系数不同，从而P型埋入扩散层4比N型埋入扩散层5高。另外，本实施例中的N型扩散层5与本发明的“反导电类型第一埋入扩散层”对应。
第二层N型外延层6堆积于第一层N型外延层3上面。
N型埋入扩散层7形成于第一层及第二层外延层3、6两个区域上。N型埋入扩散层7例如扩散锑(Sb)形成。如图所示，N型埋入扩散层7从P型埋入扩散层4上方扩散，与N型埋入扩散层5连接。另外，本实施例中的N型埋入扩散层7与本发明的“反导电类型第二埋入扩散层”对应。另外，本实施例的N型埋入扩散层5、7与本发明的“反导电类型埋入扩散层”对应。
P型扩散层8形成于外延层6上。在P型扩散层8上形成有LDMOS晶体管1的源极区域、漏极区域及反向栅极区域。
N型扩散层9、10形成于P型扩散层8上。N型扩散层9、10作为漏极区域使用，为双重扩散结构。N型扩散层9、10形成一环状，使其包围P型扩散层11。
P型扩散层11、12形成于P型扩散层8上。P型扩散层11被作为反向栅极区域使用，P型扩散层12被作为反向栅导出区域使用。
N型扩散层13形成于P型扩散层11上。N型扩散层13被作为源极区域使用。N型扩散层13形成一环状，使其包围P型扩散层12形成。位于N型扩散层9和N型扩散层13之间的P型扩散层11被作为沟道区域使用。而且，使源极电极与P型扩散层12和N型扩散层13接触。即，在P型扩散层12上施加与源极电位同电位的反向栅极电位。另外，在本实施例中，源极电位及反向栅极电位为接地电位。
N型扩散层14形成于P型扩散层8和P型分离区域17之间的外延层6上。N型扩散层14由外延层6上方的配线等与N型扩散层10连接的输出焊盘连接。根据该结构，在N型扩散层14上施加漏极电位。如图所示，在N型扩散层14下方经由N型外延层3、6形成有N型埋入扩散层5、7。在N型埋入扩散层5、7上经由N型扩散层14施加漏极电位。
栅极氧化膜15形成于形成反向栅极区域等的外延层6表面。
栅电极16形成于栅极氧化膜15上。栅电极16例如由多晶硅膜、钨硅膜等形成所希望的膜厚。
最后，在外延层6的所希望的区域形成有LOCOS(Local Oxidation ofSilicon)氧化膜18。图中未图示，但在外延层6上面形成有BPSG(BoronPhospho Silicate Glass)膜、SOG(Spin On Glass)膜等绝缘膜。
其次，如图中粗的实线所示，在形成有LDMOS晶体管1的区域的下方形成有P型埋入扩散层4和N型埋入扩散层5的PN结区域19。如上所述，在N型埋入扩散层5上施加漏极电位。另一方面，图中未图示，但P型分离区域17构成接地电位，P型埋入扩散层4经由分离区域17构成接地电位。即，在PN结区域19上施加反向偏压，在LDMOS晶体管1进行通常的动作时，其为导通状态。另外，本实施例中的PN结区域19与本发明的“第一接合区域”对应。
另外，如图中粗线所示，在LDMOS晶体管1的电流经路中形成有N型扩散层9和P型扩散层11的PN结区域20。在N型扩散层9上经由N型扩散层10施加漏极电位。另一方面，在P型扩散层11上经由P型扩散层12施加反向栅极电位。即，与PN结区域19相同，在PN结区域20上施加反向偏压。另外，本实施例中的PN结区域20与本发明的“第二接合区域”对应。另外，作为“第二接合区域”，在未形成P型扩散层8及N型扩散层9的结构中，也可以为N型外延层6和P型扩散层11的接合区域的情况。
根据该结构，PN结区域19和PN结区域20实质上施加同条件的反向偏压。而且，在LDMOS晶体管1的源-漏极间经由漏极区域施加例如在断开电动机负载等L负载时产生的过电压等。此时，在PN结区域20击穿之前，通过将PN结区域19击穿，可防止LDMOS晶体管1的破坏。详细后述，在本实施例中，决定P型埋入扩散层4及N型埋入扩散层5的杂质浓度，使PN结区域19的击穿电压比PN结区域20的击穿电压(源-漏极间的击穿电压)低。即，通过在N型埋入扩散层5的底面及其附近区域形成高浓度的P型埋入扩散层4，将耗尽层扩展的区域减窄。另外，形成PN结区域19的区域根据P型埋入扩散层4的杂质浓度状态，也形成于N型埋入扩散层5的侧面。
图2中，表示在图1所示的LDMOS晶体管1的A-A剖面，构成PN结区域19的P型埋入扩散层4及N型埋入扩散层5、7的浓度曲线图。另外，横轴表示杂质浓度。纵轴表示从衬底表面离开的距离。而且，以从衬底表面到外延层表面侧的离开距离为正，以从衬底表面到衬底底面侧的离开距离为负。
如图所示，在P型埋入扩散层4中，在距衬底2表面-4(μm)程度的区域形成有杂质浓度的波峰。在N型埋入扩散层5中，在衬底2和外延层3的分界区域形成有杂质浓度的波峰。在N型埋入扩散层7中，在距衬底2表面6(μm)程度的区域形成有杂质浓度的波峰。而且，PN结区域19形成于距衬底2表面-3～-4(μm)程度的区域。PN结区域19附近的P型埋入扩散层4的杂质浓度为1.0×1016～1.0×1017(/cm2)程度。即，P型埋入扩散层4在PN结区域19附近形成高杂质浓度的状态。该浓度曲线可通过在P型埋入扩散层4上进一步重叠形成高杂质浓度的N型埋入扩散层5而实现。
另一方面，如图1所示，在本实施例中，由于P型埋入扩散层4的杂质浓度高，且杂质扩散系数的不同，从而P型扩散层4比N型埋入扩散层5高。因此，在N型埋入扩散层5上面形成高杂质浓度的N型埋入扩散层7，将两扩散层5、7连接。
根据该结构，可构成相对P型埋入扩散层4导出N型埋入扩散层7的形状，可在PN结区域19上施加反向偏压。而且，以PN结区域19附近的P型埋入扩散层4为高杂质浓度，可使PN结区域19的击穿电压比PN结区域20的击穿电压低。
图3中，将LDMOS晶体管的BVds设为40(V)，实线表示具有过电压保护结构(PN结区域19)的情况，虚线表示没有过电压保护结构(PN结区域19)的情况。在由实线表示的结构中，由于将PN结区域19设为30(V)程度的击穿电压，故未在源-漏极间施加30(V)程度以上的电压。另一方面，在虚线所示的结构中，在源-漏极间施加38(V)程度的电压，在PN结区域20产生击穿。如上所述，由于具有PN结区域19作为过电压保护结构，从而即使在施加有过电压的情况下，也可以实现难以破坏LDMOS晶体管的结构。
另外，PN结区域19的击穿电压可根据P型埋入扩散层4、N型埋入扩散层5的杂质浓度的调整及P型埋入扩散层4、N型埋入扩散层5的扩散幅度等任意设计变更。而且，当将PN结区域19的击穿电压设定得过低时，也有LDMOS晶体管的电流能力恶化的情况。因此，考虑元件特性，可将PN结区域19的击穿电压设定在所希望的范围。
另外，如图1所示，在本实施例中，在LDMOS晶体管1的下方大范围形成P型埋入扩散层4和N型埋入扩散层5。而且，可在LDMOS晶体管1的下方大范围形成PN结区域19。根据该结构，有效地配置N型埋入扩散层15，防止在实际工作区域中未配置元件的无效区域的增加，可缩小芯片尺寸。另外，PN结区域19击穿，产生的击穿电流流向衬底2。此时，通过在宽的区域形成PN结区域19，可防止击穿电流的集中及该集中产生的热，且可防止PN结区域19的破坏。
如图4所示，在本实施例中，即使在元件形成区域形成NPN晶体管21、PNP晶体管22、CMOS晶体管23等的情况下，也可以形成作为过电压保护结构的PN结区域24、25、26。另外，由于PN结区域24、25、26的结构及其效果与使用图1说明的PN结区域19相同，故在此省略该说明。
在NPN晶体管21中，例如在对集电极施加过电压时，PN结区域24比电流经路的PN结区域27提前击穿。而且，可防止NPN晶体管21的破坏。
在PNP晶体管22中，例如在对基极施加过电压时，PN结区域25比电流经路的PN结区域28提前击穿。而且，可防止PNP晶体管22的破坏。
在CMOS晶体管23中，例如在对N沟道型晶体管的漏极电极、及P沟道型源极电极施加过电压时，PN结区域26比电流经路的PN结区域29、30域提前击穿。而且，可防止CMOS晶体管23的破坏。
在本实施例中，即使在使用NPN晶体管21、PNP晶体管22、CMOS晶体管23等作为离散的元件的情况下，或作为半导体集成电路的情况下，也可以使用过电压保护结构。
在本实施例中，对在衬底上层积两层外延层，形成过电压保护结构及半导体元件的情况进行了说明，但不限于该情况。例如，也可以为在衬底上形成一层外延层的情况，或在衬底上形成多层外延层的情况。即，通过在半导体元件下方形成比形成于半导体元件的电流经路中的PN结区域先被击穿的PN结区域，可得到同样的效果。在不脱离本发明主旨的范围内，可进行各种变更。
其次，参照图5～图10详细说明本发明一实施例的半导体装置的制造方法。另外，在下面的说明中，与图1所示的半导体装置中说明的各构成要素相同的构成要素使用相同的符号。
图5～图10是用于说明本实施例的半导体装置的制造方法的剖面图。另外，在下面的说明中，以由分离区域区分的一个元件形成区域例如形成N沟道型MOS晶体管的情况进行说明，但不限于该情况。例如，也可以为在其它元件形成区域形成P沟道型MOS晶体管、NPN型晶体管、纵型PNP晶体管等，形成半导体集成电路装置的情况。
首先，如图5所示，准备P型单晶硅衬底2。使用公知的光刻技术，从衬底2的表面向形成P型埋入扩散层4的区域离子注入P型杂质，例如硼(B)。而且，在除去光致抗蚀剂后，将离子注入的杂质扩散。
其次，如图6所示，使用公知的光刻技术，从形成有P型埋入扩散层4的衬底2表面向形成N型埋入扩散层5的区域离子注入N型杂质，例如锑(Sb)。而且，在除去光致抗蚀剂后，将离子注入的杂质扩散。
其次，如图7所示，在外延成长装置的受纳器上配置衬底2。然后，由灯加热系统，给予衬底2例如1200℃程度的高温，同时向反应管内导入SiHCl3气体和H2气体。根据该工序，在衬底2上成长例如电阻率0.1～2.0Ω·cm，厚度0.5～1.5μm程度的外延层3。根据该工序，P型埋入扩散层4及N型埋入扩散层51向外延层3扩散。此时，由于硼(B)的扩散系数比锑(Sb)的大，故P型埋入扩散层4从N型埋入扩散层5爬上去。
然后，使用公知的光刻技术，从外延层3表面向形成N型埋入扩散层7的区域离子注入N型杂质例如锑(Sb)。而且，在除去光致抗蚀剂后，将离子注入的杂质扩散。
其次，如图8所示，再次在外延成长装置的受纳器上配置衬底2。然后，由灯加热系统，给予衬底2例如1200℃程度的高温，同时向反应管内导入SiHCl3气体和H2气体。根据该工序，在外延层3上成长例如电阻率0.1～2.0Ω·cm，厚度0.5～1.5μm程度的外延层6。根据该工序，N型埋入扩散层7向外延层3、6扩散。将N型埋入扩散层5、7连接。
然后，使用公知的光刻技术，从外延层6表面形成P型扩散层8及N型扩散层9。
其次，如图9所示，给予衬底2整体热处理，在外延层6的所希望的区域形成LOCOS氧化膜18。而且，在外延层6表面堆积氧化硅膜、多晶硅膜及钨硅膜。使用公知的光刻技术，选择地除去氧化硅膜、多晶硅膜及钨硅膜，形成栅极氧化膜15及栅极电极16。
然后，使用公知的光刻技术，从外延层6表面向形成P型扩散层11的区域离子注入P型杂质，例如硼(B)。而且，在除去光致抗蚀剂后，将离子注入的杂质扩散。在该工序中，利用栅极电极16的一端侧，由自对准技术形成P型扩散层11。
最后，如图10所示，使用公知的光刻技术，从外延层6表面形成N型扩散层10、13、14及P型扩散层12。然后，在外延层6上堆积例如BPSG膜及SOG膜等作为绝缘层31。然后，使用公知的光刻技术，由例如使用CHF3+O2类气体的干式蚀刻在绝缘层31上形成接触孔32、33、34。
其次，在接触孔32、33、34内壁等形成势垒金属膜35。然后，由钨(W)膜36埋设接触孔32、33、34内。然后，利用CVD法在钨(W)膜36上面堆积铝铜(AlCu)膜、势垒金属膜。然后，使用公知的光刻技术，选择地除去AlCu膜及势垒金属膜，形成源极电极37及漏极电极38。另外，在图10所示的剖面，对栅极电极16进行配线的配线层没有图示，但在其它区域与配线层连接。另外，图中未图示，但形成于N型扩散层14上的电极39与漏极电极38同电位而电连接。
如上所述，在本实施例中，形成N型埋入扩散层5，使其与P型埋入扩散层4重叠。而且，将位于N型埋入扩散层5底面的P型埋入扩散层4的杂质浓度维持高浓度。根据该制造方法，容易地将两埋设扩散层4、5的PN结区域的击穿电压调整为所希望的范围。
另外，在本实施例中，在N型埋入扩散层5上进一步形成N型埋入扩散层7，将两埋入扩散层4、5连接。根据该制造方法，可从P型埋入扩散层4导出连接的N型埋入扩散层5、7。
另外，在本实施例中，对通过连接两个N型埋入扩散层来形成作为过电压保护结构的PN结区域的情况进行了说明，但不限于该情况。例如，也可以为由一次扩散工序或多次扩散工序形成所希望的N型埋入扩散层的情况。即，若为可在过电压保护结构中使用的形成PN结区域的方法，则可进行任意的设计变更。另外，在不脱离本发明主旨的范围内，可进行各种变更。

Claims (6)

1、一种半导体装置，在半导体衬底上堆积多层外延层，并将所述外延层作为半导体元件的形成区域使用，其特征在于，在所述半导体元件的形成区域下方形成一导电类型埋入扩散层和形成到所述一导电类型埋入扩散层上的反导电类型埋入扩散层，所述一导电类型埋入扩散层和所述反导电类型埋入扩散层的第一接合区域的击穿电压比形成于所述半导体元件的电流经路中的第二接合区域的击穿电压低。
2、如权利要求1所述的半导体装置，其特征在于，所述反导电类型埋入扩散层将反导电类型第一埋入扩散层和反导电类型第二埋入扩散层连接形成，其中，第一埋入扩散层将所述一导电类型埋入扩散层和其形成区域重叠形成，第二埋入扩散层形成于所述一导电类型埋入扩散层的上方。
3、如权利要求1或2所述的半导体装置，其特征在于，所述半导体元件为NPN晶体管、PNP晶体管、N沟道型MOS晶体管、P沟道型MOS晶体管。
4、一种半导体装置，其特征在于，具有：一导电类型半导体衬底；反导电类型第一外延层，其形成于所述半导体衬底上；一导电类型埋入扩散层，其形成于所述半导体衬底和所述第一外延层上；反导电类型第一埋入扩散层，其形成于所述半导体衬底和所述第一外延层上，将所述一导电类型埋入扩散层和其形成区域重叠形成；第一接合区域，其形成于所述一导电类型埋入扩散层和所述反导电类型第一埋入扩散层；反导电类型第二外延层，形成于所述第一外延层上；反导电类型第二埋入扩散层，其形成于所述第一及第二外延层上，与所述第一埋入扩散层连接；半导体元件，其形成于所述第二埋入扩散层上方，所述第一接合区域的击穿电压比形成于所述半导体元件的电流经路中的第二接合区域的击穿电压低。
5、如权利要求4所述的半导体装置，其特征在于，所述第一接合区域形成于所述反导电类型第一埋入扩散层的底面及其附近区域。
6、如权利要求4或5所述的半导体装置，其特征在于，所述半导体元件是NPN晶体管、PNP晶体管、N沟道型MOS晶体管、P沟道型MOS晶体管。
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