CN1231921C - 非易失性半导体存储器件 - Google Patents

非易失性半导体存储器件 Download PDF

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Publication number
CN1231921C
CN1231921C CN02122195.2A CN02122195A CN1231921C CN 1231921 C CN1231921 C CN 1231921C CN 02122195 A CN02122195 A CN 02122195A CN 1231921 C CN1231921 C CN 1231921C
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CN
China
Prior art keywords
sector
control gate
line
sectors
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN02122195.2A
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English (en)
Chinese (zh)
Other versions
CN1391232A (zh
Inventor
龟井辉彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
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Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of CN1391232A publication Critical patent/CN1391232A/zh
Application granted granted Critical
Publication of CN1231921C publication Critical patent/CN1231921C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491—Virtual ground arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
CN02122195.2A 2001-04-13 2002-04-13 非易失性半导体存储器件 Expired - Fee Related CN1231921C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001115678A JP3640175B2 (ja) 2001-04-13 2001-04-13 不揮発性半導体記憶装置
JP115678/2001 2001-04-13
JP115678/01 2001-04-13

Publications (2)

Publication Number Publication Date
CN1391232A CN1391232A (zh) 2003-01-15
CN1231921C true CN1231921C (zh) 2005-12-14

Family

ID=18966541

Family Applications (1)

Application Number Title Priority Date Filing Date
CN02122195.2A Expired - Fee Related CN1231921C (zh) 2001-04-13 2002-04-13 非易失性半导体存储器件

Country Status (3)

Country Link
US (1) US6822900B2 (https=)
JP (1) JP3640175B2 (https=)
CN (1) CN1231921C (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6532172B2 (en) * 2001-05-31 2003-03-11 Sandisk Corporation Steering gate and bit line segmentation in non-volatile memories
JP3716914B2 (ja) 2001-05-31 2005-11-16 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP3821032B2 (ja) 2002-03-20 2006-09-13 セイコーエプソン株式会社 ファイルストレージ型不揮発性半導体記憶装置
JP3815381B2 (ja) * 2002-06-06 2006-08-30 セイコーエプソン株式会社 不揮発性半導体記憶装置およびその駆動方法
JP3867624B2 (ja) * 2002-06-06 2007-01-10 セイコーエプソン株式会社 不揮発性半導体記憶装置およびその駆動方法
JP3871049B2 (ja) 2002-12-10 2007-01-24 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP2004199738A (ja) * 2002-12-16 2004-07-15 Seiko Epson Corp 不揮発性記憶装置
JP3985689B2 (ja) * 2003-02-21 2007-10-03 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP2004265508A (ja) * 2003-02-28 2004-09-24 Seiko Epson Corp 不揮発性半導体記憶装置
JP3786095B2 (ja) 2003-02-28 2006-06-14 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP3873908B2 (ja) * 2003-02-28 2007-01-31 セイコーエプソン株式会社 不揮発性半導体記憶装置及びその製造方法
KR100506941B1 (ko) * 2003-08-19 2005-08-05 삼성전자주식회사 더미 셀들을 갖는 플래쉬 메모리소자 및 그것의 소거방법들
US8233322B2 (en) * 2003-10-10 2012-07-31 Micron Technology, Inc. Multi-partition memory with separated read and algorithm datalines
FR2871940B1 (fr) * 2004-06-18 2007-06-15 St Microelectronics Rousset Transistor mos a grille flottante, a double grille de controle
US7130221B1 (en) * 2005-09-26 2006-10-31 Macronix International Co., Ltd. Dual gate multi-bit semiconductor memory
KR100706789B1 (ko) * 2005-11-17 2007-04-12 삼성전자주식회사 비휘발성 메모리 소자
US7916551B2 (en) * 2007-11-06 2011-03-29 Macronix International Co., Ltd. Method of programming cell in memory and memory apparatus utilizing the method

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63225991A (ja) 1987-03-16 1988-09-20 Hitachi Ltd 半導体記憶装置
JPH01300496A (ja) 1988-05-30 1989-12-04 Hitachi Ltd 半導体メモリ装置
JPH07161851A (ja) 1993-12-10 1995-06-23 Sony Corp 半導体不揮発性記憶装置およびその製造方法
US5408115A (en) 1994-04-04 1995-04-18 Motorola Inc. Self-aligned, split-gate EEPROM device
US5422504A (en) 1994-05-02 1995-06-06 Motorola Inc. EEPROM memory device having a sidewall spacer floating gate electrode and process
US5663923A (en) 1995-04-28 1997-09-02 Intel Corporation Nonvolatile memory blocking architecture
US5969383A (en) 1997-06-16 1999-10-19 Motorola, Inc. Split-gate memory device and method for accessing the same
JP2978477B1 (ja) 1998-06-12 1999-11-15 株式会社日立製作所 半導体集積回路装置およびその製造方法
JP3973819B2 (ja) 1999-03-08 2007-09-12 株式会社東芝 半導体記憶装置およびその製造方法
US6255166B1 (en) 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
US6177318B1 (en) 1999-10-18 2001-01-23 Halo Lsi Design & Device Technology, Inc. Integration method for sidewall split gate monos transistor
US6248633B1 (en) 1999-10-25 2001-06-19 Halo Lsi Design & Device Technology, Inc. Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory
JP4899241B2 (ja) * 1999-12-06 2012-03-21 ソニー株式会社 不揮発性半導体記憶装置およびその動作方法
DE60235335D1 (de) * 2001-03-15 2010-04-01 Halo Inc Doppelbit MONOS Speicherzellgebrauch für breite Programbandbreite
JP3780865B2 (ja) * 2001-04-13 2006-05-31 セイコーエプソン株式会社 不揮発性半導体記憶装置
JP4715024B2 (ja) * 2001-05-08 2011-07-06 セイコーエプソン株式会社 不揮発性半導体記憶装置のプログラム方法
US6563736B2 (en) * 2001-05-18 2003-05-13 Ibm Corporation Flash memory structure having double celled elements and method for fabricating the same

Also Published As

Publication number Publication date
US6822900B2 (en) 2004-11-23
JP2002313090A (ja) 2002-10-25
JP3640175B2 (ja) 2005-04-20
CN1391232A (zh) 2003-01-15
US20030072191A1 (en) 2003-04-17

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Granted publication date: 20051214

Termination date: 20130413