CN1224926A - 半导体管芯上互连凸块的制作方法 - Google Patents
半导体管芯上互连凸块的制作方法 Download PDFInfo
- Publication number
- CN1224926A CN1224926A CN99101606A CN99101606A CN1224926A CN 1224926 A CN1224926 A CN 1224926A CN 99101606 A CN99101606 A CN 99101606A CN 99101606 A CN99101606 A CN 99101606A CN 1224926 A CN1224926 A CN 1224926A
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- Prior art keywords
- layer
- projection
- tin
- eutectic
- make
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 229910000679 solder Inorganic materials 0.000 claims abstract description 48
- 230000005496 eutectics Effects 0.000 claims abstract description 47
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052802 copper Inorganic materials 0.000 claims abstract description 39
- 239000010949 copper Substances 0.000 claims abstract description 39
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 35
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 24
- 238000005516 engineering process Methods 0.000 claims description 11
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 238000010899 nucleation Methods 0.000 claims 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 7
- 238000001465 metallisation Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 9
- 229910000765 intermetallic Inorganic materials 0.000 description 8
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- 238000005275 alloying Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
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- 239000002184 metal Substances 0.000 description 4
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- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
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- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
Claims (9)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US015956 | 1998-01-30 | ||
US09/015,956 US6107180A (en) | 1998-01-30 | 1998-01-30 | Method for forming interconnect bumps on a semiconductor die |
US015,956 | 1998-01-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1224926A true CN1224926A (zh) | 1999-08-04 |
CN1154167C CN1154167C (zh) | 2004-06-16 |
Family
ID=21774542
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB991016068A Expired - Lifetime CN1154167C (zh) | 1998-01-30 | 1999-01-28 | 半导体管芯上互连凸块的制作方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6107180A (zh) |
JP (1) | JP4334647B2 (zh) |
KR (1) | KR100632712B1 (zh) |
CN (1) | CN1154167C (zh) |
TW (1) | TW419805B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100382291C (zh) * | 2005-05-17 | 2008-04-16 | 矽品精密工业股份有限公司 | 半导体装置及其制法 |
CN106356352A (zh) * | 2016-10-27 | 2017-01-25 | 江苏科技大学 | 一种凸点下金属化层构件及制备方法 |
Families Citing this family (83)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6642136B1 (en) | 2001-09-17 | 2003-11-04 | Megic Corporation | Method of making a low fabrication cost, high performance, high reliability chip scale package |
US6342443B1 (en) * | 1999-07-02 | 2002-01-29 | Advanced Semiconductor Engineering, Inc. | Method and structure for forming flip chip with collapse-controlled solder bumps on a substrate |
US6570251B1 (en) * | 1999-09-02 | 2003-05-27 | Micron Technology, Inc. | Under bump metalization pad and solder bump connections |
KR100311975B1 (ko) * | 1999-12-16 | 2001-10-17 | 윤종용 | 반도체소자 및 그 제조방법 |
DE60109339T2 (de) * | 2000-03-24 | 2006-01-12 | Texas Instruments Incorporated, Dallas | Verfahren zum Drahtbonden |
JP4750926B2 (ja) * | 2000-06-06 | 2011-08-17 | 富士通セミコンダクター株式会社 | 半導体装置 |
TW459362B (en) * | 2000-08-01 | 2001-10-11 | Siliconware Precision Industries Co Ltd | Bump structure to improve the smoothness |
US6408511B1 (en) * | 2000-08-21 | 2002-06-25 | National Semiconductor, Inc. | Method of creating an enhanced BGA attachment in a low-temperature co-fired ceramic (LTCC) substrate |
US6586323B1 (en) * | 2000-09-18 | 2003-07-01 | Taiwan Semiconductor Manufacturing Company | Method for dual-layer polyimide processing on bumping technology |
WO2002027790A1 (en) * | 2000-09-29 | 2002-04-04 | Ellipsiz Ltd | Barrier layers for solder joints |
US6570396B1 (en) * | 2000-11-24 | 2003-05-27 | Kulicke & Soffa Investment, Inc. | Interface structure for contacting probe beams |
US6667230B2 (en) * | 2001-07-12 | 2003-12-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Passivation and planarization process for flip chip packages |
KR100447968B1 (ko) | 2001-08-07 | 2004-09-10 | 주식회사 하이닉스반도체 | 웨이퍼 레벨 패키지의 제조방법 |
US6550666B2 (en) * | 2001-08-21 | 2003-04-22 | Advanpack Solutions Pte Ltd | Method for forming a flip chip on leadframe semiconductor package |
US6489229B1 (en) | 2001-09-07 | 2002-12-03 | Motorola, Inc. | Method of forming a semiconductor device having conductive bumps without using gold |
US7099293B2 (en) | 2002-05-01 | 2006-08-29 | Stmicroelectronics, Inc. | Buffer-less de-skewing for symbol combination in a CDMA demodulator |
US6732908B2 (en) * | 2002-01-18 | 2004-05-11 | International Business Machines Corporation | High density raised stud microjoining system and methods of fabricating the same |
US6930032B2 (en) * | 2002-05-14 | 2005-08-16 | Freescale Semiconductor, Inc. | Under bump metallurgy structural design for high reliability bumped packages |
US6596619B1 (en) | 2002-05-17 | 2003-07-22 | Taiwan Semiconductor Manufacturing Company | Method for fabricating an under bump metallization structure |
US20030234276A1 (en) * | 2002-06-20 | 2003-12-25 | Ultratera Corporation | Strengthened bonding mechanism for semiconductor package |
US20040007779A1 (en) * | 2002-07-15 | 2004-01-15 | Diane Arbuthnot | Wafer-level method for fine-pitch, high aspect ratio chip interconnect |
KR100476301B1 (ko) * | 2002-07-27 | 2005-03-15 | 한국과학기술원 | 전기도금법에 의한 반도체 소자의 플립칩 접속용 ubm의형성방법 |
US6762503B2 (en) * | 2002-08-29 | 2004-07-13 | Micron Technology, Inc. | Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same |
US6780751B2 (en) * | 2002-10-09 | 2004-08-24 | Freescale Semiconductor, Inc. | Method for eliminating voiding in plated solder |
JP4758614B2 (ja) * | 2003-04-07 | 2011-08-31 | ローム・アンド・ハース・エレクトロニック・マテリアルズ,エル.エル.シー. | 電気めっき組成物および方法 |
CN1284207C (zh) * | 2003-06-03 | 2006-11-08 | 香港科技大学 | 一种用于半导体封装的焊球的制备方法 |
US8084866B2 (en) | 2003-12-10 | 2011-12-27 | Micron Technology, Inc. | Microelectronic devices and methods for filling vias in microelectronic devices |
US7091124B2 (en) | 2003-11-13 | 2006-08-15 | Micron Technology, Inc. | Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices |
US7294929B2 (en) * | 2003-12-30 | 2007-11-13 | Texas Instruments Incorporated | Solder ball pad structure |
US20050247894A1 (en) | 2004-05-05 | 2005-11-10 | Watkins Charles M | Systems and methods for forming apertures in microfeature workpieces |
JP4327656B2 (ja) * | 2004-05-20 | 2009-09-09 | Necエレクトロニクス株式会社 | 半導体装置 |
TWI331370B (en) * | 2004-06-18 | 2010-10-01 | Megica Corp | Connection between two circuitry components |
US7232754B2 (en) | 2004-06-29 | 2007-06-19 | Micron Technology, Inc. | Microelectronic devices and methods for forming interconnects in microelectronic devices |
US7465654B2 (en) * | 2004-07-09 | 2008-12-16 | Megica Corporation | Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures |
US8022544B2 (en) * | 2004-07-09 | 2011-09-20 | Megica Corporation | Chip structure |
US20060023107A1 (en) * | 2004-08-02 | 2006-02-02 | Bolken Todd O | Microelectronic imagers with optics supports having threadless interfaces and methods for manufacturing such microelectronic imagers |
US7452803B2 (en) * | 2004-08-12 | 2008-11-18 | Megica Corporation | Method for fabricating chip structure |
US7425499B2 (en) | 2004-08-24 | 2008-09-16 | Micron Technology, Inc. | Methods for forming interconnects in vias and microelectronic workpieces including such interconnects |
US7429494B2 (en) * | 2004-08-24 | 2008-09-30 | Micron Technology, Inc. | Microelectronic imagers with optical devices having integral reference features and methods for manufacturing such microelectronic imagers |
US7083425B2 (en) | 2004-08-27 | 2006-08-01 | Micron Technology, Inc. | Slanted vias for electrical circuits on circuit boards and other substrates |
US7300857B2 (en) | 2004-09-02 | 2007-11-27 | Micron Technology, Inc. | Through-wafer interconnects for photoimager and memory wafers |
DE102004047730B4 (de) * | 2004-09-30 | 2017-06-22 | Advanced Micro Devices, Inc. | Ein Verfahren zum Dünnen von Halbleitersubstraten zur Herstellung von dünnen Halbleiterplättchen |
US7547969B2 (en) | 2004-10-29 | 2009-06-16 | Megica Corporation | Semiconductor chip with passivation layer comprising metal interconnect and contact pads |
US7271482B2 (en) | 2004-12-30 | 2007-09-18 | Micron Technology, Inc. | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
US7282433B2 (en) * | 2005-01-10 | 2007-10-16 | Micron Technology, Inc. | Interconnect structures with bond-pads and methods of forming bump sites on bond-pads |
US7321140B2 (en) * | 2005-03-11 | 2008-01-22 | Applied Materials, Inc. | Magnetron sputtered metallization of a nickel silicon alloy, especially useful as solder bump barrier |
TWI258176B (en) * | 2005-05-12 | 2006-07-11 | Siliconware Precision Industries Co Ltd | Semiconductor device and fabrication method thereof |
US7795134B2 (en) | 2005-06-28 | 2010-09-14 | Micron Technology, Inc. | Conductive interconnect structures and formation methods using supercritical fluids |
US20060290001A1 (en) * | 2005-06-28 | 2006-12-28 | Micron Technology, Inc. | Interconnect vias and associated methods of formation |
CN1901163B (zh) | 2005-07-22 | 2011-04-13 | 米辑电子股份有限公司 | 连续电镀制作线路组件的方法及线路组件结构 |
TWI281699B (en) * | 2005-07-26 | 2007-05-21 | Siliconware Precision Industries Co Ltd | Semiconductor device and fabrication method thereof |
TW200709359A (en) * | 2005-08-31 | 2007-03-01 | Advanced Semiconductor Eng | Wafer structure |
US20070045812A1 (en) * | 2005-08-31 | 2007-03-01 | Micron Technology, Inc. | Microfeature assemblies including interconnect structures and methods for forming such interconnect structures |
US7863187B2 (en) * | 2005-09-01 | 2011-01-04 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
TWI295498B (en) * | 2005-09-30 | 2008-04-01 | Siliconware Precision Industries Co Ltd | Semiconductor element with conductive bumps and fabrication method thereof |
US7397121B2 (en) | 2005-10-28 | 2008-07-08 | Megica Corporation | Semiconductor chip with post-passivation scheme formed over passivation layer |
US20070102815A1 (en) * | 2005-11-08 | 2007-05-10 | Kaufmann Matthew V | Bumping process with self-aligned A1-cap and the elimination of 2nd passivation layer |
US8266152B2 (en) * | 2006-03-03 | 2012-09-11 | Perfect Search Corporation | Hashed indexing |
US20070238283A1 (en) * | 2006-04-05 | 2007-10-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Novel under-bump metallization for bond pad soldering |
US7749899B2 (en) | 2006-06-01 | 2010-07-06 | Micron Technology, Inc. | Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces |
US20080003803A1 (en) * | 2006-06-30 | 2008-01-03 | Pei-Haw Tsao | Semiconductor package substrate for flip chip packaging |
US7629249B2 (en) | 2006-08-28 | 2009-12-08 | Micron Technology, Inc. | Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods |
US7902643B2 (en) | 2006-08-31 | 2011-03-08 | Micron Technology, Inc. | Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods |
TWI320588B (en) * | 2006-12-27 | 2010-02-11 | Siliconware Precision Industries Co Ltd | Semiconductor device having conductive bumps and fabrication methodthereof |
TWI343084B (en) * | 2006-12-28 | 2011-06-01 | Siliconware Precision Industries Co Ltd | Semiconductor device having conductive bumps and fabrication methodthereof |
US7820543B2 (en) * | 2007-05-29 | 2010-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Enhanced copper posts for wafer level chip scale packaging |
SG150410A1 (en) | 2007-08-31 | 2009-03-30 | Micron Technology Inc | Partitioned through-layer via and associated systems and methods |
US8492263B2 (en) | 2007-11-16 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protected solder ball joints in wafer level chip-scale packaging |
US7884015B2 (en) | 2007-12-06 | 2011-02-08 | Micron Technology, Inc. | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
KR101037832B1 (ko) * | 2008-05-09 | 2011-05-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US8299616B2 (en) * | 2010-01-29 | 2012-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | T-shaped post for semiconductor devices |
JP2011165862A (ja) * | 2010-02-09 | 2011-08-25 | Sony Corp | 半導体装置、チップ・オン・チップの実装構造、半導体装置の製造方法及びチップ・オン・チップの実装構造の形成方法 |
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DE102012102021A1 (de) * | 2012-03-09 | 2013-09-12 | Epcos Ag | Mikromechanisches Messelement und Verfahren zur Herstellung eines mikromechanischen Messelements |
US9515036B2 (en) | 2012-04-20 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for solder connections |
DE112013003715T5 (de) * | 2012-07-28 | 2015-06-03 | Laird Technologies, Inc. | Mit metallischem Film überzogener Schaumstoffkontakt |
KR101440341B1 (ko) * | 2012-09-27 | 2014-09-15 | 앰코 테크놀로지 코리아 주식회사 | 반도체 장치 및 그 제조 방법 |
US10276402B2 (en) * | 2016-03-21 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and manufacturing process thereof |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5470787A (en) * | 1994-05-02 | 1995-11-28 | Motorola, Inc. | Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same |
US5466635A (en) * | 1994-06-02 | 1995-11-14 | Lsi Logic Corporation | Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating |
JPH0845938A (ja) * | 1994-07-27 | 1996-02-16 | Toshiba Corp | 半導体装置及びその製造方法 |
US5937320A (en) * | 1998-04-08 | 1999-08-10 | International Business Machines Corporation | Barrier layers for electroplated SnPb eutectic solder joints |
-
1998
- 1998-01-30 US US09/015,956 patent/US6107180A/en not_active Expired - Lifetime
-
1999
- 1999-01-15 TW TW088100601A patent/TW419805B/zh not_active IP Right Cessation
- 1999-01-27 JP JP01856099A patent/JP4334647B2/ja not_active Expired - Fee Related
- 1999-01-27 KR KR1019990002501A patent/KR100632712B1/ko not_active IP Right Cessation
- 1999-01-28 CN CNB991016068A patent/CN1154167C/zh not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100382291C (zh) * | 2005-05-17 | 2008-04-16 | 矽品精密工业股份有限公司 | 半导体装置及其制法 |
CN106356352A (zh) * | 2016-10-27 | 2017-01-25 | 江苏科技大学 | 一种凸点下金属化层构件及制备方法 |
Also Published As
Publication number | Publication date |
---|---|
JPH11274200A (ja) | 1999-10-08 |
KR19990068153A (ko) | 1999-08-25 |
KR100632712B1 (ko) | 2006-10-13 |
TW419805B (en) | 2001-01-21 |
US6107180A (en) | 2000-08-22 |
CN1154167C (zh) | 2004-06-16 |
JP4334647B2 (ja) | 2009-09-30 |
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