EP0398485A1 - A method of making a Flip Chip Solder bond structure for devices with gold based metallisation - Google Patents

A method of making a Flip Chip Solder bond structure for devices with gold based metallisation Download PDF

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Publication number
EP0398485A1
EP0398485A1 EP90303603A EP90303603A EP0398485A1 EP 0398485 A1 EP0398485 A1 EP 0398485A1 EP 90303603 A EP90303603 A EP 90303603A EP 90303603 A EP90303603 A EP 90303603A EP 0398485 A1 EP0398485 A1 EP 0398485A1
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EP
European Patent Office
Prior art keywords
solder
metallisation
flip
barrier
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP90303603A
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German (de)
French (fr)
Other versions
EP0398485B1 (en
Inventor
David John Pedder
David John Warner
Kim Louise Pickering
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Electronics Ltd
Original Assignee
Plessey Overseas Ltd
GEC Marconi Ltd
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Priority claimed from GB8911147A external-priority patent/GB2228825B/en
Application filed by Plessey Overseas Ltd, GEC Marconi Ltd filed Critical Plessey Overseas Ltd
Publication of EP0398485A1 publication Critical patent/EP0398485A1/en
Application granted granted Critical
Publication of EP0398485B1 publication Critical patent/EP0398485B1/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/001—Interlayers, transition pieces for metallurgical bonding of workpieces
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    • G—PHYSICS
    • G02—OPTICS
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Definitions

  • the present invention relates to a flip-chip solder bond arrangement.
  • Flip-chip solder bonding is now attracting significant attention as a means of providing very high density, area interconnections between a chip and a substrate, as a bonding technique with very attractive electrical characteristics (low inductance and capacitance) for high speed electronic devices and as a method of achieving very precise alignment and separation of components for micro-optical or related application.
  • Examples of specific applications include solder bonded thermal detector - silicon circuit hybrids for IR detection and imaging, high 'lead' count VLSI silicon ICs, flip-chip bonded GaAs devices for microwave applications and solder bonded, V-grooved silicon micro-benches for optical fibre alignment to an integrated optics (LiNbO3) substrate.
  • These devices all basically involve a 'chip' component and a 'substrate' component, both of which are provided with mating arrays of solderable metallisation pads (typically using CrCuAu multilayer metallisation), and either or both of which are provided with solder bumps over the solderable pads (typically using 95Pb:5Sn or 63Sn:37Pb solder (wt%)) as illustrated schematically in Figure 1.
  • solderable metallisation pads typically using CrCuAu multilayer metallisation
  • solder bumps over the solderable pads typically using 95Pb:5Sn or 63Sn:37Pb solder (wt%)
  • an integrated circuit chip 2 and a substrate component 4 (which may itself be a chip) each of which having on one surface thereof a registering array of solderable metallisation pads 6, 8, and either or both of which are provided with solder bumps 10 over the solderable pads.
  • the components 2, 4 are first aligned to within the accuracy required for the solder bumps 10 to contact the corresponding wettable pad 8 or bumps (within ⁇ 1/2 a pad diameter).
  • the assembly is then raised above the melting point of the solder involved under inert or reducing conditions.
  • the solder wets the wettable metallisation and surface tension forces then act to pull the two components into very accurate final alignment.
  • the bonded assembly is then cooled to form a solidly bonded hybrid device structure.
  • the final, equilibrium bond shape and spacing of the two components is controlled by the balance of surface tension and gravitational forces at the bonding temperature, and can readily be calculated for a regular array of circular bonds, knowing the individual solder bump volumes, wettable pad sizes, chip mass and solder surface tension.
  • the final solder bond geometry is that of a double truncated sphere, making calculation particularly straight forward.
  • the process of bonding is illustrated schematically in Figure 2.
  • solder to form the bumps may be applied over areas larger than that of the wettable metallisation, using a variety of masking techniques, to provide a controlled 'dewet' ratio and allow independent control of solder bump heights from a uniform solder coating thickness, as illustrated in Figure 3.
  • Gold is employed in such devices since it is untarnishable, uncorrodable and highly reliable and is therefore preferred since such devices are often employed for military applications where high precision is required.
  • Metallurgical interaction would also bring about a change in track geometry and the potential for formation of gold-tin intermetallics, lower melting point gold-lead phases and for joint embrittlement.
  • the present invention provides a flip-chip solder bonding arrangement including a semiconductor substrate having thereon layers of metallisation which have a tendency to interact with a solder material, forming on said layers of metallisation a barrier metallisation layer which is not reactive with said solder material, forming solder pads on the barrier layer and thereafter forming solder bonds with such solder pads employing said solder material.
  • layers of metallisation are formed of gold on III-V semiconductor components and a barrier layer preferably of chromium is formed on the metallisation layers.
  • the barrier layer is arranged so that its area is larger than the intended area for solder deposition.
  • the invention is principally concerned with gold, the present invention could equally well be applied to metallisation layers of silver and copper which have similar metallurgical properties to gold.
  • the problem does not usually arise with aluminium which is normally used for metallisation layers since aluminium will naturally form a self protective oxide coating.
  • Chromium is preferred for the barrier material, but other materials could be employed, for example titanium, tungsten, or mixtures thereof, in particular titanium-tungsten.
  • figure 4 shows a preferred embodiment of the invention wherein a substrate 40 of gallium arsenide has formed thereon gold metallisation layers 42.
  • a barrier layer 44 of solder-inert material in this instance chromium, 44 is formed on gold layer 42.
  • a solder wettable pad 46 is formed on barrier layer 44.
  • Solder pad 46 forms one pad of an array of pads positioned over the substrate 40, and a corresponding barrier layer portion 44 is provided, disposed beneath each pad 46.
  • a solder bump 48 of 95% lead, 5% tin composition is formed on solder pad 46. As shown in dotted lines, solder bump 48 in its initial state overlaps the solder pad 46 in order to provide a solder bump of the required dimensions.
  • solder bump is shown in full lines after it has been reflowed to make a solder bond where it has roughly the shape of a sphere extending from the solder pad 46. It will be understood that the material of the barrier layer, chromium, is non-wettable and therefore permits the use of different "dewet" ratios to achieve solder bump height control.
  • FIG. 5 A completed solder bond is shown in figure 5 wherein the structure of figure 4 is connected via solder bump 48 to a similar structure having a ceramic substrate 50, metallisation layers 52 of gold, a barrier metal layer 54 of chromium, and a solder pad 56.
  • barrier metallisation area A further criterion on the dimension of the barrier metallisation area is concerned with the alignment stage of flip-chip bonding process.
  • the barrier metallisation must be of sufficient area to prevent the solder bump on one component being in contact with gold tracks on the other component. This area is thus defined by the precision of the bonding and alignment equipment employed.
  • the material must not interact with solder, be producible in pin-hole free layers, and act as a good diffusion barrier to solder.
  • the barrier layer must also be non-­wettable to solder, so that dewetting can take place.
  • Chromium has been found to be effective as a barrier layer. This can be evaporated or sputtered, sputtering being the preferred method as it gives better low stress cover, good topography step coverage and good adhesion. Titanium may be a suitable alternative barrier metallisation to Cr.

Abstract

A flip-chip solder bonding arrangement including a semiconductor substrate (40) having thereon layers of metallisation (42, 44, 46) which have a tendency to interact with a solder material, forming on said layers of metallisation (42, 44, 46) a barrier metallisation layer (44) which is not reactive with said solder material, forming solder pads (46) on the barrier layer (44) and thereafter forming solder bonds (48) with such solder pads (46) employing said solder material.

Description

  • The present invention relates to a flip-chip solder bond arrangement.
  • Flip-chip solder bonding is now attracting significant attention as a means of providing very high density, area interconnections between a chip and a substrate, as a bonding technique with very attractive electrical characteristics (low inductance and capacitance) for high speed electronic devices and as a method of achieving very precise alignment and separation of components for micro-optical or related application. Examples of specific applications include solder bonded thermal detector - silicon circuit hybrids for IR detection and imaging, high 'lead' count VLSI silicon ICs, flip-chip bonded GaAs devices for microwave applications and solder bonded, V-grooved silicon micro-benches for optical fibre alignment to an integrated optics (LiNbO₃) substrate.
  • These devices all basically involve a 'chip' component and a 'substrate' component, both of which are provided with mating arrays of solderable metallisation pads (typically using CrCuAu multilayer metallisation), and either or both of which are provided with solder bumps over the solderable pads (typically using 95Pb:5Sn or 63Sn:37Pb solder (wt%)) as illustrated schematically in Figure 1.
  • Referring to Figure 1 an integrated circuit chip 2 and a substrate component 4 (which may itself be a chip) each of which having on one surface thereof a registering array of solderable metallisation pads 6, 8, and either or both of which are provided with solder bumps 10 over the solderable pads. To bond the two components, the components 2, 4 are first aligned to within the accuracy required for the solder bumps 10 to contact the corresponding wettable pad 8 or bumps (within ∼¹/₂ a pad diameter). The assembly is then raised above the melting point of the solder involved under inert or reducing conditions. The solder wets the wettable metallisation and surface tension forces then act to pull the two components into very accurate final alignment. The bonded assembly is then cooled to form a solidly bonded hybrid device structure. The final, equilibrium bond shape and spacing of the two components is controlled by the balance of surface tension and gravitational forces at the bonding temperature, and can readily be calculated for a regular array of circular bonds, knowing the individual solder bump volumes, wettable pad sizes, chip mass and solder surface tension. For large bond arrays with circular wettable pads and for low chip masses, the final solder bond geometry is that of a double truncated sphere, making calculation particularly straight forward. The process of bonding is illustrated schematically in Figure 2.
  • It should be noted that the solder to form the bumps may be applied over areas larger than that of the wettable metallisation, using a variety of masking techniques, to provide a controlled 'dewet' ratio and allow independent control of solder bump heights from a uniform solder coating thickness, as illustrated in Figure 3.
  • The use of 'dewet' has previously meant that the deposited solder has been in contact with aluminium or similar non-wettable metallisation, polyimide or oxide passivation, from all of which dewetting can take place.
  • However, recent work concentrating on the flip-chip bonding of III-V semiconductor devices onto ceramic substrates, using gold for low resistance microstrip tracks on device and substrate, has posed some problems.
  • Gold is employed in such devices since it is untarnishable, uncorrodable and highly reliable and is therefore preferred since such devices are often employed for military applications where high precision is required.
  • Attempts at reflow and bonding with solder in contact with gold would lead to metallurgical interactions (gold in contact with a 95% lead-tin solder would produce low melting point phases) producing an ill-defined solder contact area and a decrease in the volume of solder forming the truncated sphere, resulting in a disastrous loss of control of bump height.
  • Metallurgical interaction would also bring about a change in track geometry and the potential for formation of gold-tin intermetallics, lower melting point gold-lead phases and for joint embrittlement.
  • The present invention provides a flip-chip solder bonding arrangement including a semiconductor substrate having thereon layers of metallisation which have a tendency to interact with a solder material, forming on said layers of metallisation a barrier metallisation layer which is not reactive with said solder material, forming solder pads on the barrier layer and thereafter forming solder bonds with such solder pads employing said solder material.
  • Thus in a preferred arrangement layers of metallisation are formed of gold on III-V semiconductor components and a barrier layer preferably of chromium is formed on the metallisation layers. The barrier layer is arranged so that its area is larger than the intended area for solder deposition.
  • Although the invention is principally concerned with gold, the present invention could equally well be applied to metallisation layers of silver and copper which have similar metallurgical properties to gold. The problem does not usually arise with aluminium which is normally used for metallisation layers since aluminium will naturally form a self protective oxide coating.
  • Chromium is preferred for the barrier material, but other materials could be employed, for example titanium, tungsten, or mixtures thereof, in particular titanium-tungsten.
  • A preferred embodiment of the invention will now be described with reference to the accompanying drawings wherein:-
    • Figure 1 is a schematic diagram of the known flip-chip solder bonding process;
    • Figure 2 is a schematic view illustrating how a solder bump performs a self-aligning procedure during the formation of the solder bond;
    • Figure 3 illustrates a method by which the height of a solder bond is controlled;
    • Figure 4 illustrates a structure in accordance with a preferred embodiment of the invention; and,
    • Figure 5 shows a completed solder bond with two such structures as shown in figure 4.
  • Referring now to the drawings, figure 4 shows a preferred embodiment of the invention wherein a substrate 40 of gallium arsenide has formed thereon gold metallisation layers 42. A barrier layer 44 of solder-inert material in this instance chromium, 44 is formed on gold layer 42. A solder wettable pad 46 is formed on barrier layer 44. Solder pad 46 forms one pad of an array of pads positioned over the substrate 40, and a corresponding barrier layer portion 44 is provided, disposed beneath each pad 46. A solder bump 48 of 95% lead, 5% tin composition is formed on solder pad 46. As shown in dotted lines, solder bump 48 in its initial state overlaps the solder pad 46 in order to provide a solder bump of the required dimensions. The solder bump is shown in full lines after it has been reflowed to make a solder bond where it has roughly the shape of a sphere extending from the solder pad 46. It will be understood that the material of the barrier layer, chromium, is non-wettable and therefore permits the use of different "dewet" ratios to achieve solder bump height control.
  • A completed solder bond is shown in figure 5 wherein the structure of figure 4 is connected via solder bump 48 to a similar structure having a ceramic substrate 50, metallisation layers 52 of gold, a barrier metal layer 54 of chromium, and a solder pad 56.
  • A further criterion on the dimension of the barrier metallisation area is concerned with the alignment stage of flip-chip bonding process. The barrier metallisation must be of sufficient area to prevent the solder bump on one component being in contact with gold tracks on the other component. This area is thus defined by the precision of the bonding and alignment equipment employed.
  • To be effective as a barrier layer, the material must not interact with solder, be producible in pin-hole free layers, and act as a good diffusion barrier to solder. The barrier layer must also be non-­wettable to solder, so that dewetting can take place.
  • Chromium has been found to be effective as a barrier layer. This can be evaporated or sputtered, sputtering being the preferred method as it gives better low stress cover, good topography step coverage and good adhesion. Titanium may be a suitable alternative barrier metallisation to Cr.
  • Utilisation of barrier metal technology has meant that it has been possible to exploit flip-chip solder bonding for MMIC devices where Au is used as a track material. Working devices have been produced by flip-chip bonding a GaAs IC containing active elements, to hybrid circuits on alumina and other microwave ceramic substrates carrying interconnects and frequency selective elements.

Claims (6)

1. A flip-chip solder bonding arrangement including a semiconductor substrate having thereon layers of metallisation which have a tendency to interact with a solder material, forming on said layers of metallisation a barrier metallisation layer which is not reactive with said solder material, forming solder pads on the barrier layer and thereafter forming solder bonds with such solder pads employing said solder material.
2. A flip-chip solder bonding arrangement according to claim 1 wherein the metallisation layers are formed of gold.
3. A flip-chip solder bonding arrangement according to claim 1 wherein the barrier metallisation layer is formed of chromium.
4. A flip-chip solder bonding arrangement according to claim 1 wherein the barrier metallisation layer is formed of titanium, tungsten or titanium-tungsten.
5. A flip-ship solder bonding arrangement according to any preceding claim wherein a separate barrier metallisation portion is provided for each solder pad of an array of solder pads formed on the substrate, each barrier metallisation portion being dimensioned so as to receive the solder pad and a solder bump formed thereon, which may have greater lateral dimensions than the respective solder pad.
6. A flip-chip solder bonding arrangement substantially as described with reference to figures 4 and 5 of the accompanying drawings.
EP90303603A 1989-05-16 1990-04-04 A method of making a Flip Chip Solder bond structure for devices with gold based metallisation Expired - Lifetime EP0398485B1 (en)

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GB8911147A GB2228825B (en) 1989-02-03 1989-05-16 A method of making a flip chip solder bonding device
GB8911147 1989-05-16

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EP0685857A1 (en) * 1994-06-03 1995-12-06 Plessey Semiconductors Limited Inductor chip device
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EP0507718A1 (en) * 1991-04-04 1992-10-07 International Business Machines Corporation Low lead content Pb-Sn-Ag-Sb solder alloy useful in an interconnect metallization structure
EP0685857A1 (en) * 1994-06-03 1995-12-06 Plessey Semiconductors Limited Inductor chip device
EP0690460A1 (en) * 1994-06-30 1996-01-03 Plessey Semiconductors Limited Multi-chip module inductor structures
US5747870A (en) * 1994-06-30 1998-05-05 Plessey Semiconductors Limited Multi-chip module inductor structure
EP0694933A1 (en) * 1994-07-29 1996-01-31 Plessey Semiconductors Limited Trimmable inductor structure
EP0694932A1 (en) * 1994-07-29 1996-01-31 Plessey Semiconductors Limited Inductor device
US6005466A (en) * 1994-07-29 1999-12-21 Mitel Semiconductor Limited Trimmable inductor structure
EP0717441A3 (en) * 1994-12-13 1997-05-02 At & T Corp Method of solder bonding a body, e.g. a silicon chip, to another body
EP0724930A1 (en) * 1995-02-01 1996-08-07 Alcatel N.V. Device comprising solder bumps formed on a substrate and process for producing these solder bumps
FR2729878A1 (en) * 1995-02-01 1996-08-02 Alcatel Nv DEVICE COMPRISING WELDING PLOTS FORMED ON A SUBSTRATE AND METHOD OF MANUFACTURING SUCH WELDING PLOTS
WO1996026808A1 (en) * 1995-03-01 1996-09-06 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Metallised under-layer for (soldering) filler materials
NL1003207C2 (en) * 1995-05-30 1997-06-24 Motorola Inc A method of manufacturing a flip chip semiconductor device with an inductor.
FR2745120A1 (en) * 1996-02-15 1997-08-22 Solaic Sa IC with especially aluminium pad covered by barrier layer
EP1696253A2 (en) * 2005-02-24 2006-08-30 Northrop Grumman Corporation Accurate relative alignment and epoxy-free attachment of optical elements
EP1696253A3 (en) * 2005-02-24 2006-11-08 Northrop Grumman Corporation Accurate relative alignment and epoxy-free attachment of optical elements

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EP0398485B1 (en) 1995-08-09
DE69021438T2 (en) 1996-01-25
DE69021438D1 (en) 1995-09-14
JPH03101242A (en) 1991-04-26
US5108027A (en) 1992-04-28

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