DE69021438T2 - Method for producing a flip-chip solder structure for arrangements with gold metallization. - Google Patents
Method for producing a flip-chip solder structure for arrangements with gold metallization.Info
- Publication number
- DE69021438T2 DE69021438T2 DE69021438T DE69021438T DE69021438T2 DE 69021438 T2 DE69021438 T2 DE 69021438T2 DE 69021438 T DE69021438 T DE 69021438T DE 69021438 T DE69021438 T DE 69021438T DE 69021438 T2 DE69021438 T2 DE 69021438T2
- Authority
- DE
- Germany
- Prior art keywords
- solder
- wettable
- pads
- metallization
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910000679 solder Inorganic materials 0.000 title claims description 72
- 239000010931 gold Substances 0.000 title claims description 22
- 238000001465 metallisation Methods 0.000 title claims description 22
- 229910052737 gold Inorganic materials 0.000 title claims description 17
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 230000004888 barrier function Effects 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 229910052804 chromium Inorganic materials 0.000 claims description 10
- 239000011651 chromium Substances 0.000 claims description 10
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011324 bead Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000001842 Brominated vegetable oil Substances 0.000 description 1
- 229910003327 LiNbO3 Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000012754 barrier agent Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- UCHOFYCGAZVYGZ-UHFFFAOYSA-N gold lead Chemical compound [Au].[Pb] UCHOFYCGAZVYGZ-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/001—Interlayers, transition pieces for metallurgical bonding of workpieces
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
- G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
- G02B6/4232—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using the surface tension of fluid solder to align the elements, e.g. solder bump techniques
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Description
Die vorliegende Erfindung betrifft ein Verfahren zur Herstellung einer Flip- Chip-Lötvorrichtung.The present invention relates to a method for manufacturing a flip-chip soldering device.
Das Flip-Chip-Verlöten zieht zur Zeit als ein Mittel, Flächenverbindungen zwischen einem Chip und einem Substrat bereitzustellen, als Verbindungsverfahren mit sehr attraktiven elektrischen Eigenschaften (niedriger Induktivität und Kapazität) für elektronische Hochgeschwindigkeitsvorrichtungen und als ein Verfahren, um eine sehr genaue Ausrichtung und Trennung der Komponenten für mikrooptische oder verwandte Anwendungen zu erzielen, bedeutende Aufmerksamkeit auf sich. Beispiele spezieller Anwendungen beinhalten gelötete thermische Detektor-Siliciumhybridschaltungen für die IR-Aufnahme und Abbildung, Silicium-integrierte Schaltungen mit großen Anschlußzahlen und sehr hohem Intergrationsgrad (VLSI), Flip- Chip-verbundene GaAs-Vorrichtungen für Mikrowellenanwendungen und verlötete, mit V-förmigen Vertiefungen versehene Silicium Mikrotische zur Ausrichtung von Lichtwellenleitern auf ein Substrat der integrierten Optik (LiNbO&sub3;).Flip-chip soldering is currently attracting significant attention as a means of providing surface connections between a chip and a substrate, as an interconnection method with very attractive electrical properties (low inductance and capacitance) for high-speed electronic devices, and as a method of achieving very precise alignment and separation of components for micro-optical or related applications. Examples of specific applications include soldered thermal detector silicon hybrid circuits for IR sensing and imaging, very high-lead silicon integrated circuits (VLSI), flip-chip connected GaAs devices for microwave applications, and soldered V-welled silicon microstages for aligning optical fibers to an integrated optics substrate (LiNbO3).
Alle diese Vorrichtungen beinhalten grundsätzlich eine 'Chip'-Komponente und eine 'Substrat'-Komponente, die beide mit passenden Feldern lötbarer Metallisierungspolster (normalerweise wird eine CrCuAu-Mehrschichtmetallisierung verwendet) versehen sind, und von denen eines oder beide mit erhöhten Kontaktflecken aus Lötmetall über den lötbaren Polstern versehen ist oder sind (normalerweise wird ein Lötmetall verwendet, das in Gewichtsprozent 95pb:5Sn oder 63Sn:37Pb enthält), wie es in Figur 1 dargestellt ist.All such devices basically include a 'chip' component and a 'substrate' component, both of which are provided with matching fields of solderable metallization pads (typically CrCuAu multilayer metallization is used), and one or both of which is provided with raised pads of solder over the solderable pads (typically a solder containing 95pb:5Sn or 63Sn:37Pb by weight) as shown in Figure 1.
In Figur 1 haben ein Chip 2 mit einer integrierten Schaltung und eine Substratkomponente 4 (die selbst ein Chip sein kann) jeweils auf einer ihrer Oberflächen ein Aufnahmefeld aus verlötbaren Metallisierungspolstern 6, 8, und eines oder beide sind mit erhöhten Kontaktflecken aus Lötmetall 10 über den verlötbaren Polstern versehen. Um die beiden Komponenten zu verbinden, werden die Komponenten 2, 4 zunächst mit einer Genauigkeit ausgerichtet, die erforderlich ist, so daß die erhöhten Kontaktflecke aus Lötmetall 10 die entsprechenden benetzbaren Polster 8 oder erhöhten Kontaktflecke (innerhalb ~1/2 Polsterdurchmesser) berühren. Die Anordnung wird anschließend über den Schmelzpunkt des Lötmetalls unter inerten oder reduzierenden Bedingungen erhitzt. Das Lötmetall benetzt das benetzbare Metallisierungspolster und Oberflächenspannungskräfte bewirken dann, daß die zwei Komponenten in eine sehr exakte Endausrichtung gezogen werden. Die verbundene Anordnung wird dann abgekühlt, um eine fest verbundene Hybridstrukturvorrichtung zu bilden. Die endgültige Gleichgewichtsverbindungsform und der Abstand der beiden Komponenten wird durch den Ausgleich der Oberflächenspannungs- und Gravitationskräfte bei den Verbindungstemperaturen gesteuert und kann ohne weiteres für ein regelmäßiges Feld aus kreisförmigen Bindungen berechnet werden, wenn die einzelnen Volumina der erhöhten Kontaktflecke aus Lötmetall, die Abmessungen der benetzbaren Polster, die Masse des Chips und die Oberflächenspannung des Lötmetalls bekannt sind. Bei großen Verbindungsfeldern mit kreisförmigen, benetzbaren Polstern und bei geringen Chipmassen entspricht die Geometrie der endgültigen Lötverbindung einer beidseitig abgestumpften Kugel, wodurch die Berechnung besonders einfach wird. Der Verbindungsvorgang ist schematisch in Figur 2 dargestellt.In Figure 1, an integrated circuit chip 2 and a substrate component 4 (which may itself be a chip) each have on one of their surfaces a receiving field of solderable metallization pads 6, 8, and one or both are provided with raised contact pads of solder 10 above the solderable pads. To connect the two components, the components 2, 4 are first aligned with a precision required so that the raised solder pads 10 contact the corresponding wettable pads 8 or raised pads (within ~1/2 pad diameter). The assembly is then heated above the melting point of the solder under inert or reducing conditions. The solder wets the wettable metallization pad and surface tension forces then act to pull the two components into a very precise final alignment. The bonded assembly is then cooled to form a tightly bonded hybrid structural device. The final equilibrium bond shape and spacing of the two components is controlled by the balance of surface tension and gravitational forces at the bond temperatures and can be readily calculated for a regular field of circular bonds if the individual volumes of the raised solder pads, the dimensions of the wettable pads, the mass of the chip, and the surface tension of the solder are known. For large connection fields with circular, wettable pads and for low chip masses, the geometry of the final solder connection corresponds to a truncated sphere on both sides, which makes the calculation particularly simple. The connection process is shown schematically in Figure 2.
Es sollte angemerkt werden, daß das Lötmetall, damit es die erhöhten Kontaktflecke bildet, über Bereiche aufgebracht werden kann, die größer sind als die benetzbare Metallisierung, wobei eine Vielzahl unterschiedlicher Maskierungstechniken verwendet wird, um ein definiertes 'Abperl'-Verhältnis bereitzustellen und eine unabhängige Steuerung der Höhen der erhöhten Kontaktflecke aus Lötmetall über einer Lötbeschichtung mit einer gleichmäßigen Dicke bereitzustellen, wie es in Figur 3 dargestellt ist.It should be noted that the solder to form the raised pads can be deposited over areas larger than the wettable metallization using a variety of different masking techniques to provide a defined 'beading' ratio and to provide independent control of the heights of the raised solder pads over a solder coating of uniform thickness, as shown in Figure 3.
Die Verwendung von 'Abperlen' oben hat bedeutet, daß das aufgebrachte Lötmetall in Kontakt mit Aluminium oder eine ähnliche nicht-benetzbare Metallisierung, ein Polyimid oder eine Oxidpassivierung gebracht worden ist, von denen allen ein Abperlen erfolgen kann.The use of 'beading' above has meant that the deposited solder has been brought into contact with aluminum or a similar non-wettable metallization, polyimide or oxide passivation, all of which can bead up.
Jedoch haben die kürzlich durchgeführten Arbeiten, die sich auf die Flip-Chip- Verbindung von III-V-Halbleitern auf keramische Substraten konzentrieren, wobei Gold für Mikrostripbahnen mit geringem Widerstand auf Vorrichtungen und Substraten verwendet werden, einige Probleme aufgezeigt.However, recent work focusing on flip-chip interconnection of III-V semiconductors on ceramic substrates, using gold for low resistance microstrip lines on devices and substrates, has highlighted some problems.
Gold wird in derartigen Vorrichtungen verwendet, da es nicht anlaufen, nicht korridieren kann und hochgradig zuverlässig ist und daher bevorzugt ist, da derartige Vorrichtungen häufig für Anwendungen im Militärbereich eingesetzt werden, wo eine hohe Genauigkeit erforderlich ist.Gold is used in such devices because it does not tarnish, does not corrode and is highly reliable and is therefore preferred as such devices are often used in military applications where high accuracy is required.
Rückfluß- und Lötversuche mit Lötmetall in Kontakt mit Gold würden zu einer metallurgischen Wechselwirkung führen (Gold in Kontakt mit einem 95%-igen Blei-Zinn-Lötmetall würde zu Phasen mit niedrigem Schmelzpunkt führen), die einen schlecht bestimmten Lötkontaktbereich und eine Abnahme des Volumens an Lötmetall verursacht, das die abgestumpfte Kugel bildet, was zu einer katastrophalen Verschlechterung der Höheneinstellung der erhöhten Kontaktflecke führen würde.Reflow and soldering attempts with solder in contact with gold would result in a metallurgical interaction (gold in contact with a 95% lead-tin solder would result in low melting point phases) causing a poorly defined solder contact area and a decrease in the volume of solder forming the truncated ball, leading to a catastrophic deterioration of the height adjustment of the raised contact pads.
Metallurgische Wechselwirkungen würden ebenfalls eine Veränderung der Bahngeometrie und die Möglichkeit einer Bildung von intermetallischen Verbindungen aus Gold und Zinn, Gold-Blei-Phasen mit einem niedrigeren Schmelzpunkt und eine Versprödung der Verbindung mit sich bringen.Metallurgical interactions would also cause a change in the orbital geometry and the possibility of formation of intermetallic compounds of gold and tin, gold-lead phases with a lower melting point and embrittlement of the compound.
Intersoc. conf. Thermal Phenomena in fab. and operation of elect. comp., I-therm'88, Los Angeles CA, 11.-13. Mai 1988, Seite 67-70, beschreibt die thermische Stabilität von BLM-Schichten (ball-limited-metal layers), die durch den gesteuerten Zusammenfall von erhöhten Kontaktflecken aus Lötmetall (Blei-5 Gew.-% Zinn) für Flip-Chip-Verbindungen gebildet werden. Alle BLM-Schichten bestehen aus einer dreifachen Schichtablagerung von Cr oder Ti als Häftschicht, Ni, Mo, Pd oder Pt als Sperrschicht und Au als Oberflächenmetall.Intersoc. conf. Thermal Phenomena in fab. and operation of elect. comp., I-therm'88, Los Angeles CA, May 11-13, 1988, pages 67-70, describes the thermal stability of ball-limited-metal layers (BLM) formed by the controlled collapse of raised pads of solder (lead-5 wt% tin) for flip-chip interconnects. All BLM layers consist of a triple layer deposition of Cr or Ti as an adhesion layer, Ni, Mo, Pd or Pt as a barrier layer and Au as a surface metal.
Pat. Abs. Jap., Vol. 4, Nr. 44 (E-005), 5/4/80 (JP-A-55152235) offenbart Dünnfilmschaltungen, in denen Cr und Au auf ein Aluminiumsubstrat aufgebracht sind und ein gewünschtes Muster im Spiegelbild eingeätzt wird, um einen Dünnfilmdrahtleiter herzustellen. Mit Hilfe einer Schutzmaske wird Nickel als Lötmetall-Diffusionssperrschicht auf dem Au abgeschieden. Anschließend wird wieder mit Cu und Lötmetall beschichtet, indem die Maske auf dem Nickel des Verbindungsanschlusses verwendet wird, um einen Schutz zu entfernen. Wenn das Lötmetall aufgelöst werden kann, indem der Dünnfilmschaltkreis erhitzt wird, bleibt das Lötmetall an dem Ort des Verbindungsanschlusses und fließt nicht auf das Gold aus. Diese Lötverbindung kann mit Au erfolgen. Das Metall für die Lötmetall-Diffuionssperrschicht beinhaltet Ni. Ti, Mo, W und Ta als Sperrmittel. Sn, Cu, Pb, Zn, Ag werden als das Metall mit guten Eigenschaften für Lötanwendungen eingesetzt.Pat. Abs. Jap., Vol. 4, No. 44 (E-005), 5/4/80 (JP-A-55152235) discloses thin film circuits in which Cr and Au are deposited on an aluminum substrate and a desired pattern is etched in mirror image to produce a thin film wire conductor. By means of a protective mask, nickel as solder diffusion barrier layer deposited on the Au. Then Cu and solder are coated again by using the mask on the nickel of the connection terminal to remove a protection. If the solder can be dissolved by heating the thin film circuit, the solder will stay at the connection terminal location and will not flow out to the gold. This solder joint can be made with Au. The metal for the solder diffusion barrier layer includes Ni. Ti, Mo, W and Ta as barrier agents. Sn, Cu, Pb, Zn, Ag are used as the metal with good properties for soldering applications.
WO-A-8701509 offenbart einen Flip-Chip-Verbindungsvorgang, in dem es erforderlich ist, daß ein Chip genau auf einer Linie mit einem Muster aus elektrischen Verbindungspads auf einem Substratkörper liegt. Elektrische Verbindungen zwischen dem Chip und dem Polster auf dem Körper werden durch erhöhte Kontaktflecke aus Lötmetall gebildet, die verschmolzen werden, um die Verbindungen beständig zu machen. Das Verfahren stellt Vorrichtungen bereit, um den Chip genau auszurichten, indem die Oberflächenspannungskräfte, die in den Lötmetallbereichen auftreten, ausgenutzt werden. Eine Lötmetallkugel mit einem Durchmesser von 40 um sorgt für eine entsprechende Kraft für die Ausrichtung und erlaubt Lötverbindungen mit einem geringeren Durchmesser zwischen zwei Komponenten exakt auszurichten.WO-A-8701509 discloses a flip chip bonding process in which a chip is required to lie precisely in line with a pattern of electrical bonding pads on a substrate body. Electrical connections between the chip and the pad on the body are formed by raised pads of solder which are fused to make the connections permanent. The process provides means to precisely align the chip by taking advantage of the surface tension forces present in the solder areas. A 40 µm diameter solder ball provides adequate alignment force and allows smaller diameter solder joints between two components to be precisely aligned.
Pat. Abs. Jap., Vol. 10. Nr. 293 (E-443) 4/10/86 (JP-A-61111550) beschreibt eine Dünnfilmvorrichtung, in der eine Anschlußverdrahtung aus leitfähigem Metall, wie Titan oder Chrom gefertigt ist, die eine ausgezeichnete Haftfähigkeit mit einem isolierenden Substrat hat und sich nicht in weiches Lötmetall einfügt. Eine Verbindungsverdrahtung ist aus Au oder ähnlichem, einem leitfähigen Metall, das sich in weiches Lötmetall einfügt und gegen Korrosion beständig ist, gefertigt. Die Verbindungsanordnung ist mit runden Verbindungssitzen an Teilen versehen, die den erhöhten Kontaktflecken eines Chips entsprechen, der mit "Kontaktflecken" an diesen Verbindungssitzen angebracht ist und mit diesen Teilen durch Wärmeverschmelzung der erhöhten Kontaktflecke verbunden ist.Pat. Abs. Jap., Vol. 10. No. 293 (E-443) 4/10/86 (JP-A-61111550) describes a thin film device in which a connecting wiring is made of conductive metal, such as titanium or chromium, which has excellent adhesiveness with an insulating substrate and does not blend with soft solder. A connecting wiring is made of Au or the like, a conductive metal which blends with soft solder and is resistant to corrosion. The connecting assembly is provided with round connecting seats at parts corresponding to raised contact pads of a chip, which is attached with "contact pads" to these connecting seats and connected to these parts by heat fusion of the raised contact pads.
Erfindungsgemäß ist ein Verfahren zur Herstellung einer Flip-Chip-Lötverbindungsvorrichtung vorgesehen, das die Schritte beinhaltet, ein III-V-Halbleitersubstrat bereitzustellen, das auf dem Substrat eine Metallisierungsschicht eines Metalls bildet, das aus der Gruppe ausgewählt ist, die aus Gold, Silber und Kupfer besteht, auf der Metallisierungsschicht eine Sperrschicht aus einem nicht benetzbaren Lötmetall zu bilden, das aus der Gruppe ausgewählt ist, die aus Chrom, Titan, Wolfram und Titan-Wolfram besteht, benetzbare Lötpolster auf der Sperrschicht zu bilden, und anschließend auf jedem dieser benetzbaren Lötpolster einen erhöhten Kontaktfleck aus Lötmetall zu bilden, der größere seitliche Abmessungen als die jeweiligen benetzbaren Lötpolster hat.According to the invention, a method for manufacturing a flip-chip solder connection device is provided, which includes the steps of a III-V semiconductor substrate forming on the substrate a metallization layer of a metal selected from the group consisting of gold, silver and copper, forming on the metallization layer a barrier layer of a non-wettable solder metal selected from the group consisting of chromium, titanium, tungsten and titanium-tungsten, forming wettable solder pads on the barrier layer, and then forming on each of these wettable solder pads a raised contact pad of solder metal having larger lateral dimensions than the respective wettable solder pads.
Folglich bestehen die Metallisierungsschichten in einer bevorzugen Anordnung aus Gold auf III-V-Halbleiterkomponenten und eine Sperrschicht, bevorzugt aus Chrom. ist auf den Metallisierungsschichten ausgebildet. Die Sperrschicht ist derart angeordnet, daß ihre Fläche größer als die Fläche ist, auf die Lötmetall aufgebracht werden soll.Thus, in a preferred arrangement, the metallization layers consist of gold on III-V semiconductor components and a barrier layer, preferably of chromium, is formed on the metallization layers. The barrier layer is arranged such that its area is larger than the area to which solder is to be applied.
Obwohl sich die Erfindung prinzipiell mit Gold befaßt, kann die Erfindung gleichermaßen gut auf Metallisierungsschichten aus Silber und Kupfer angewendet werden, die vergleichbare metallurgische Eigenschaften wie Gold haben. Das Problem tritt gewöhnlich nicht bei Aluminium auf, das normalerweise als Metallisierungsschicht verwendet wird, da Aluminium auf natürliche Weise eine selbstschützende Oxidschicht ausbildet.Although the invention principally deals with gold, the invention can be equally well applied to metallization layers of silver and copper, which have comparable metallurgical properties to gold. The problem does not usually occur with aluminum, which is normally used as a metallization layer, since aluminum naturally forms a self-protecting oxide layer.
Eine bevorzugte Ausführungsform der Erfindung wird nun anhand der beiliegenden Zeichnungen beschrieben, wobeiA preferred embodiment of the invention will now be described with reference to the accompanying drawings, in which
Figur 1 eine schematische Darstellung des bekannten Flip-Chip-Verbindungsverfahrens ist,Figure 1 is a schematic representation of the known flip-chip connection method,
Figur 2 eine schematische Ansicht ist, die darstellt, wie ein erhöhter Kontaktfleck aus Lötmetall einen selbstausrichtenden Vorgang während der Bildung der Lötverbindung bewirkt,Figure 2 is a schematic view illustrating how a raised pad of solder causes a self-aligning process during the formation of the solder joint,
Figur 3 ein Verfahren darstellt, durch das die Höhe einer Lötverbindung gesteuert wird,Figure 3 illustrates a method by which the height of a solder joint is controlled,
Figur 4 eine Struktur gemäß einer bevorzugten Ausführungsform der Erfindung darstellt undFigure 4 shows a structure according to a preferred embodiment of the invention and
Figur 5 eine vollständige Lötverbindung mit zwei wie in Figur 4 dargestellten Strukturen zeigt.Figure 5 shows a complete solder joint with two structures as shown in Figure 4.
Von den Figuren zeigt Figur 4 eine bevorzugte Ausführungsform der Erfindung, wobei auf einem Substrat 40 aus Galliumarsenid eine Goldmetallisierungsschicht 42 ausgebildet ist. Eine Sperrschicht 44 aus einem Material, das gegenüber Lötmetall inert ist, in diesem Fall Chrom, ist auf der Goldschicht 42 ausgebildet. Ein benetzbares Lötpolster 46 ist auf der Sperrschicht 44 ausgebildet. Das Lötmetallpolster 46 bildet ein Polster eines Feldes aus Polstern, die über dem Substrat 40 ausgebildet sind, und unter jedem Polster 46 angeordnet ist ein entsprechender Sperrschichtbereich 44 vorgesehen. Eine Lötmetallkugel 48 aus einer Zusammensetzung aus 95 % Blei und 5 % Zinn wird auf dem Lötpolster 46 ausgebildet. Wie in gestrichelten Linien dargestellt ist, überlappt der erhöhte Kontaktfleck aus Lötmetall 48 in seinem Ausgangszustand das Lötpolster 46, so daß ein Lötpolster mit den erforderlichen Abmessungen bereitgestellt wird. Das Lötpolster ist in durchgezogenen Linien dargestellt, nachdem es zurückgeflossen ist, um eine Lötverbindung bereitzustellen, die ungefähr die Form einer Kugel hat, die sich von dem Lötpolster 46 erstreckt. Es versteht sich, daß das Material der Sperrschicht Chrom, nicht benetzbar ist und es daher erlaubt, daß verschiedene 'Abperl'-Verhältnisse dazu genutzt werden, um eine Einstellung der Höhe des erhöhten Kontaktflecks aus Lötmetall zu erreichen.Of the figures, Figure 4 shows a preferred embodiment of the invention, wherein a gold metallization layer 42 is formed on a substrate 40 of gallium arsenide. A barrier layer 44 of a material inert to solder, in this case chromium, is formed on the gold layer 42. A wettable solder pad 46 is formed on the barrier layer 44. The solder pad 46 forms one pad of an array of pads formed over the substrate 40, and a corresponding barrier layer region 44 is provided beneath each pad 46. A solder ball 48 of a composition of 95% lead and 5% tin is formed on the solder pad 46. As shown in dashed lines, the raised pad of solder 48 in its initial state overlaps the solder pad 46, thus providing a solder pad of the required dimensions. The solder pad is shown in solid lines after it has reflowed to provide a solder joint that is approximately in the shape of a ball extending from the solder pad 46. It will be understood that the barrier layer material, chromium, is non-wettable and therefore allows different 'beading' ratios to be used to achieve adjustment of the height of the raised pad of solder.
Eine vollständige Lötverbindung ist in Figur 5 gezeigt, in der die Struktur aus Figur 4 über einen erhöhten Kontaktfleck aus Lötmetall 48 mit einer ähnlichen Struktur verbunden ist, die ein Substrat 50, Metallisierungsschichten 52 aus Gold, eine Sperrmetallschicht 54 und ein Lötpolster 56 aufweist.A completed solder joint is shown in Figure 5, in which the structure of Figure 4 is connected via a raised solder pad 48 to a similar structure comprising a substrate 50, gold metallization layers 52, a barrier metal layer 54, and a solder pad 56.
Ein weiteres Kriterium für die Abmessungen des Sperrschichtmetalllsierungsbereiches steht im Zusammenhang mit dem Ausrichtungsschritt des Flip-Chip-Verbindungsverfahrens. Die Sperrschichtmetallisierung muß eine ausreichend große Fläche haben, um zu verhindern, daß sich der erhöhte Kontaktfleck aus Lötmetall aus einer Komponente in Kontakt mit der Goldbahn auf der anderen Komponente befindet. Dieser Bereich ist demzufolge durch die Genauigkeit der Bildung und des verwendeten Ausrichtungszubehörs bestimmt.Another criterion for the dimensions of the barrier metallization area is related to the alignment step of the flip-chip interconnection process. The barrier metallization must have a sufficiently large area to prevent the raised pad of solder from moving out of a component in contact with the gold track is on the other component. This range is therefore determined by the accuracy of the formation and the alignment accessories used.
Um eine wirksame Sperrschicht zu bilden darf das Material nicht mit Lötmetall in Wechselwirkung treten, muß in Schichten herstellbar sein, die frei von Defekten sind, und als gute Diffusionssperrschicht gegenüber Lötmetall wirken. Die Sperrschicht darf ebenfalls nicht durch Lötmetall benetzbar sein, so daß ein Abperlen erfolgen kann.In order to form an effective barrier layer, the material must not interact with solder, must be able to be produced in layers that are free of defects and must act as a good diffusion barrier layer against solder. The barrier layer must also not be wettable by solder so that it can bead up.
Es hat sich herausgestellt, daß Chrom eine wirksame Sperrschicht ist. Es kann verdampft oder aufgesprüht werden, wobei das Aufsprühverfahren bevorzugt ist, da es eine bessere Beschichtung mit niedriger Spannung, eine gute Bedeckung topographischer Stufen und eine gute Haftung ergibt. Titan kann eine geeignete alternative Metallisierungsschicht zu Chrom sein.Chromium has been found to be an effective barrier layer. It can be evaporated or sprayed, with the spraying method being preferred as it gives a better low voltage coating, good coverage of topographical steps and good adhesion. Titanium can be a suitable alternative metallization layer to chromium.
Der Einsatz der Sperrschichtmetall-Technologie hat bedeutet, daß es möglich war, Flip-Chip-Lötverbindungen für MMIC-Vorrichtungen auszunutzen, in denen Au als Bahnmaterial eingesetzt wird. Funktionsfähige Vorrichtungen sind hergestellt worden, indem ein GaAs-IC, das aktive Elemente enthält, mit Hybridschaltungen auf Aluminiumoxid und andere keramische Mikroowellensubstrate. die Verbindungen und Frequenzselektionselemente tragen, durch das Flip-Chip-Bindungsverfahren verbunden worden sind.The use of barrier metal technology has meant that it has been possible to exploit flip-chip solder connections for MMIC devices using Au as the trace material. Working devices have been made by bonding a GaAs IC containing active elements to hybrid circuits on alumina and other ceramic microwave substrates carrying interconnects and frequency selection elements by the flip-chip bonding technique.
Claims (2)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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GB8911147A GB2228825B (en) | 1989-02-03 | 1989-05-16 | A method of making a flip chip solder bonding device |
Publications (2)
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DE69021438D1 DE69021438D1 (en) | 1995-09-14 |
DE69021438T2 true DE69021438T2 (en) | 1996-01-25 |
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DE69021438T Expired - Fee Related DE69021438T2 (en) | 1989-05-16 | 1990-04-04 | Method for producing a flip-chip solder structure for arrangements with gold metallization. |
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US (1) | US5108027A (en) |
EP (1) | EP0398485B1 (en) |
JP (1) | JPH03101242A (en) |
DE (1) | DE69021438T2 (en) |
Families Citing this family (46)
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JPH0734997B2 (en) * | 1991-04-04 | 1995-04-19 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Metallized structure |
US5289631A (en) * | 1992-03-04 | 1994-03-01 | Mcnc | Method for testing, burn-in, and/or programming of integrated circuit chips |
US5470787A (en) * | 1994-05-02 | 1995-11-28 | Motorola, Inc. | Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same |
GB2290171B (en) * | 1994-06-03 | 1998-01-21 | Plessey Semiconductors Ltd | Inductor chip device |
GB2290913B (en) * | 1994-06-30 | 1998-03-11 | Plessey Semiconductors Ltd | Multi-chip module inductor structure |
GB2292016B (en) * | 1994-07-29 | 1998-07-22 | Plessey Semiconductors Ltd | Inductor device |
GB2292015B (en) * | 1994-07-29 | 1998-07-22 | Plessey Semiconductors Ltd | Trimmable inductor structure |
US5539153A (en) * | 1994-08-08 | 1996-07-23 | Hewlett-Packard Company | Method of bumping substrates by contained paste deposition |
US5468655A (en) * | 1994-10-31 | 1995-11-21 | Motorola, Inc. | Method for forming a temporary attachment between a semiconductor die and a substrate using a metal paste comprising spherical modules |
TW253856B (en) * | 1994-12-13 | 1995-08-11 | At & T Corp | Method of solder bonding, and article produced by the method |
FR2729878A1 (en) * | 1995-02-01 | 1996-08-02 | Alcatel Nv | DEVICE COMPRISING WELDING PLOTS FORMED ON A SUBSTRATE AND METHOD OF MANUFACTURING SUCH WELDING PLOTS |
JPH10506758A (en) * | 1995-03-01 | 1998-06-30 | フラオンホーファー ゲゼルシャフト ツール フェルデルング デル アンゲヴァンテン フォルシュング エー ファオ | Substrate with metal base of solder material |
US5541135A (en) * | 1995-05-30 | 1996-07-30 | Motorola, Inc. | Method of fabricating a flip chip semiconductor device having an inductor |
US5985692A (en) * | 1995-06-07 | 1999-11-16 | Microunit Systems Engineering, Inc. | Process for flip-chip bonding a semiconductor die having gold bump electrodes |
FR2745120A1 (en) * | 1996-02-15 | 1997-08-22 | Solaic Sa | IC with especially aluminium pad covered by barrier layer |
DE19606101A1 (en) * | 1996-02-19 | 1997-08-21 | Siemens Ag | Semiconductor body with solder material layer |
US6395991B1 (en) | 1996-07-29 | 2002-05-28 | International Business Machines Corporation | Column grid array substrate attachment with heat sink stress relief |
US5773897A (en) * | 1997-02-21 | 1998-06-30 | Raytheon Company | Flip chip monolithic microwave integrated circuit with mushroom-shaped, solder-capped, plated metal bumps |
US6293456B1 (en) | 1997-05-27 | 2001-09-25 | Spheretek, Llc | Methods for forming solder balls on substrates |
US6609652B2 (en) | 1997-05-27 | 2003-08-26 | Spheretek, Llc | Ball bumping substrates, particuarly wafers |
US7654432B2 (en) | 1997-05-27 | 2010-02-02 | Wstp, Llc | Forming solder balls on substrates |
US7007833B2 (en) * | 1997-05-27 | 2006-03-07 | Mackay John | Forming solder balls on substrates |
US7288471B2 (en) * | 1997-05-27 | 2007-10-30 | Mackay John | Bumping electronic components using transfer substrates |
US6082610A (en) * | 1997-06-23 | 2000-07-04 | Ford Motor Company | Method of forming interconnections on electronic modules |
US6053394A (en) * | 1998-01-13 | 2000-04-25 | International Business Machines Corporation | Column grid array substrate attachment with heat sink stress relief |
US20020076910A1 (en) * | 1999-12-15 | 2002-06-20 | Pace Benedict G. | High density electronic interconnection |
US6781065B1 (en) | 2000-06-08 | 2004-08-24 | The Whitaker Corporation | Solder-coated articles useful for substrate attachment |
US6429046B1 (en) * | 2000-07-13 | 2002-08-06 | Motorola, Inc. | Flip chip device and method of manufacture |
TWI313507B (en) | 2002-10-25 | 2009-08-11 | Megica Corporatio | Method for assembling chips |
US7242099B2 (en) * | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
JP2003198117A (en) * | 2001-12-28 | 2003-07-11 | Matsushita Electric Ind Co Ltd | Soldering method and junction structure body |
US7394161B2 (en) * | 2003-12-08 | 2008-07-01 | Megica Corporation | Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto |
US7173590B2 (en) * | 2004-06-02 | 2007-02-06 | Sony Corporation | Pixel circuit, active matrix apparatus and display apparatus |
JP2015060097A (en) * | 2013-09-19 | 2015-03-30 | ソニー株式会社 | Optical transmission module |
US20060186180A1 (en) * | 2005-02-24 | 2006-08-24 | Northrop Grumman Corporation | Accurate relative alignment and epoxy-free attachment of optical elements |
DE102005052563B4 (en) * | 2005-11-02 | 2016-01-14 | Infineon Technologies Ag | Semiconductor chip, semiconductor device and method of making the same |
KR100680997B1 (en) * | 2005-12-05 | 2007-02-09 | 한국전자통신연구원 | Method of flip chip bonding and its application for optical module |
US8076587B2 (en) * | 2008-09-26 | 2011-12-13 | Siemens Energy, Inc. | Printed circuit board for harsh environments |
KR101675727B1 (en) * | 2010-03-09 | 2016-11-14 | 주식회사 케이씨씨 | Metal-bonded ceramic substrate |
JP2013125768A (en) * | 2011-12-13 | 2013-06-24 | Japan Oclaro Inc | Solder bonding device and reception module |
US8802556B2 (en) * | 2012-11-14 | 2014-08-12 | Qualcomm Incorporated | Barrier layer on bump and non-wettable coating on trace |
US9609752B1 (en) | 2013-03-15 | 2017-03-28 | Lockheed Martin Corporation | Interconnect structure configured to control solder flow and method of manufacturing of same |
US10422870B2 (en) | 2015-06-15 | 2019-09-24 | Humatics Corporation | High precision time of flight measurement system for industrial automation |
US10591592B2 (en) | 2015-06-15 | 2020-03-17 | Humatics Corporation | High-precision time of flight measurement systems |
CN108701896B (en) | 2015-12-17 | 2021-03-12 | 修麦提克斯公司 | Device for realizing radio frequency positioning |
US12080415B2 (en) | 2020-10-09 | 2024-09-03 | Humatics Corporation | Radio-frequency systems and methods for co-localization of medical devices and patients |
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FR1483574A (en) * | 1965-06-24 | 1967-09-06 | ||
JPS4838096A (en) * | 1971-09-14 | 1973-06-05 | ||
JPS5950106B2 (en) * | 1976-10-15 | 1984-12-06 | 株式会社東芝 | Electrode structure of semiconductor devices |
JPS5568654A (en) * | 1978-11-20 | 1980-05-23 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPS5571023A (en) * | 1978-11-24 | 1980-05-28 | Toshiba Corp | Method of forming electrode on compound semiconductor |
US4273859A (en) * | 1979-12-31 | 1981-06-16 | Honeywell Information Systems Inc. | Method of forming solder bump terminals on semiconductor elements |
US4510514A (en) * | 1983-08-08 | 1985-04-09 | At&T Bell Laboratories | Ohmic contacts for semiconductor devices |
US4772935A (en) * | 1984-12-19 | 1988-09-20 | Fairchild Semiconductor Corporation | Die bonding process |
GB8522429D0 (en) * | 1985-09-10 | 1985-10-16 | Plessey Co Plc | Alignment for hybrid device |
GB2194387A (en) * | 1986-08-20 | 1988-03-02 | Plessey Co Plc | Bonding integrated circuit devices |
US4840302A (en) * | 1988-04-15 | 1989-06-20 | International Business Machines Corporation | Chromium-titanium alloy |
BE1001855A3 (en) * | 1988-06-29 | 1990-03-20 | Picanol Nv | Pneumatic wire clip for inner edge device for looms. |
US4907734A (en) * | 1988-10-28 | 1990-03-13 | International Business Machines Corporation | Method of bonding gold or gold alloy wire to lead tin solder |
-
1990
- 1990-04-04 EP EP90303603A patent/EP0398485B1/en not_active Expired - Lifetime
- 1990-04-04 DE DE69021438T patent/DE69021438T2/en not_active Expired - Fee Related
- 1990-05-15 JP JP2125287A patent/JPH03101242A/en active Pending
-
1991
- 1991-04-12 US US07/684,483 patent/US5108027A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH03101242A (en) | 1991-04-26 |
DE69021438D1 (en) | 1995-09-14 |
EP0398485A1 (en) | 1990-11-22 |
EP0398485B1 (en) | 1995-08-09 |
US5108027A (en) | 1992-04-28 |
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