GB2194387A - Bonding integrated circuit devices - Google Patents

Bonding integrated circuit devices Download PDF

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Publication number
GB2194387A
GB2194387A GB08620288A GB8620288A GB2194387A GB 2194387 A GB2194387 A GB 2194387A GB 08620288 A GB08620288 A GB 08620288A GB 8620288 A GB8620288 A GB 8620288A GB 2194387 A GB2194387 A GB 2194387A
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GB
United Kingdom
Prior art keywords
bond
minor
solder
joint
bonds
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB08620288A
Other versions
GB8620288D0 (en
Inventor
David John Pedder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB08620288A priority Critical patent/GB2194387A/en
Publication of GB8620288D0 publication Critical patent/GB8620288D0/en
Publication of GB2194387A publication Critical patent/GB2194387A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

In the manufacture of a flip chip bonded hybrid integrated circuit device having a substrate 1 and a flip chip 3 joined by solder bonds 7, 8, the bonds occupying portions of the substrate surface which have dissimilar bond areas, the bonds 8 which occupy the smaller ones of the bond areas on the substrate have a solder volume arranged such that the resulting minor bonds after their formation adopt a joint shape with generally concave side walls. The provision of the concave side walls acts to increase the fatigue life of the joint so that device reliability is improved. <IMAGE>

Description

SPECIFICATION Integrated circuit devices This invention relates to integrated circuit devices. It relates partiularly to devices of the flip chip solder bonded kind and discloses a method by which the reliability of the device in service may be improved.
One cause of failure in service of a flip chip solder bonded hybrid device can be due to a solder joint deformation effect where conditions of ambient temperature or power cycling have been experienced. A change of temperature can give rise to joint deformation as a result of a mismatch in the thermal expansion coefficients of the hybrid components. Equally a temperature gradient that may occur between expansion matched components in a flip chip bonded hybrid device can also result in a solder joint deformation. This joint deformation, under service conditions can actually determine and control the hybrid device life by reason of the potential fatigue failure of the solder joint.
It should be noted that the solder compositions commonly employed in flip chip bonded devices (for example, 95 weight percent of lead, five percent tin; melting range 310-314 C, are, at room temperature, operating at about one twentieth of the melting temperature on the Absolute Scale. At such temperatures, metal alloy yield strengths are low and any mechanical displacement between the separate components of a flip chip bonded hybrid device can be accommodated by an essentially plastic deformation of the solder joint material. The fatigue life of a solder joint under these conditions is determined by a mechanism termed its low cycle (thermal) fatigue.The actual fatigue life of a given solder joint is a relatively complex function of the level of joint deformation (which in turn is a function of expansion coefficients, temperature gradients and joint position relative to a neutral axis of the hybrid, device), joint shape, solder joint ductility and cycle frequency and profile details. Thus, for example, the solder joint fatigue life has been described by a mathematical equation which takes into account the effects of creep and related timetemperature dependent properties of the solder material. The maximum strain in the joint, which determines the fatigue life, is a function of joint geometry and shape.
The present inventipn was devised to provide an improved construction of integrated circuit device which could allow an extension in the potential life in service expectancy of the device.
According to the invention, there is provided a flip chip bonded hybrid integrated circuit device having a substrate and a flip chip joined by solder bonds, the bond occupying portions of the substrate surface which have dissimilar bond areas, in which the bonds occupying the smaller ones of the band areas on the substrate have a solder volume arranged such that the resulting minor bonds after their formation adopt a joint shape with generally concave side walls.
Preferably, the said volume of the minor solder bonds is less than that of a right cylinder of radius equal to that of the smaller bond area with a height equal to that required for the intended spacing between said substrate and the flip chip.
The invention also comprises a method of making a flip chip bonded hybrid integrated circuit device comprising the steps of preparing a substrate body having major and minor bond areas to which a flip chip is to be joined, placing solder deposits about the said areas for eventually forming solder joints with the said chip, the quantities of solder for deposit on the said minor bond areas being proportioned to ensure that the eventual bonds formed about these minor areas will have generally concave side walls.
By way of example, some particular embodiments of the invention will now be described with reference to the accompanying drawings, in which: Figure 1 shows schematically on a greatly enlarged scale the effects of solder joint displacement on thermal cycling in a flip chip solder bonded hybrid integrated circuit device; Figures 2 and 3 show some of the dimensions that are significant in calculating the stresses involved; Figures 4 to 6 show different possible bond geometries for flip chip bonded hybrid devices, and, Figures 7 to 9 show the conditions required for depositing predetermined solder volumes for device joints.
As depicted in Figure 1, a flip chip hybrid device has a substrate 1 with several solder bonds 2 providing electrical connections and a physical support means for a flip chip device 3. The flip chip device 3 is required to be supported in a parallel arrangement with the substrate 1 so the solder masses 2 are located roughly equally on either side of a neutral axis 4 to ensure that the chip device 3 will not tend to tilt out of parallel during the operation of fusing the material of the solder masses 2.
After manufacture of the hybrid device, it can be expected to be put into service in an environment where it will be exposed to time and temperature changes on the material of the solder masses 2 and the effects of creep will also occur. Figure 2 shows some of these effects on a single solder mass 2 which is spaced by a distance d from the neutral axis 4. In this Figure, the upper surface of the solder material forming the mass 2 has been moved a short distance in the direction of the axis 4 and the volume of the solder mass has therefore taken up the shape indicated by the dotted line 6.
Figure 3 shows the general geometry of the solder joint with an indication of the dimensions that might be needed for calculating the stresses involved.
Figure 4 shows the different bond geometries that occur when a flip chip bonded hybrid includes two, or more, different bond sizes.
The bonds having the largest and the smallest areas are termed the major and minor bonds respectively. The present considerations apply particularly to the case where the total perimeter of all the major bonds significantly exceeds that of all the minor bonds and thus the overall equilibrium bond height, which is determined by the balance of surface tension forces between the total number of bonds, is dominated by the design of the major bonds.
A number of different minor bond geometries may then be considered for a given, and to a first approximation, fixed major bond geometry.
The situation shown in Figure 4 has the major solder joint 7 volume and the minor solder joint 8 volume arranged so that both joints are the equilibrium joint shape for the required common joint height, H. The equilibrium shapes correspond to that of a simple truncated sphere.
The minor joint 8 under these circumstances will show a shorter thermal cycle fatigue life than will the major joint 7 for two reasons.
Firstly, the fatigue life is controlled by the value of the maximum strain on a joint, and the maximum strain location occurs at a strain concentration region where the solder joint meets one of the hybrid surfaces, the maximum strain increasing as the angle A becomes more acute. The corresponding value for where the major solder joint 7 meets the hybrid surface is the angle B. Since A is less than B the minor bond experiences a higher strain than the major bond, with the result that fatigue crack nucleation will occur first at the minor bond.
Secondly, the fatigue life also depends upon the diameter of the relevant solder joint since this dimension is the distance over which a fatigue crack must propagate to cause a joint failure. The combination of higher local strain and the rislc of a smaller crack site causing failure leads to the minor bond condition controlling fatigue life. Thus a reduction of the minor bond joint curvature, as depicted in Figure 5, can- be used to reduce strain concentration and increase hybrid device reliability. The optimum joint geometry is illustrated in Figure 6, in which the minor joint is rendered concave rather than convex In shape. The point of maximum strain in the minor bond is now at the bond centre point and it is very considerably smaller than for the convex bond case.A limit on the concavity of the minor bond does exist, as shown in Figure 4, since the minor solder bump height after initial bump formation must clearly be greater than the equilibrium bond height determined by the major bonds. Again the volume of the minor solder bond must be less than that of the right cylinder of radius equal to that of the minor bond with height equal to that of the major bond heights, in order for the minor bond to adopt a concave joint shape.
The conditions for depositing the required predetermined volumes of solder are depicted in Figures 7 to 9. Figure 7 shows the solder masses 2 as deposited on top of electrically conductive film areas 9 supported on the substrate 1. Subsequent fusion of the solder material causes this to form a globule which is centred on each conductive film area 9 on the substrate. The globule will be pulled into a shape having a minimum surface area by surface tension forces and clearly the height of the globule upon any particular conductive area will depend upon the volume of solder deposited on that area. As already mentioned, the globule height should be no less than the required joint height.
Figure 9 shows the profiles of the solder masses when the flip chip has been located in place on the substrate. The minor solder joint 8 has formed a concave shape which is somewhat smaller in volume than that of a cylinder based on the relevant electrically conductive film area 9. The profile of such a cylinder is indicated by the dotted line 11. The globule volume which forms a precursor for this bond should therefore be smaller than the volume of this cylinder in order to obtain the required concave side walls.
The foregoing description of an embodiment of the invention has been given by way of example only and a number of modifications may be made without departing from the scope of the invention as defined in the appended claims. For instance, it is not essential that the provision of bonds with generally concave side walls should be restricted only to the minor bond areas. In a different embodiment, the provision of bonds with concave side walls could be used for all of the bond areas on the substrate provided that some alternative means was adopted for maintaining the correct spacing between the two surfaces which is one of the normal functions of the major bond areas. 1. A flip chip bonded hybrid integrated circuit device having a substrate and a flip chip joined by solder bonds, the bonds occupying portions of the substrate surface which have dissimilar bond areas, in which the bonds occupying the smaller ones of the bond areas on the substrate have a solder volume arranged such that the resulting minor bonds after their formation adopt a joint shape with generally concave side walls.
2. A device as claimed in Claim 1, in which the said volume of the minor solder bonds is
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (4)

  1. **WARNING** start of CLMS field may overlap end of DESC **.
    therefore taken up the shape indicated by the dotted line 6.
    Figure 3 shows the general geometry of the solder joint with an indication of the dimensions that might be needed for calculating the stresses involved.
    Figure 4 shows the different bond geometries that occur when a flip chip bonded hybrid includes two, or more, different bond sizes.
    The bonds having the largest and the smallest areas are termed the major and minor bonds respectively. The present considerations apply particularly to the case where the total perimeter of all the major bonds significantly exceeds that of all the minor bonds and thus the overall equilibrium bond height, which is determined by the balance of surface tension forces between the total number of bonds, is dominated by the design of the major bonds.
    A number of different minor bond geometries may then be considered for a given, and to a first approximation, fixed major bond geometry.
    The situation shown in Figure 4 has the major solder joint 7 volume and the minor solder joint 8 volume arranged so that both joints are the equilibrium joint shape for the required common joint height, H. The equilibrium shapes correspond to that of a simple truncated sphere.
    The minor joint 8 under these circumstances will show a shorter thermal cycle fatigue life than will the major joint 7 for two reasons.
    Firstly, the fatigue life is controlled by the value of the maximum strain on a joint, and the maximum strain location occurs at a strain concentration region where the solder joint meets one of the hybrid surfaces, the maximum strain increasing as the angle A becomes more acute. The corresponding value for where the major solder joint 7 meets the hybrid surface is the angle B. Since A is less than B the minor bond experiences a higher strain than the major bond, with the result that fatigue crack nucleation will occur first at the minor bond.
    Secondly, the fatigue life also depends upon the diameter of the relevant solder joint since this dimension is the distance over which a fatigue crack must propagate to cause a joint failure. The combination of higher local strain and the rislc of a smaller crack site causing failure leads to the minor bond condition controlling fatigue life. Thus a reduction of the minor bond joint curvature, as depicted in Figure 5, can- be used to reduce strain concentration and increase hybrid device reliability. The optimum joint geometry is illustrated in Figure 6, in which the minor joint is rendered concave rather than convex In shape. The point of maximum strain in the minor bond is now at the bond centre point and it is very considerably smaller than for the convex bond case.A limit on the concavity of the minor bond does exist, as shown in Figure 4, since the minor solder bump height after initial bump formation must clearly be greater than the equilibrium bond height determined by the major bonds. Again the volume of the minor solder bond must be less than that of the right cylinder of radius equal to that of the minor bond with height equal to that of the major bond heights, in order for the minor bond to adopt a concave joint shape.
    The conditions for depositing the required predetermined volumes of solder are depicted in Figures 7 to 9. Figure 7 shows the solder masses 2 as deposited on top of electrically conductive film areas 9 supported on the substrate 1. Subsequent fusion of the solder material causes this to form a globule which is centred on each conductive film area 9 on the substrate. The globule will be pulled into a shape having a minimum surface area by surface tension forces and clearly the height of the globule upon any particular conductive area will depend upon the volume of solder deposited on that area. As already mentioned, the globule height should be no less than the required joint height.
    Figure 9 shows the profiles of the solder masses when the flip chip has been located in place on the substrate. The minor solder joint 8 has formed a concave shape which is somewhat smaller in volume than that of a cylinder based on the relevant electrically conductive film area 9. The profile of such a cylinder is indicated by the dotted line 11. The globule volume which forms a precursor for this bond should therefore be smaller than the volume of this cylinder in order to obtain the required concave side walls.
    The foregoing description of an embodiment of the invention has been given by way of example only and a number of modifications may be made without departing from the scope of the invention as defined in the appended claims. For instance, it is not essential that the provision of bonds with generally concave side walls should be restricted only to the minor bond areas. In a different embodiment, the provision of bonds with concave side walls could be used for all of the bond areas on the substrate provided that some alternative means was adopted for maintaining the correct spacing between the two surfaces which is one of the normal functions of the major bond areas. 1.A flip chip bonded hybrid integrated circuit device having a substrate and a flip chip joined by solder bonds, the bonds occupying portions of the substrate surface which have dissimilar bond areas, in which the bonds occupying the smaller ones of the bond areas on the substrate have a solder volume arranged such that the resulting minor bonds after their formation adopt a joint shape with generally concave side walls.
  2. 2. A device as claimed in Claim 1, in which the said volume of the minor solder bonds is less than that of a right cylinder of radius equal to that of the smaller bond area with a height equal to that required for the intended spacing between said substrate and flip chip.
  3. 3. A flip chip bonded hybrid integrated circuit device substantially as hereinbefore described with reference to the accompanying drawings.
  4. 4. A method of making a flip chip bonded hybrid integrated circuit device comprising the steps of preparing a substrate body having major and minor bond areas to which a flip chip is to be joined, placing solder deposits about the said areas for eventually forming solder joints with the said chip, the quantities of solder for deposit on the said minor bond areas being proportioned to ensure that the eventual bond formed about these minor areas will have generally concave side walls.
    5; A method of making a flip chip bonded hybrid integrated circuit device substantially as hereinbefore described with reference to the accompaying drawings.
GB08620288A 1986-08-20 1986-08-20 Bonding integrated circuit devices Withdrawn GB2194387A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB08620288A GB2194387A (en) 1986-08-20 1986-08-20 Bonding integrated circuit devices

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Application Number Priority Date Filing Date Title
GB08620288A GB2194387A (en) 1986-08-20 1986-08-20 Bonding integrated circuit devices

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Publication Number Publication Date
GB8620288D0 GB8620288D0 (en) 1986-10-01
GB2194387A true GB2194387A (en) 1988-03-02

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0398485A1 (en) * 1989-05-16 1990-11-22 Gec-Marconi Limited A method of making a Flip Chip Solder bond structure for devices with gold based metallisation
EP0725434A2 (en) * 1995-02-03 1996-08-07 Plessey Semiconductors Limited Microchip module assemblies
EP0899787A2 (en) * 1997-07-25 1999-03-03 Mcnc Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structurs formed thereby
US6329608B1 (en) 1995-04-05 2001-12-11 Unitive International Limited Key-shaped solder bumps and under bump metallurgy
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
DE102005015109A1 (en) * 2005-04-01 2006-10-05 Robert Bosch Gmbh Semiconductor chip assembling method, involves lifting component region of chip from substrate such that region indirectly contacts substrate via soldering material and chip is assembled on substrate by flip-chip technique
US7659621B2 (en) 2003-10-14 2010-02-09 Unitive International Limited Solder structures for out of plane connections
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US7839000B2 (en) 2002-06-25 2010-11-23 Unitive International Limited Solder structures including barrier layers with nickel and/or copper
US7879715B2 (en) 2002-06-25 2011-02-01 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
US7932615B2 (en) 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508118A (en) * 1965-12-13 1970-04-21 Ibm Circuit structure
GB1298115A (en) * 1969-08-14 1972-11-29 Ibm Electric circuit module
GB1412363A (en) * 1972-12-11 1975-11-05 Ibm Attachment of circuit devices to a substrate
GB2062963A (en) * 1979-11-12 1981-05-28 Hitachi Ltd Semiconductor chip mountings
EP0147576A1 (en) * 1983-11-25 1985-07-10 International Business Machines Corporation Process for forming elongated solder connections between a semiconductor device and a supporting substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508118A (en) * 1965-12-13 1970-04-21 Ibm Circuit structure
GB1298115A (en) * 1969-08-14 1972-11-29 Ibm Electric circuit module
GB1412363A (en) * 1972-12-11 1975-11-05 Ibm Attachment of circuit devices to a substrate
GB2062963A (en) * 1979-11-12 1981-05-28 Hitachi Ltd Semiconductor chip mountings
EP0147576A1 (en) * 1983-11-25 1985-07-10 International Business Machines Corporation Process for forming elongated solder connections between a semiconductor device and a supporting substrate

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0398485A1 (en) * 1989-05-16 1990-11-22 Gec-Marconi Limited A method of making a Flip Chip Solder bond structure for devices with gold based metallisation
EP0725434A2 (en) * 1995-02-03 1996-08-07 Plessey Semiconductors Limited Microchip module assemblies
EP0725434A3 (en) * 1995-02-03 1998-10-14 Mitel Semiconductor Limited Microchip module assemblies
US6392163B1 (en) 1995-04-04 2002-05-21 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
US6389691B1 (en) 1995-04-05 2002-05-21 Unitive International Limited Methods for forming integrated redistribution routing conductors and solder bumps
US6329608B1 (en) 1995-04-05 2001-12-11 Unitive International Limited Key-shaped solder bumps and under bump metallurgy
EP0899787A3 (en) * 1997-07-25 2001-05-16 Mcnc Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structurs formed thereby
EP0899787A2 (en) * 1997-07-25 1999-03-03 Mcnc Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structurs formed thereby
SG99384A1 (en) * 1997-07-25 2003-10-27 Unitive Int Ltd Controlled-shaped solder reservoirs for increasing the volume of solders bumps, and structures formed thereby
US7839000B2 (en) 2002-06-25 2010-11-23 Unitive International Limited Solder structures including barrier layers with nickel and/or copper
US7879715B2 (en) 2002-06-25 2011-02-01 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
US8294269B2 (en) 2002-06-25 2012-10-23 Unitive International Electronic structures including conductive layers comprising copper and having a thickness of at least 0.5 micrometers
US7659621B2 (en) 2003-10-14 2010-02-09 Unitive International Limited Solder structures for out of plane connections
DE102005015109A1 (en) * 2005-04-01 2006-10-05 Robert Bosch Gmbh Semiconductor chip assembling method, involves lifting component region of chip from substrate such that region indirectly contacts substrate via soldering material and chip is assembled on substrate by flip-chip technique
DE102005015109B4 (en) * 2005-04-01 2007-06-21 Robert Bosch Gmbh Method for mounting semiconductor chips on a substrate and corresponding arrangement
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US7932615B2 (en) 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers

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Publication number Publication date
GB8620288D0 (en) 1986-10-01

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