CN1473359A - 用于制造互连结构的方法和装置 - Google Patents

用于制造互连结构的方法和装置 Download PDF

Info

Publication number
CN1473359A
CN1473359A CNA018083455A CN01808345A CN1473359A CN 1473359 A CN1473359 A CN 1473359A CN A018083455 A CNA018083455 A CN A018083455A CN 01808345 A CN01808345 A CN 01808345A CN 1473359 A CN1473359 A CN 1473359A
Authority
CN
China
Prior art keywords
bottom land
column
passivation layer
layer
perforate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA018083455A
Other languages
English (en)
Other versions
CN1291468C (zh
Inventor
���ϡ�B����˹����
阿迪·B·密斯特里
�ǵ¹���
林纳·乔德哈利
K
斯科特·K·波兹德
A
戴伯拉·A·哈根
������G�����ƶ�
瑞贝卡·G·科尔
凯蒂克·安南塔纳亚南
F
乔治·F·卡尼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of CN1473359A publication Critical patent/CN1473359A/zh
Application granted granted Critical
Publication of CN1291468C publication Critical patent/CN1291468C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11912—Methods of manufacturing bump connectors involving a specific sequence of method steps the bump being used as a mask for patterning other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01009—Fluorine [F]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

在此公开一种互连结构(10)，例如倒装片结构，其中包括一个底部焊盘(14)和形成在该底部焊盘(14)并且从该底部焊盘(14)延伸的立柱(17)。该立柱(17)和底部焊盘(14)是连续的，并且为基本上相同的导电基底材料。通常，一个焊接结构(26)形成在该立柱(17)上，其中该焊接结构(26)被暴露，用于随后回流附着到另一个结构上。本发明涉及封装集成电路，特别涉及没有采用标准的凸块下的冶金方法的立柱(17)和凸块的结构和处理方法。

Description

用于制造互连结构的方法和装置
技术领域
本发明涉及封装集成电路，特别涉及不采用标准的凸块下的冶金方法(under bump metallurgy)的立柱和凸块的结构和处理方法。
背景技术
本发明涉及在集成电路芯片上形成包含立柱和凸块的互连结构的处理方法和结构。当前，在半导体工业中，对底部焊盘的顶部进行凸块下的冶金方法(UBM)处理，其中该底部焊盘一般为铝或铜或者它们的合金。该UBM通常包括在蒸发的凸块立柱下方的一层铬、一层铬铜合金(CrCu)、一层铜(Cu)以及一层金(Au)。对于电镀凸块，该UBM通常包括在该立柱下方的一层钛钨氮化物(TiWNx)、一层钛钨合金(TiW)和一层铜。该下方凸块金属被用于获得良好的附着性以及用于减小底部焊盘与该立柱之间的应力的焊锡扩散阻挡层。
本发明提供一种不需要UBM的互连结构，从而减少处理步骤、制造成本并且增加可靠性。在本发明中，使用基本上相同的基底材料，立柱被直接应用于底部焊盘。本发明的优点包括使用基本上相同的底部材料作为立柱和作为结合焊盘，其减小应力、减少处理步骤和成本，而不产生立柱和底部焊盘之间的粘合性问题。
附图说明
本发明通过举例说明并且不限于附图中所示，基本相同的参考标号表示相同的部件，其中：
图1-3示出用于形成互连结构的相继处理步骤的截面示图；
图4A-5示出根据本发明包括蚀刻该互连结构的相继处理步骤的截面示图；
图6-8示出根据本发明用于形成该立柱的相继处理步骤的截面示图；
图9-11示出根据本发明用于形成焊接结构的相继处理步骤的截面示图；
图12-13示出根据本发明用于进一步形成没有焊接结构的立柱的相继处理步骤的截面示图；
图14-16示出根据本发明的另一个实施例用于形成立柱和焊接结构的相继处理步骤的截面示图；以及
图17A和17B示出根据本发明的一个应用的截面示图。
本领域的技术人员应当知道图中的部件用于简单和清楚地示出，并且不一定按照比例描绘。例如，在图中的一些部件的尺寸可能相对于其它部件被夸大，以有助于对本发明的实施例的理解。
具体实施方式
图1示出一种互连结构10，其中包括在底部焊盘14下方的阻挡层12，例如钽。例如氮化钛、钨、氮化钨、钛硅氮化物、钽硅氮化物、镍等等可以用作为阻挡材料。阻挡层12被用于防止底部焊盘14的材料扩散到基片(未示出)中。最好，底部焊盘14的导电基底材料为铜。但是底部焊盘14的基底材料例如还可以是铜合金、镍钒合金或者任何材料，其中该基底材料为导电金属并且不于焊接材料发生强烈的反应以产生不利的影响。例如，来自焊锡中的锡可以与例如铜这样的底部焊盘的基底材料发生反应，以形成金属性并且易碎的锡/铜组合物。只要有足够的铜，可以使用该材料。基底材料被定义为形成底部焊盘14的主要材料。例如，铜合金以铜作为主要的基底材料，包括一些额外的添加元素。
在底部焊盘14上方为绝缘阻挡种子层或者阻蚀层16，其例如是大约50纳米厚的等离子体增强的氮化物(PEN)层。在阻蚀层16上方为钝化层18，例如具有大约450纳米厚的一层氮氧化硅。互连结构一般包括被例如四乙基原硅酸盐(TEOS或Si(OC2H5)4)这样的绝缘材料(未示出)所分离的在芯片上的多个接合焊盘14或者底部焊盘。该绝缘材料还可以是掺杂粉糠剂(flourine-doped)的TEOS(FTEOS)或者任何第一介电常数的材料(即多孔氧化物)。该结构10被用光刻胶19所构图，并且在底部焊盘14上方的钝化层18被蚀刻，使得在底部焊盘14的区域上方的钝化层18的剩余厚度例如为大约50纳米。所用的蚀刻化学物质可能导致钝化层的垂直边缘，或者导致钝化层18的倾斜边缘，如图2中所示。
例如聚酰亚胺这样的弹性材料20被淀积在钝化层的上方，如图3中所示，并且第二光刻胶层23被淀积和构图。作为光刻构图处理的一部分，聚酰亚胺也被构图。一种光刻胶剥离测试如下，使用聚酰亚胺作为用于任何进一步的钝化蚀刻的蚀刻掩膜。弹性层20和钝化层18被同时使用标准蚀刻处理方法进行蚀刻。蚀刻可能导致在图4A和4B中所示的两个实施例之一。如果使用由光刻胶层23所示的光刻胶图案，则弹性层20和钝化层18的边缘将基本上在相同的点结束，称为边到边覆盖，如图4A中所示。通过使用由具有较窄开孔的光刻胶层21所示的光刻胶图案，钝化层18的边缘被弹性层20所覆盖，如图4B中所示。在图4A和图4B中，弹性层20和钝化层18的边缘剖面被示出为倾斜的。弹性层20和钝化层18的弯曲边缘剖面间接取决于在图2中所示的蚀刻处理步骤过程中使用的蚀刻化学物质，并且直接取决于在图4A和4B中所示的蚀刻处理步骤过程中使用的化学物质。在图3中所示淀积弹性层20过程中，在图2中蚀刻钝化层18中所用的蚀刻化学物质决定弹性层20的剖面。该边缘剖面的优点在于倾斜侧壁减少可能在边缘处堆积的污染物的量。另外，弹性层20和钝化层18的边缘剖面可以大约为垂直。但是，在边缘处堆积的污染物的量增加。
在蚀刻弹性层20和钝化层18之后，阻蚀层18被蚀刻，如图5中所示，确定在底部焊盘14上的一个开孔。在图5中所示的实施例中，弹性层20和钝化层18被用作为掩膜。之后，执行RF预清理，以除去已经在图4A-4B中所示的处理步骤过程中和之后在接合焊盘14上生长的天然金属氧化物层。该氧化物层的厚度例如为大约10纳米。
不破坏真空状态，把一个种子层15溅射到晶片10上，如图6中所示。该种子层15为基本上与底部焊盘14的导电基底材料相同的材料。例如，由于底部焊盘14被示出为由铜基底材料所形成，因此种子层15也是铜基底材料。如底部焊盘14所示，例如铜合金、镍钒合金或者基底材料为导电金属并且不与焊盘材料发生反应而产生不良影响的任何材料可以用作为种子层15，只要该材料基本上与底部焊盘14的基底材料相同即可。该溅射种子层15的厚度例如小于100纳米。较薄的溅射种子层15具有使得在后期的处理步骤中更加有效地蚀刻该较薄种子层15的优点。在本发明的实施例中，溅射种子层15作为用于晶片基底的一种电连接和附着层。
在图7中，形成光刻胶层24。图8示出形成立柱17为与底部焊盘14相连续，并且基本上为与底部焊盘14相同的导电基底材料。例如通过电镀、蒸发或溅射，使立柱17通过开孔形成在底部焊盘14上。最好，由于该底部焊盘14被示出由铜基底材料所形成，立柱17的导电基底材料是铜。但是，立柱17的基底材料例如还可以是铜合金、镍钒合金或者基底材料为导电金属并且不与焊盘材料发生反应而产生不良影响的任何材料，只要该材料基本上与底部焊盘14的基底材料相同即可。立柱17的上表面被示出为处于比光刻胶层24的上表面的高度更低的高度。立柱17的厚度最好足够大，从而在该器件的使用寿命过程中不会完全被焊锡材料所消耗。例如，对于个人通信产品，该立柱17约大于5微米。
在图9中，焊锡层26被电镀或蒸发在立柱17上。一般来说，所用的材料为高铅/锡，这是大于90重量百分比的铅与10重量百分比的锡；共熔铅/锡，这是63重量百分比的铅与37重量百分比的锡。其它可能的焊锡是不含铜或者环保的焊锡，例如锡银合金、锡银铜合金、锡银铋合金等等。在图10中，使用标准蚀刻处理除去光刻胶层24以及除去种子层15。使用适合于所用的焊锡材料的温度在图11中使焊锡层26回流，并且暴露焊接结构，用于后续的回流附着。立柱17周围的凸块或球体一般通过回流处理所形成。使用图11中所示的结构，在一个实施例中，作为在构成半导体基片内的电子器件的倒装片结构上的一个所控制的伸缩式芯片连接，即，电路片与基片之间的电连接。
在本发明的另一个实施例中，不形成焊锡层26，并且立柱17被暴露，用于后续附着到另一个结构上。因此，在图8的处理步骤之后，使用标准蚀刻处理除去光刻胶层24，如图12中所示。使用标准处理蚀刻该种子层15，以形成立柱17，如图13中所示。在种子层15的蚀刻过程中，立柱17的一部分也被蚀刻。但是，蚀刻量可忽略，或者用于形成立柱17的材料量补偿在蚀刻种子层17时被蚀刻的立柱17材料的部分。
图14-16具体示出通过蒸发形成立柱17的示意图。例如，在图5的蚀刻处理步骤之后，例如钼这样的掩膜被置于弹性层20上。图15示出通过蒸发使立柱17形成为所需的厚度，其中立柱17的基底材料基本上与底部焊盘14的基底材料相同。在形成立柱17的蒸发处理过程中，基底材料的蒸发层53也形成在掩膜51上，随后该掩膜被除去。如果需要的话，通过蒸发在立柱17上的铅/锡而形成焊锡层19，如图16中所示。掩膜51被除去，并且焊锡层19可以被回流，用于随后附着到另一个结构上。在图14-16中所示的实施例中，种子层15是不必要的，因为不需要用于该立柱和焊锡层的电总线。
图17A-17B示出一种应用，其中立柱17(没有焊锡层或焊接结构)被后续附着到另一个结构上。包括例如形成在倒装芯片上的电子器件的半导体基片30包括根据本发明的多个互连结构32，其电连接到该半导体基片30。该多个互连结构32使用由具有绝缘填充物34的绝缘基质36所构成的材料连接到在测试板40上的多个导电焊盘38。当施加热量和压力时，通过使如图17B中所示的多个互连结构32和导电焊盘38之间对齐，该导电填充物34把多个互连结构32电连接到在测试板40上的多个导电焊盘38。
在制作和封装倒装片结构的互连结构中的其它处理步骤一般包括施加热量，用于焊锡结构或凸块的回流附着，形成半导体结构的底部焊盘和电子器件之间的适当互连，以及把立柱接合或附着到一块板或半导体结构上。这些进一步的处理步骤是常规的，并且不需要在此重复描述。类似地，在此所述的主要处理步骤可以与本领域的技术人员所熟知的其它步骤相结合。尽管单个立柱和凸块被示出，用于说明的目的，但是应当知道在实践中，多个立柱和凸块被制作在单个互连结构上，这是本技术领域广泛采用的方法。
在上文的说明书中，已经参照具体实施例描述本发明。但是，本领域的普通技术人员应当知道可以作出各种改变和变型而不脱离本发明的权利要求中给出的范围。相应地，说明书和附图被认为是说明性而非限制性的，并且所有这种改变被包含在本发明的范围内。
上文所述的优点和解决方案是关于具体实施例的。但是，优点、对问题的解决方案以及可以设想到或者更加显然的可能造成任何优点或解决方案的任何要素不被认为是任何或所有权利要求的关键、必需或本质的特征或要素。如在此所用，术语“包括”、“包含”或者任何其它变型是非排它性的包含，例如包含一系列要素的一种处理、方法、产品或装置不仅仅包含这些要素，而且还可以包含没有在此列出的其它要素或者这些处理、方法、产品或装置所固有的要素。

Claims (34)

1.一种互连结构，其中包括：
底部焊盘；以及
立柱，其形成在底部焊盘上，并且从底部焊盘延伸，其中该立柱和底部焊盘是连续的，并且基本上为相同的导电基底材料。
2.根据权利要求1所述的互连结构，其中该立柱被暴露，用于随后附着到另一个结构上。
3.根据权利要求1所述的互连结构，其中进一步包括：
形成在该立柱上的焊接结构，其中所述焊接结构被暴露用于随后回流附着到另一个结构上。
4.根据权利要求3所述的互连结构，其中该焊锡结构由选自铅、锡、锡和铅、铅和银以及锡银铜合金的导电材料所形成。
5.根据权利要求1所述的互连结构，其中该导电基底材料为金属。
6.根据权利要求4所述的互连结构，其中该金属选自铜、镍和镍钒合金。
7.一种倒装片结构，其中包括：
包括形成在其上面的电子器件的半导体基片；
在该半导体基片上并且电连接到该电子器件的底部焊盘；
在底部焊盘与半导体基片之间的阻挡层；以及
形成在底部焊盘上并且从该底部焊盘延伸的立柱，其中该立柱和底部焊盘是连续的，并且基本上为相同的导电基底材料。
8.根据权利要求7所述的倒装片结构，其中进一步包括：
在半导体基片上的钝化层，其中该钝化层确定在底部焊盘上的一个开孔，通过该开孔形成立柱。
9.根据权利要求8所述的倒装片结构，其中该钝化层包括确定所述开孔的边缘，并且该钝化层的边缘被一个弹性层所覆盖。
10.根据权利要求9所述的倒装片结构，其中该弹性层包括聚酰亚胺。
11.根据权利要求7所述的倒装片结构，其中该立柱被暴露，用于随后附着到其它结构上。
12.根据权利要求7所述的倒装片结构，其中进一步包括：
形成在该立柱上的焊接结构，其中所述焊接结构被暴露用于随后回流附着到另一个结构上。
13.根据权利要求12所述的倒装片结构，其中该焊锡结构由选自铅、锡、锡和铅、铅和银以及锡银铜合金的导电材料所形成。
14.根据权利要求7所述的倒装片结构，其中该导电基底材料为金属。
15.根据权利要求13所述的倒装片结构，其中该金属选自铜、镍和镍钒合金。
16.一种倒装片结构，其中包括：
包括形成在其上面的电子器件的半导体基片；
在该半导体基片上并且电连接到该电子器件的底部焊盘；
在底部焊盘与半导体基片之间的阻挡层；
在半导体基片上的钝化层，其中该钝化层包括确定在底部焊盘上的一个开孔的边缘，其中该钝化层和边缘被一个弹性层所覆盖；
形成在底部焊盘上并且从该底部焊盘延伸的立柱，其中该立柱和底部焊盘是连续的，并且基本上为相同的导电基底材料。
17.根据权利要求16所述的倒装片结构，其中进一步包括：
形成在该立柱上的焊接结构，其中该焊接结构被暴露，用于随后附着到其它结构上。
18.一种制造互连结构的方法，其中包括：
形成一个底部焊盘；
在该互连结构上形成一个钝化层，其中该钝化层包括在该底部焊盘上确定一个开孔的边缘；
直接通过该开孔在该底部焊盘上形成一个立柱，并且其基本上为与底部焊盘相同的导电基底材料。
19.根据权利要求18所述的方法，其中该立柱被暴露，用于随后附着到另一个结构上。
20.根据权利要求18所述的方法，其中进一步包括：
在该立柱上形成一个焊锡结构，其中所述焊锡结构被暴露用于随后回流附着到另一个结构上。
21.根据权利要求18所述的方法，其中进一步包括：
由一个弹性层覆盖该钝化层和该钝化层的边缘。
22.根据权利要求21所述的方法，其中该弹性层包括聚酰亚胺。
23.根据权利要求18所述的方法，其中形成立柱的步骤包括：
(a)在该互连结构上溅射基本上与底部焊盘相同导电基底材料的种子层，其中该种子层被通过开孔溅射到该底部焊盘上；
(b)通过使用与底部焊盘基本上相同的导电基底材料进行电镀，使该立柱从底部焊盘上延伸；以及
(c)除去在该立柱周围外部的互连结构上的种子层。
24.根据权利要求23所述的方法，其中在步骤(b)之前进一步包括在该互连结构上形成光刻胶部分的步骤，其中该光刻胶部分提供在该底部焊盘上的第二开孔，以及在步骤(c)之前除去该光刻胶部分。
25.根据权利要求23所述的方法，其中除去在该立柱周围外部的互连结构上的种子层的步骤进一步包括：
蚀去在该立柱周围外部的种子层。
26.根据权利要求18所述的方法，其中形成立柱的步骤进一步包括：
(a)通过使用与底部焊盘基本上相同的导电基底材料进行蒸发，使该立柱从底部焊盘上延伸。
27.根据权利要求26所述的方法，其中在步骤(a)之前进一步包括在该互连结构上形成一个金属掩膜，其中该金属掩膜提供在底部焊盘上的第二开孔，以及在步骤(a)之后除去该金属掩膜。
28.根据权利要求20所述的方法，其中形成焊接结构的步骤进一步包括：
在该立柱上电镀一种导电材料；以及
施加足以熔化该导电材料的热量，并且使得该导电材料在立柱上流动。
29.根据权利要求28所述的方法，其中该导电材料由选自铅、锡、锡和铅、铅和银以及锡银铜合金的导电材料所形成。
30.根据权利要求18所述的方法，其中该导电基底材料为金属。
31.根据权利要求30所述的方法，其中该金属选自铜、镍和镍钒合金。
32.一种制造互连结构的方法，其中包括：
形成一个底部焊盘；
在该互连结构上形成一个钝化层，其中该钝化层包括在该底部焊盘上确定一个开孔的边缘；
由一个弹性层覆盖该钝化层和该钝化层的边缘；
在该互连结构上溅射基本上与底部焊盘相同导电基底材料的种子层，其中该种子层被通过第一开孔溅射到该底部焊盘上；
在该互连结构上形成一个光刻胶部分，其中该光刻胶部分提供在底部焊盘上的第二开孔；
通过使用与底部焊盘基本上相同的导电基底材料进行蒸发，使该立柱从底部焊盘通过第一和第二开孔延伸，其中该立柱和底部焊盘是连续的；
除去该光刻胶部分；以及
除去在该立柱周围外侧的互连结构上的种子层。
33.根据权利要求32所述的方法，其中该立柱被暴露，用于随后附着到另一个结构上。
34.根据权利要求32所述的方法，其中进一步包括：
在除去光刻胶部分的步骤之前在该立柱上形成一个焊接结构；以及
施加足以熔化该导电金属的热量，并且使得该导电金属在立柱上流动；以及
其中所述焊接结构被暴露、用于随后回流附着到另一个结构上。
CNB018083455A 2000-04-18 2001-04-06 用于制造互连结构的方法和装置 Expired - Lifetime CN1291468C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/551,312 2000-04-18
US09/551,312 US6429531B1 (en) 2000-04-18 2000-04-18 Method and apparatus for manufacturing an interconnect structure

Publications (2)

Publication Number Publication Date
CN1473359A true CN1473359A (zh) 2004-02-04
CN1291468C CN1291468C (zh) 2006-12-20

Family

ID=24200750

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB018083455A Expired - Lifetime CN1291468C (zh) 2000-04-18 2001-04-06 用于制造互连结构的方法和装置

Country Status (7)

Country Link
US (1) US6429531B1 (zh)
JP (1) JP5064632B2 (zh)
KR (1) KR100818902B1 (zh)
CN (1) CN1291468C (zh)
AU (1) AU2001251415A1 (zh)
TW (1) TW490775B (zh)
WO (1) WO2001080303A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102723317A (zh) * 2011-03-28 2012-10-10 飞兆半导体公司 芯片尺寸封装内的可靠焊料块耦合

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6614117B1 (en) * 2002-06-04 2003-09-02 Skyworks Solutions, Inc. Method for metallization of a semiconductor substrate and related structure
KR100476301B1 (ko) * 2002-07-27 2005-03-15 한국과학기술원 전기도금법에 의한 반도체 소자의 플립칩 접속용 ｕｂｍ의형성방법
US6878633B2 (en) * 2002-12-23 2005-04-12 Freescale Semiconductor, Inc. Flip-chip structure and method for high quality inductors and transformers
JP2004247530A (ja) * 2003-02-14 2004-09-02 Renesas Technology Corp 半導体装置及びその製造方法
US7470997B2 (en) * 2003-07-23 2008-12-30 Megica Corporation Wirebond pad for semiconductor chip or wafer
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
JP4219951B2 (ja) * 2006-10-25 2009-02-04 新光電気工業株式会社 はんだボール搭載方法及びはんだボール搭載基板の製造方法
JP4682964B2 (ja) * 2006-10-30 2011-05-11 株式会社デンソー 半導体装置およびその製造方法
US9324667B2 (en) 2012-01-13 2016-04-26 Freescale Semiconductor, Inc. Semiconductor devices with compliant interconnects
KR102315276B1 (ko) 2014-10-06 2021-10-20 삼성전자 주식회사 집적회로 소자 및 그 제조 방법

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5071518A (en) 1989-10-24 1991-12-10 Microelectronics And Computer Technology Corporation Method of making an electrical multilayer interconnect
JP3141364B2 (ja) * 1992-05-06 2001-03-05 住友電気工業株式会社 半導体チップ
KR960011855B1 (ko) * 1992-10-08 1996-09-03 삼성전자 주식회사 반도체장치의 범프 형성방법
US5466635A (en) 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US5447264A (en) * 1994-07-01 1995-09-05 Mcnc Recessed via apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon
JPH0837190A (ja) * 1994-07-22 1996-02-06 Nec Corp 半導体装置
JP2701751B2 (ja) * 1994-08-30 1998-01-21 日本電気株式会社 半導体装置の製造方法
EP0751566A3 (en) * 1995-06-30 1997-02-26 Ibm Metal thin film barrier for electrical connections
DE19616373A1 (de) 1996-04-24 1997-08-14 Fraunhofer Ges Forschung Herstellung galvanisch abgeformter Kontakthöcker
JPH1092924A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 半導体装置及びその製造方法
JPH10209154A (ja) * 1997-01-21 1998-08-07 Oki Electric Ind Co Ltd 半導体装置
US6441487B2 (en) * 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
US6251528B1 (en) * 1998-01-09 2001-06-26 International Business Machines Corporation Method to plate C4 to copper stud
US5977632A (en) * 1998-02-02 1999-11-02 Motorola, Inc. Flip chip bump structure and method of making
US6075290A (en) 1998-02-26 2000-06-13 National Semiconductor Corporation Surface mount die: wafer level chip-scale package and process for making the same
US5943597A (en) * 1998-06-15 1999-08-24 Motorola, Inc. Bumped semiconductor device having a trench for stress relief
JP2000091369A (ja) 1998-09-11 2000-03-31 Sony Corp 半導体装置及びその製造方法
US6218732B1 (en) 1998-09-15 2001-04-17 Texas Instruments Incorporated Copper bond pad process
JP3577419B2 (ja) * 1998-12-17 2004-10-13 新光電気工業株式会社 半導体装置およびその製造方法
US6180505B1 (en) 1999-01-07 2001-01-30 International Business Machines Corporation Process for forming a copper-containing film
JP2000228006A (ja) * 1999-02-05 2000-08-15 Alps Electric Co Ltd ボンディングパットおよびバンプを用いた接合体、および磁気ヘッド装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102723317A (zh) * 2011-03-28 2012-10-10 飞兆半导体公司 芯片尺寸封装内的可靠焊料块耦合

Also Published As

Publication number Publication date
TW490775B (en) 2002-06-11
KR20020091210A (ko) 2002-12-05
JP2004501504A (ja) 2004-01-15
AU2001251415A1 (en) 2001-10-30
WO2001080303A3 (en) 2002-02-21
CN1291468C (zh) 2006-12-20
US6429531B1 (en) 2002-08-06
JP5064632B2 (ja) 2012-10-31
KR100818902B1 (ko) 2008-04-04
WO2001080303A2 (en) 2001-10-25

Similar Documents

Publication Publication Date Title
CN1291468C (zh) 用于制造互连结构的方法和装置
US6511901B1 (en) Metal redistribution layer having solderable pads and wire bondable pads
US7834454B2 (en) Electronic structures including barrier layers defining lips
US6417089B1 (en) Method of forming solder bumps with reduced undercutting of under bump metallurgy (UBM)
EP1134805B1 (en) Solder bump fabrication methods and structure including a titanium barrier layer
US6375062B1 (en) Surface bumping method and structure formed thereby
US7358174B2 (en) Methods of forming solder bumps on exposed metal pads
US6489229B1 (en) Method of forming a semiconductor device having conductive bumps without using gold
US6251501B1 (en) Surface mount circuit device and solder bumping method therefor
US9943930B2 (en) Composition of a solder, and method of manufacturing a solder connection
US20020096764A1 (en) Semiconductor device having bump electrode
US8106516B1 (en) Wafer-level chip scale package
US20100219528A1 (en) Electromigration-Resistant Flip-Chip Solder Joints
US20020086520A1 (en) Semiconductor device having bump electrode
US20080054461A1 (en) Reliable wafer-level chip-scale package solder bump structure in a packaged semiconductor device
US20100117231A1 (en) Reliable wafer-level chip-scale solder bump structure
CN1315158C (zh) 选择性电镀半导体器件的输入/输出焊盘的方法
WO2007064073A1 (en) Bump with multiple vias for semiconductor package, method of fabrication method thereof, and semiconductor package using the same
US20050026416A1 (en) Encapsulated pin structure for improved reliability of wafer
US6429046B1 (en) Flip chip device and method of manufacture
US7994043B1 (en) Lead free alloy bump structure and fabrication method
US7138327B2 (en) Method of routing an electrical connection on a semiconductor device and structure therefor

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20180918

Address after: texas

Patentee after: Fisical Semiconductor Inc.

Address before: Illinois

Patentee before: Motorola Inc.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20181016

Address after: American Texas

Patentee after: NXP America Co Ltd

Address before: texas

Patentee before: Fisical Semiconductor Inc.

TR01 Transfer of patent right
CX01 Expiry of patent term

Granted publication date: 20061220

CX01 Expiry of patent term