TW490775B - Method and apparatus for manufacturing an interconnect structure - Google Patents

Method and apparatus for manufacturing an interconnect structure Download PDF

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Publication number
TW490775B
TW490775B TW090109167A TW90109167A TW490775B TW 490775 B TW490775 B TW 490775B TW 090109167 A TW090109167 A TW 090109167A TW 90109167 A TW90109167 A TW 90109167A TW 490775 B TW490775 B TW 490775B
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Taiwan
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base plate
wire
layer
flip
patent application
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TW090109167A
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English (en)
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Addi B Mistry
Rina Chowdhury
Scott K Pozder
Deborah A Hagen
Rebecca G Cole
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Motorola Inc
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Description

490775 A7 B7 五、發明説明( 塵1先前技術之春考 經濟部中央標準局員工消費合作社印製 此况明書已於2000年4月18日在美國歸檔爲專利申請説明 書第 〇9/551,312 號。 發明領域 本發明有關積體電路之封裝,更特別的是有關一不需該 “準在凸塊冶金學下的打線和凸塊之結構和處理。 發明背景 本發明涉及在積體電路晶片上形成包括一打線和一凸塊 互連結構之方法和結構。目前,在半導體工業中,於基墊 上方施加一在凸塊之下的金屬(UBM),其中該基墊板通常 爲鋁或銅或其合金。該凸塊之下的金屬UBM通常包括一層 鉻,一層鉻銅(CrCu),一層銅(Cu),和一層金(Au)在一蒸發 的凸塊打線之下。對一電鍍凸塊而言,該凸塊之下的^屬 UBM通常包括一層鈦鎢氮化物(TiWNx),一層鈦鎢(丁丨和 一層銅在該打線之下。將此在凸塊冶金學下用做一焊鍚擴 散障礙以獲得良好的黏著性,並且用於減少在該基墊板和 該打線間的應力。 本發明提供一不需凸塊之下的金屬UBM的互連結構,因 而減少處理步驟、製造成本並增加信賴性。在本發明中, 使用實質上相同的基本材料將一打線直接施加至該基墊板 。本發明之優點包括使用實質上相同的基本材料於該打線 和該結合板以降低應力、減少處理步驟和成本,而不會在 該打線和基塾板間產生黏著問題。 附圖之簡要敘诚 -4- 本紙張尺度適用中國國家標準( CNS ) Α4規格(210 X 297公釐) -------- (請先閲讀背面之注意事項再填寫本頁) -裝-
、1T 斷 發明說明(2 ) 透過範例圖示本發明並且不限於附圖,其中相同的參考 表示類似元件,並且其中: , " 向圖1 II圖示形成該I連結構的連續方法步驟之橫斷面 ^5圖示如本發明,包括刻該互連結構的連續 之橫__圖; 圖6到8圖示如本發明形成該打線的連續方法步驟之橫 面圖; ” 圖9到:Π圖示如本發明形成一鲜錄結構的連續彳法步驟之 橫斷面圖。 、圖12到13圖示如本發明供進一步形成用於無銲鍚結構的 孩打線上的連續方法步驟之橫斷面圖; 圖14到16圖示如本發明其它具體實例,形成一打線和一 銲鍚結構的連續方法步驟之橫斷面圖;及 圖17A和17B圖示如本發明之本發明應用橫斷面圖。 熟於先前技術者將了解到在圖中的元件係依簡化和清晰 而圖示,並且不必依實際尺寸繪製。例如,在圖中某些元件 相對於其它元件的尺寸可能被放大,以協助提升對本發明 具體實例之了解。 & 附圖之詳細敘 圖1圖示一互連結構1〇,包括一障礙層12,例如妲在 基墊板14的正下方。可使用其它金屬,例如氮化妲,鎢\氮 化鎢,氮化鈦矽,氮化鈕矽,鎳等,做爲障礙材料。使用該 障礙層12以避免在基體内(未顯示)該基墊板14材料的擴散。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ------------裝— (請先閱讀背面之注意事項再填寫本頁) . 經濟部智慧財產局員工消費合作社印製 490775 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明( 最好,該基墊板14的導電基本材料爲銅。然而,該基墊板14 的基本材料也可爲,例如,銅合金,鎳釩,或任何該基本材 料馬導通金屬並且不會與焊鍚材料積極反應而產生一不想 要的效應的材料。例如,該焊鍚中的錫可與該基墊板14的 基本材料,例如銅,起反應以形成一金屬的和脆的錫/銅化 合物。只要該錫不是很需要銅並且有足夠的銅,就可使用 該材料。該基本材料被定義爲要形成該基墊板14所使用最 多的材料。例如,由於銅包括某些額外的摻質元件,銅合 金將佔該基本材料的大多數。 在忒基塾板14正上方有一電介質障礙種籽層或蝕刻停止 層1 6,爲例如爲約5 0毫米層的電漿加強氮化(pEN)層。在該 钱刻停止層16之上爲一被動層18,例如,一層氮氧化矽 (SiON),厚度約爲450毫米。該互連結構一般包括複數個連 結板14或基墊板,在一晶片上以一電介質材料(未顯示)區隔 ’例如四乙醇正娃酸鹽tetraethyi〇rth〇siiicate(丁E〇s或 Si(OC2H5)4)。該電介質材料也可爲氦摻雜質(fl〇urine· doped)TEOS(FTEOS)或任何低電介質常數的材料(亦即通氣 性氧化物porous oxide)。該結構1〇以一光阻19樣式化,並 且在该基塾板14上方的該被動層1 8被蚀刻,以致於該被動 層1 8超過在該基塾板14 一區域的剩餘厚度爲,例如,約5 〇 毫米。所使用的該蝕刻化學作用可導致該被動層的垂直邊 緣或該被動層1 8的傾斜邊緣,如圖2所示。 、 如圖3所示,將一彈性層20,例如一聚亞胺薄膜,沉積於 該被動層的上方,並且沉積和樣式第二光阻層23。做爲該 -6- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) (請先閲讀背面之注意事項再填寫本頁) •裝· 訂 490775 A7 " "-------------- —_____ 五、發明說明(4 ) 光阻樣式處理的一部份,該聚亞胺薄膜也被樣式化。接著 一光阻剥除測試,留下該聚亞胺薄膜做爲任何進—步被動 触刻的姓刻遮罩。使用一標準姓刻方法同時姓刻該彈性層 2〇和被動層18。蝕刻可導致圖示於圖4八和忉的二具體實二 中。若使用由光阻層23所例示的光阻樣式,該彈性層 2〇和該被動層18的邊緣會終止於大約相同的點,稱爲從邊 緣覆蓋到邊緣的範圍,如圖4A所示。透過使用由光阻層Η 所例示的具有較窄開口的光阻樣式,該被動層18的邊^爲 忒彈性層20所覆盍,如圖4Β所示。在圖4Α和圖4Β兩者中, 該彈性層20和被動層18的邊緣輪廓被圖示爲傾斜的。該彈 性層20和被動層18彎曲的邊緣輪廓間接視圖示於圖2該蝕刻 處理步驟中所使用的該蝕刻化學作用而定,並且直接視圖 示糸圖4Α和4Β中泫银刻處理步驟所使用的該化學作用而定 。在圖3所示的該彈性層20沉積期間,圖2蝕刻該被動層18 中所使用的該蝕刻化學作用決定該彈性層2〇的輪廓。此邊 緣輪廓的優點爲該傾斜牆減少了會陷在該邊緣的污染物的 里。該彈性層20和該被動層1 8的邊緣輪廓可,或者,大約 是垂直面。然而,陷在該邊緣的污染物的量會增加。 在姓刻該彈性層20和該被動層1 8之後,如圖5所示蝕刻該 蚀刻停止層1 6以在該基墊板14上定義一開口。在圖示於圖 5内的該具體實例中,使用該彈性層2〇和該被動層18做爲遮 罩。在圖示於圖4A到4B的該處理步驟的期間和該步驟之後 ’接著執行RF預先清除,以移除形成於該連結板丨4上原有的 金屬氧化物層。此氧化物層的厚度爲,例如,約1〇毫米。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝--------訂--------- 經濟部智慧財產局員工消費合作社印製 經濟部中央標準局員工消費合作社印製 4^0775 A7 B7 五、發明説明() 5 如圖π於圖6,以不打破眞空的方式將一種籽層丨5濺鍍於 該晶圓10上。該種籽層15係爲實質上與該基墊板丨4的導電 基本材料相同的材料。例如,由於該基墊板14已圖示爲是由 銅基本材料所形成,該種籽層丨5也爲一銅基本材料。如已 對該基墊板14加以敘述過的,只要該材料實質上與該基墊 板14的基本材料相同,可將其它材料使用於該種籽層1 5上 ,例如銅合金,鎳釩,或任何材料,其中該基本材料爲導通 金屬並且不會與該焊鍚材料起反應而產生不想要的效應。 此濺鍍種籽層15的厚度爲,例如,小於1〇〇毫米。一較薄的濺 鍍種籽層1 5的優點爲,在稍後的處理步驟期間,該較薄的 種籽層1 5能有較有效率的蝕刻。該濺鍍種籽層丨5充作本發 明具體實例中該晶圓基體的電子連續性和膠層。 在圖7中,形成一光阻層24。圖8圖示一打線17的形成,係 與該基墊板14連續並且實質上以與該基墊板14相同的導電 基本材料所形成。例如,透過電鍍·、蒸發或濺鍍,經由在該 基土板14之上的開口而形成該打線17。由於已圖示該基塾 板14係以銅基本材料所形成,最好,該打線”的導電基本 材料也爲銅。然而,该打線1 7的基本材料也可爲,例如,銅 合金,鎳釩,或任何材料,其中該基本材料爲導通金屬,不 會與焊鍚材料起反應而產生不想要的效應,並且只要該材 料實質上與該基塾板14的基本材料相同。圖示之該打線17 上層表面高度低於該光阻層24的上層表面高度。該打線17 的厚度最好大到在該裝置的壽命期間内不會整個被該焊鍚 材料消耗掉。例如,對個人通訊產品而言,該打線17大於 -8- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) -裝 經濟部中央標準局員工消費合作社印製 490775 五、發明説明( 約5微米。 在圖9, 一焊錫層26被電錢或蒸發在該打輯之上。通常 所使用的及材料爲一鬲的鉛’錫,意味著大於⑽重量百分 比的鉛和1 〇重量百分!^的祖 ®刀比的錫;低共熔的鉛/錫,爲63重量百 分比的錯和37重量百分比的錫。其它可能的焊錫爲無錯或 裱保的焊錫,如錫銀、錫銀銅、錫銀鉍等。在圖1〇中,移 除該光阻層24,並且使用標準姓刻方法移除該種杆層15。 圖11孩焊錫層26已使用適於所使用的該焊錫材料的溫度輪 庸以高溫迴焊,並且暴露該焊錫結構供後續的高溫迴焊黏 結。通常由該高溫迴焊方法形成一凸塊或在該打㈣四週 的球狀月豆。在一具體實例中,使用圖示於圖^ ^内的結構做 爲:已控制的可折疊的晶片連接,該電子連接係在該晶粒 和炫基之間’在一覆晶結構上’包括一電子裝置在一半 導體基體内。 在本發明之另—具體實例中,未形成該烊錫層26,並且 暴露該打線供後續黏結至另一結構。因而,在圖8該處理 步驟之後,使用標準蝕刻方法移除該光阻層24,如圖⑵斤 :。使用標準方法蝕刻該種籽層15以形成該打線17,如圖 π於圖13。在该種籽層丨5的蝕刻期間,也蝕刻一部份的該 打線Π。然而,蝕刻的量若不是很不明顯,就是形成該打 線17的材料的量補償了當蝕刻該種籽層15時所蝕刻的該打 線π部份的材料。 圖14到16特別圖示以蒸發形成該打線17。例如,在圖5該 蝕刻方法步驟心後,將一遮罩5丨,例如鉬(M〇iybdenum), --------^-裝-- (請先閱讀背面之注意事項再填寫本頁) 、11 -9- 經濟部中央榡準局員工消費合作衽印製 490775 A7 ----—_ B7 五、發明説明(7 ) '一~— - 置於該彈性層20上。圖15圖示以蒸發將該打線_成至該 斤要的厚度’其中孩打線17的基本材料實質上與該基塾板 14的基本材料相同。在形成該打線㈤蒸發方法期間,該 材料的已瘵發層5 3也可形成於接著要被移除的該遮罩 1上右有必要,將鉛/錫蒸發於打線17上形成焊錫層丨9, 圖16所不。移除該遮罩5丨並且該焊錫層1 9可能被高溫迴 、于(、後、黏結至另一結構。在圖示於圖14到16的具體實例 中,由於該打線和焊錫層不需電子匯流排,因此不需該種 籽層1 5。 圖17Α到17Β圖示一應用,其中該打線17(不需焊錫層或焊 錫結構)接著附著至另一結構。一半導體基體30,具有一電 子裝置例如’覆晶晶粒,形成於其上,包括如本發明之複 數個互連結構32,電子地連接至該半導體基體3〇。該複數 個互連結構32使用由具有導通濾波器34的絕緣矩陣36所構 成的材料連接至測試板4〇上的複數個導通墊38。當加熱和 加壓時,該導通濾波器34,對準該複數個互連結構32和導 通塾3 8 ’將該複數個互連結構32電子連接至在該測試板4〇 上的複數個導通墊3 8,如圖17Β所示。 该覆晶結構之互連結構製造和封裝的進一步處理步驟通 常包括加熱供焊錫結構或凸塊的高溫迴焊黏結;在基墊板 和半導體結構之電子裝置間形成適當的互連;並且將打線 連結或黏結至一板或半導體結構。這些進一步的處理步驟 爲傳統的並且不需在此重覆敘述。相同地,在此所揭露的 該原則處理步驟可能與其它對那些熟於先前技術者早已很 -10- 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) •裝· 、11 ^/75 A7 B7 、發明說明(8 ) :瞭的步驟結合在-起。雖然爲了解釋的目的僅圖示一草 —打,和凸塊’應了解在實務上,先前技術中早已廣泛應 用在單互連結構上製造多個打線和凸塊。 在前述之説明書中,已參考特定具體實例加以敌述本發 j然而’對热於先可技術者而言,可從事各種改良和改 變而不偏離在了述該申請專利€圍中所説明的本發明範嘴 。據此,應以説明的而非限制的方式來看待該説明書和附 圖,並且意圖將所有此種改良包括於本發明範嘴内。 已於上面敘述過關於特定具體實例之利益、其它優點和 對問題的解決方案。然而,制益、優點、對問題的解決 万案和能使得任何利益、優點或解決方案發生或變得更明 白的任何s件不需解釋爲任何或所有該中請專利範圍重要 的、必備的或必要的特色或元件。如在此所使用的該術 語”包括”或任何其它的變化,意圖涵蓋—非除外的包含, 以致於:處理’万法’物件或包括元件表的裝置並不僅包 括那些7C件’但可能包括未清楚地列出或所固有的此處理 ’方法,物件或裝置的其它元件。 裝·-------訂—------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 適 度 張一紙 本 釐一公 197 2 X 10 2 /V 格 規 A4 ls)A N (c 準 標 家 國

Claims (1)

  1. 490775
    經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 1 · 一種覆晶結構,包括; 一半導體基體,包括一電子裝置形成於其上; 一基墊板’在該半導體基體上,並且電氣連接至該電 子裝置; 一障礙層’位於該基墊板和該半導體基體之間;並且 一打線,形成於該基墊板上,並且從該基墊板延伸出 ’其中該打線和基墊板係連續並且由實質上相同的 導電基本材料所形成。 2·如申請專利範圍第1項之覆晶結構,尚包括: 一被動層,在該半導體基體上,其中該被動層定義一 在该基墊板上方的開口,該打線經由此開口而形成。 3 ·如申叫專利範圍第2項之覆晶結構,其中該被動層包括定 義該開口的邊緣,並且其中該被動層和該邊緣爲一彈 性層所覆蓋。 4·如申請專利範圍第3項之覆晶結構,其中該彈性層係由— 聚亞胺薄膜所構成。 5·如申請專利範圍第丨項之覆晶結構,其中該打線被暴露以 供後續的黏結至另一結構。 、 6. 如申請專利範圍第丨項之覆晶結構,尚包括: 一焊錫結構形成於該打線上,其中該焊錫結構被暴霞 供後續高溫迴焊黏至另一結構。 】、路 7. 如申請專利範圍第6項之覆晶結構,其中該焊锡結構係 下列各物中所選出導電材料所形成: :由 、场、踢和· 、錫和銀、以及錫、銀和銅。 σ _ '12- 本紙張尺度適用中_家標準(CNS)A4規_在(21〇 χ 297公爱) AW ---I----二π—-------- (請先閱讀背面之注意事項再填寫本頁) 490775 A8 B8 C8 D8 六、申睛專利範圍 8·如申請專利範圍第1項之覆晶結構,其中該導電基本材料 爲一金屬。 9.如申請專利範圍第7項之覆晶結構,其中該金屬係由下列 各物中所選出:銅、鎳和鎳釩。 1〇· —種製造互連結構之方法,包括: 形成一基塾板; 在泫互連結構上形成一被動層,其中該被動層包括定 義一在該基墊板上的開口的邊緣; 經由該開口在該基墊板上直接形成一打線並且從該基 塾板延伸出;並且 其中該打線和基墊板皆爲連續並且由實質上相同的導 電基本材料所形成。 11 ·如申請專利範圍第10項之方法,其中該打線被暴露供後 續黏結至另一結構。 12 ·如申請專利範圍第1 〇項之方法,尚包括: 在該打線上形成一焊錫結構,其中該焊錫結構被暴露 供後續鬲溫迴焊·黏結至另一結構。 13.如申請專利範圍第1〇項之方法,尚包括: 以一彈性層覆蓋該被動層和該被動層的邊緣。 14 ·如申凊專利範圍第13項之方法,其中該彈性層係由一聚 亞胺薄膜所構成。 15.如申請專利範圍第1〇項之方法,其中形成該打線的步驟 尚包括: (a)透過蒸發將該打線從該基墊板延伸出;使用實質上 相同的導電基本材料做爲該基墊板。 ... -13- _ (請先閱讀背面之注意事項再填寫本頁) · ammmmm —Bi ί 1_1 ·1 ϋ 訂---- 經濟部智慧財產局員工消費合作社印製 本紙張尺度_ +關家標準(CNS;A4規格(210 297公釐)
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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US7902679B2 (en) * 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6614117B1 (en) * 2002-06-04 2003-09-02 Skyworks Solutions, Inc. Method for metallization of a semiconductor substrate and related structure
KR100476301B1 (ko) * 2002-07-27 2005-03-15 한국과학기술원 전기도금법에 의한 반도체 소자의 플립칩 접속용 ubm의형성방법
US6878633B2 (en) * 2002-12-23 2005-04-12 Freescale Semiconductor, Inc. Flip-chip structure and method for high quality inductors and transformers
JP2004247530A (ja) * 2003-02-14 2004-09-02 Renesas Technology Corp 半導体装置及びその製造方法
US7470997B2 (en) * 2003-07-23 2008-12-30 Megica Corporation Wirebond pad for semiconductor chip or wafer
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
JP4219951B2 (ja) * 2006-10-25 2009-02-04 新光電気工業株式会社 はんだボール搭載方法及びはんだボール搭載基板の製造方法
JP4682964B2 (ja) * 2006-10-30 2011-05-11 株式会社デンソー 半導体装置およびその製造方法
US20120248599A1 (en) * 2011-03-28 2012-10-04 Ring Matthew A Reliable solder bump coupling within a chip scale package
US9324667B2 (en) 2012-01-13 2016-04-26 Freescale Semiconductor, Inc. Semiconductor devices with compliant interconnects
KR102315276B1 (ko) 2014-10-06 2021-10-20 삼성전자 주식회사 집적회로 소자 및 그 제조 방법

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5071518A (en) 1989-10-24 1991-12-10 Microelectronics And Computer Technology Corporation Method of making an electrical multilayer interconnect
JP3141364B2 (ja) * 1992-05-06 2001-03-05 住友電気工業株式会社 半導体チップ
KR960011855B1 (ko) * 1992-10-08 1996-09-03 삼성전자 주식회사 반도체장치의 범프 형성방법
US5466635A (en) 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US5447264A (en) * 1994-07-01 1995-09-05 Mcnc Recessed via apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon
JPH0837190A (ja) * 1994-07-22 1996-02-06 Nec Corp 半導体装置
JP2701751B2 (ja) * 1994-08-30 1998-01-21 日本電気株式会社 半導体装置の製造方法
EP0751566A3 (en) * 1995-06-30 1997-02-26 Ibm Metal thin film barrier for electrical connections
DE19616373A1 (de) 1996-04-24 1997-08-14 Fraunhofer Ges Forschung Herstellung galvanisch abgeformter Kontakthöcker
JPH1092924A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 半導体装置及びその製造方法
JPH10209154A (ja) * 1997-01-21 1998-08-07 Oki Electric Ind Co Ltd 半導体装置
US6441487B2 (en) * 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
US6251528B1 (en) * 1998-01-09 2001-06-26 International Business Machines Corporation Method to plate C4 to copper stud
US5977632A (en) * 1998-02-02 1999-11-02 Motorola, Inc. Flip chip bump structure and method of making
US6075290A (en) 1998-02-26 2000-06-13 National Semiconductor Corporation Surface mount die: wafer level chip-scale package and process for making the same
US5943597A (en) * 1998-06-15 1999-08-24 Motorola, Inc. Bumped semiconductor device having a trench for stress relief
JP2000091369A (ja) 1998-09-11 2000-03-31 Sony Corp 半導体装置及びその製造方法
US6218732B1 (en) * 1998-09-15 2001-04-17 Texas Instruments Incorporated Copper bond pad process
JP3577419B2 (ja) * 1998-12-17 2004-10-13 新光電気工業株式会社 半導体装置およびその製造方法
US6180505B1 (en) 1999-01-07 2001-01-30 International Business Machines Corporation Process for forming a copper-containing film
JP2000228006A (ja) * 1999-02-05 2000-08-15 Alps Electric Co Ltd ボンディングパットおよびバンプを用いた接合体、および磁気ヘッド装置

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US6429531B1 (en) 2002-08-06
KR100818902B1 (ko) 2008-04-04
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CN1473359A (zh) 2004-02-04
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