CN120279967A - 存储器系统 - Google Patents

存储器系统 Download PDF

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Publication number
CN120279967A
CN120279967A CN202510440484.XA CN202510440484A CN120279967A CN 120279967 A CN120279967 A CN 120279967A CN 202510440484 A CN202510440484 A CN 202510440484A CN 120279967 A CN120279967 A CN 120279967A
Authority
CN
China
Prior art keywords
data
output
pad
read
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202510440484.XA
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English (en)
Chinese (zh)
Inventor
山本健介
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Kioxia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kioxia Corp filed Critical Kioxia Corp
Priority to CN202510440484.XA priority Critical patent/CN120279967A/zh
Publication of CN120279967A publication Critical patent/CN120279967A/zh
Pending legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604Improving or facilitating administration, e.g. storage management
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063Control signal output circuits, e.g. status or busy flags, feedback command signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7201Logical to physical mapping or translation of blocks or pages

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
CN202510440484.XA 2019-09-13 2019-09-13 存储器系统 Pending CN120279967A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202510440484.XA CN120279967A (zh) 2019-09-13 2019-09-13 存储器系统

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN202510440484.XA CN120279967A (zh) 2019-09-13 2019-09-13 存储器系统
CN201980098583.7A CN114127697B (zh) 2019-09-13 2019-09-13 存储器系统
PCT/JP2019/036211 WO2021049033A1 (ja) 2019-09-13 2019-09-13 メモリシステム

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201980098583.7A Division CN114127697B (zh) 2019-09-13 2019-09-13 存储器系统

Publications (1)

Publication Number Publication Date
CN120279967A true CN120279967A (zh) 2025-07-08

Family

ID=74867014

Family Applications (2)

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CN202510440484.XA Pending CN120279967A (zh) 2019-09-13 2019-09-13 存储器系统
CN201980098583.7A Active CN114127697B (zh) 2019-09-13 2019-09-13 存储器系统

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201980098583.7A Active CN114127697B (zh) 2019-09-13 2019-09-13 存储器系统

Country Status (5)

Country Link
US (3) US11868648B2 (https=)
JP (1) JPWO2021049033A1 (https=)
CN (2) CN120279967A (https=)
TW (2) TWI861483B (https=)
WO (1) WO2021049033A1 (https=)

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JPWO2021049033A1 (https=) * 2019-09-13 2021-03-18
KR20220142660A (ko) * 2021-04-15 2022-10-24 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
KR20220157155A (ko) * 2021-05-20 2022-11-29 에스케이하이닉스 주식회사 스토리지 장치 및 그 동작 방법
JP7703473B2 (ja) 2022-03-18 2025-07-07 キオクシア株式会社 半導体記憶装置
JP2024131386A (ja) * 2023-03-16 2024-09-30 キオクシア株式会社 メモリシステム
US12265708B2 (en) * 2023-06-27 2025-04-01 Viavi Solutions Inc. Timing alignment for data structure read commands

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Also Published As

Publication number Publication date
US20220137870A1 (en) 2022-05-05
US20240094941A1 (en) 2024-03-21
CN114127697A (zh) 2022-03-01
TWI764251B (zh) 2022-05-11
TWI861483B (zh) 2024-11-11
TW202115568A (zh) 2021-04-16
CN114127697B (zh) 2025-04-29
US20250021260A1 (en) 2025-01-16
TW202230124A (zh) 2022-08-01
US12135898B2 (en) 2024-11-05
WO2021049033A1 (ja) 2021-03-18
US11868648B2 (en) 2024-01-09
JPWO2021049033A1 (https=) 2021-03-18

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