TWI861483B - 半導體記憶裝置 - Google Patents

半導體記憶裝置 Download PDF

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Publication number
TWI861483B
TWI861483B TW111112753A TW111112753A TWI861483B TW I861483 B TWI861483 B TW I861483B TW 111112753 A TW111112753 A TW 111112753A TW 111112753 A TW111112753 A TW 111112753A TW I861483 B TWI861483 B TW I861483B
Authority
TW
Taiwan
Prior art keywords
data
output
signal
signals
dqs
Prior art date
Application number
TW111112753A
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English (en)
Chinese (zh)
Other versions
TW202230124A (zh
Inventor
山本健介
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication of TW202230124A publication Critical patent/TW202230124A/zh
Application granted granted Critical
Publication of TWI861483B publication Critical patent/TWI861483B/zh

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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604Improving or facilitating administration, e.g. storage management
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063Control signal output circuits, e.g. status or busy flags, feedback command signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7201Logical to physical mapping or translation of blocks or pages

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
TW111112753A 2019-09-13 2020-08-25 半導體記憶裝置 TWI861483B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
WOPCT/JP2019/036211 2019-09-13
PCT/JP2019/036211 WO2021049033A1 (ja) 2019-09-13 2019-09-13 メモリシステム

Publications (2)

Publication Number Publication Date
TW202230124A TW202230124A (zh) 2022-08-01
TWI861483B true TWI861483B (zh) 2024-11-11

Family

ID=74867014

Family Applications (2)

Application Number Title Priority Date Filing Date
TW111112753A TWI861483B (zh) 2019-09-13 2020-08-25 半導體記憶裝置
TW109128932A TWI764251B (zh) 2019-09-13 2020-08-25 記憶體系統

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW109128932A TWI764251B (zh) 2019-09-13 2020-08-25 記憶體系統

Country Status (5)

Country Link
US (3) US11868648B2 (https=)
JP (1) JPWO2021049033A1 (https=)
CN (2) CN120279967A (https=)
TW (2) TWI861483B (https=)
WO (1) WO2021049033A1 (https=)

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JPWO2021049033A1 (https=) * 2019-09-13 2021-03-18
KR20220142660A (ko) * 2021-04-15 2022-10-24 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
KR20220157155A (ko) * 2021-05-20 2022-11-29 에스케이하이닉스 주식회사 스토리지 장치 및 그 동작 방법
JP7703473B2 (ja) 2022-03-18 2025-07-07 キオクシア株式会社 半導体記憶装置
JP2024131386A (ja) * 2023-03-16 2024-09-30 キオクシア株式会社 メモリシステム
US12265708B2 (en) * 2023-06-27 2025-04-01 Viavi Solutions Inc. Timing alignment for data structure read commands

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TWI298161B (en) * 2005-07-06 2008-06-21 Fujitsu Ltd Ferroelectric storage device
TWI357082B (en) * 2005-04-30 2012-01-21 Hynix Semiconductor Inc Semiconductor memory device and method for stably
JP2013050996A (ja) * 2006-10-04 2013-03-14 Marvell World Trade Ltd フラッシュメモリデバイスを指定する集積回路
TWI463492B (zh) * 2006-12-13 2014-12-01 Samsung Electronics Co Ltd 電阻式記憶體裝置
TWI579860B (zh) * 2015-03-23 2017-04-21 國立成功大學 一種記憶細胞及具該記憶細胞的內容可定址記憶體
US20170125092A1 (en) * 2015-10-29 2017-05-04 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and memory system
TWI585774B (zh) * 2011-12-12 2017-06-01 三星電子股份有限公司 記憶體元件以及用於記憶體元件之感測及閂鎖電路
CN107025931A (zh) * 2016-01-29 2017-08-08 台湾积体电路制造股份有限公司 静态随机存取存储器阵列、追踪单元以及阵列配置方法
JP2018163440A (ja) * 2017-03-24 2018-10-18 東芝メモリ株式会社 メモリシステム

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JP2002150789A (ja) * 2000-11-09 2002-05-24 Hitachi Ltd 不揮発性半導体記憶装置
US6788593B2 (en) * 2001-02-28 2004-09-07 Rambus, Inc. Asynchronous, high-bandwidth memory component using calibrated timing elements
JP4237109B2 (ja) * 2004-06-18 2009-03-11 エルピーダメモリ株式会社 半導体記憶装置及びリフレッシュ周期制御方法
JP4967452B2 (ja) * 2006-05-18 2012-07-04 富士通セミコンダクター株式会社 半導体メモリ
KR100764060B1 (ko) * 2006-09-29 2007-10-09 삼성전자주식회사 불휘발성 메모리 장치 및 시스템 그리고 그것을 위한메모리 셀 어레이 구조
US20080086590A1 (en) 2006-10-04 2008-04-10 Masayuki Urabe Flash Memory Control Interface
US20080273389A1 (en) * 2007-03-21 2008-11-06 Micron Technology, Inc. Flash memory cells, NAND cell units, methods of forming NAND cell units, and methods of programming NAND cell unit strings
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KR102403339B1 (ko) 2016-02-22 2022-06-02 에스케이하이닉스 주식회사 데이터 정렬 장치
KR102902406B1 (ko) 2017-02-14 2025-12-19 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법
JP2019128829A (ja) * 2018-01-25 2019-08-01 東芝メモリ株式会社 半導体記憶装置及びメモリシステム
JP2020047340A (ja) 2018-09-19 2020-03-26 キオクシア株式会社 不揮発性メモリ及びメモリシステム
JPWO2021049033A1 (https=) * 2019-09-13 2021-03-18
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JP7282699B2 (ja) 2020-01-21 2023-05-29 キオクシア株式会社 半導体記憶装置

Patent Citations (9)

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Publication number Priority date Publication date Assignee Title
TWI357082B (en) * 2005-04-30 2012-01-21 Hynix Semiconductor Inc Semiconductor memory device and method for stably
TWI298161B (en) * 2005-07-06 2008-06-21 Fujitsu Ltd Ferroelectric storage device
JP2013050996A (ja) * 2006-10-04 2013-03-14 Marvell World Trade Ltd フラッシュメモリデバイスを指定する集積回路
TWI463492B (zh) * 2006-12-13 2014-12-01 Samsung Electronics Co Ltd 電阻式記憶體裝置
TWI585774B (zh) * 2011-12-12 2017-06-01 三星電子股份有限公司 記憶體元件以及用於記憶體元件之感測及閂鎖電路
TWI579860B (zh) * 2015-03-23 2017-04-21 國立成功大學 一種記憶細胞及具該記憶細胞的內容可定址記憶體
US20170125092A1 (en) * 2015-10-29 2017-05-04 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and memory system
CN107025931A (zh) * 2016-01-29 2017-08-08 台湾积体电路制造股份有限公司 静态随机存取存储器阵列、追踪单元以及阵列配置方法
JP2018163440A (ja) * 2017-03-24 2018-10-18 東芝メモリ株式会社 メモリシステム

Also Published As

Publication number Publication date
US20220137870A1 (en) 2022-05-05
CN120279967A (zh) 2025-07-08
US20240094941A1 (en) 2024-03-21
CN114127697A (zh) 2022-03-01
TWI764251B (zh) 2022-05-11
TW202115568A (zh) 2021-04-16
CN114127697B (zh) 2025-04-29
US20250021260A1 (en) 2025-01-16
TW202230124A (zh) 2022-08-01
US12135898B2 (en) 2024-11-05
WO2021049033A1 (ja) 2021-03-18
US11868648B2 (en) 2024-01-09
JPWO2021049033A1 (https=) 2021-03-18

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