CN1158711C - 存储器单元 - Google Patents
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- 230000003071 parasitic effect Effects 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title description 3
- 239000003990 capacitor Substances 0.000 claims abstract description 46
- 238000009792 diffusion process Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims description 42
- 239000002019 doping agent Substances 0.000 claims description 39
- 230000015654 memory Effects 0.000 claims description 16
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 65
- 150000004767 nitrides Chemical class 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 238000001020 plasma etching Methods 0.000 description 11
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 10
- 238000011049 filling Methods 0.000 description 10
- 238000000137 annealing Methods 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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Abstract
一种沟槽电容器,具有邻近轴环的扩散区,以增加寄生MOSFET的栅阈值电压。它能使用较薄的轴环,同时可以得到可以接受的漏电流。在一个实施例中,扩散区是自对准的。
Description
技术领域
本发明一般涉及一种半导体器件,特别涉及一种沟槽电容存储器单元。
背景技术
集成电路(ICs)中使用电容器来进行电荷存储。例如包括如动态RAMs(DRAMs)等随机存储存储器(RAMs)的存储器件在电容器中存储电荷。电容器中的电荷电平(“0”或“1”)作为数据位。
DRAM IC包括由行和列互联的存储器单元阵列。通常行和列连接分别为字线和位线。通过激活合适的字线和位线来实现从或向存储器单元的数据读取或数据写入。
DRAM存储单元通常包括连接到电容器上的金属氧化物半导体场效应晶体管(MOSFET)。这种晶体管包括栅及第一和第二扩散区。根据晶体管的工作,第一和第二扩散区分别指源或漏。为了方便,术语源和漏可以互换。晶体管的栅连接到字线、源连接到位线。晶体管的漏连接到电容器或存储节点。给栅加合适的电压导通晶体管,形成到电容器的导电通道。当晶体管截止时该导电通道关闭。
在DRAMs中通常使用沟槽电容器。沟槽电容器为形成在硅衬底中的三维结构。普通的沟槽电容器包括腐蚀进衬底的沟槽。通常用n+掺杂的多晶来填充沟槽,该多晶作为电容器(指存储节点)的一个极板。例如,通过n+掺杂剂从掺杂源到包围沟槽下部的衬底区的外扩散来形成电容器的第二个极板,即“掩埋极板”。提供介质层以分开形成电容器的两个极板。为了防止沿沟槽上部产生的寄生漏电或将之减少到可接受的水平,在其中提供有足够厚度的氧化物轴环。通常,氧化物轴环应厚得足以将寄生漏电减小到小于1fA/单元。
不断缩小器件的要求使高密度及小特征尺寸和小单元面积的DRAMs的设计更容易。例如,设计规则已经从0.25μm降低到约
0.12μm和更低。在小尺寸的基本规则下,存储节点扩散与掩埋极板之间的垂直寄生MOSFET漏电的控制由于较小的沟槽尺寸而变得困难。这是因为小沟槽开口需要相应减小轴环的厚度以容易填充沟槽。但是,为了将寄生漏电降低到可接受的水平,根据工作电压条件,轴环的厚度需要为约25-70nm。这样厚的轴环阻碍较小沟槽的填充。
减小寄生漏电的另一个技术是增加晶体管的阱中的掺杂剂浓度。但是,提高掺杂剂浓度增大了耗尽区中的电场,这导致结漏电的急剧增加。当硅中存在晶体缺陷时更是如此。
由此可知,希望提供有非常低的寄生漏电的小沟槽电容器。
发明内容
因此本发明涉及沟槽电容存储器单元。根据一个实施例,如果在衬底中提供扩散区,则它邻近轴环区。扩散区与轴环区自对准。扩散区增大了由节点扩散区、掩埋极板、和轴环构成的寄生MOSFET晶体管的栅阈值电压。通过增加栅阈值电压,可以在电容器中使用较薄的轴环,同时实现所希望的漏电。
本发明提供一种存储器单元,包括:晶体管,晶体管包括栅极及第一和第二扩散区;形成在衬底中的沟槽电容器,其中沟槽电容器包括沟槽上部的介质轴环、衬底中包围沟槽电容器下部的掩埋扩散区、在轴环上面电连接晶体管与电容器的节点扩散区;第三扩散区,第三扩散区位于邻近轴环的衬底中并且包括掺杂剂,该掺杂剂包括浓度在5×1017到2×1018cm-3之间的硼,该浓度足够增加寄生晶体管的栅阈值电压,由此降低漏电流,寄生晶体管由轴环、掩埋扩散区和节点扩散区形成。
本发明使得小沟槽电容器的寄生漏电将非常低。
附图说明
图1表示常规沟槽电容器DRAM单元;
图2表示根据本发明一个实施例的沟槽电容器DRAM单元;
图3a-e表示形成本发明一个实施例的沟槽电容器DRAM单元的工艺。
具体实施方式
本发明涉及集成电路(IC)中使用的沟槽电容器存储器单元。例如IC包括随机存取存储器(RAM)、动态随机存取存储器(DRAM)、或同步DRAM(SDRAM)。如专用IC ASIC、合并DRAM逻辑电路(嵌埋DRAM)、或其它逻辑电路等应用的IC也有用。
通常在晶片上平排形成大量ICs。完成工艺后,切割晶片,将ICs分离成分立芯片。然后封装芯片,得到用于如计算机系统、蜂窝电话、个人数字助手(PDAs)等用户产品和其它电子产品等最终产品。
参见图1,该图示出了使用n沟道MOSFET的常规沟槽电容器DRAM单元100,以容易讨论本发明。例如,Nesbit等在
有自对准掩埋条(BEST)的0.6μm 2 256Mb的沟槽DRAM单元,IEDM 93-627中说明了这种常规沟槽电容器DRAM单元,此处引用作为参考。通常用字线和位线互联单元阵列以形成DRAM芯片。
DRAM单元100包括形成在衬底101上的沟槽电容器160。通常用重掺n型掺杂剂的多晶硅(多晶)161填充沟槽。多晶作为电容器的一个极板,称为“存储节点”。掺有n型掺杂剂的掩埋极板165包围沟槽的下部。在沟槽的上部是降低寄生漏电的轴环168。节点介质163分开电容器的两个极板。提供包括n型掺杂剂的掩埋阱170以连接阵列中DRAM单元的掩埋极板。掩埋阱上面是p-阱173。p阱提供正确的掺杂类型和连接,使低漏电N~FET正确工作。
DRAM单元还包括晶体管110。晶体管包括栅112、包括n型掺杂剂的源扩散区113、漏扩散区114。如前面讨论的,源漏的设计取决于晶体管的工作。栅作为字线。由于字线栅连接到电容器,通常称它为“有源字线”。晶体管到电容器的连接通过称为“节点扩散”的扩散区125来实现。
提供浅沟槽隔离(STI)180将DRAM单元与其它单元或器件隔离。如图所示,字线120形成在沟槽上,并用STI将它们隔离。字线120称为“跨越字线(passing wordline)”。这种构型称为折合位线结构。
层间介质层189形成在字线上。作为位线的导电层形成在层间介质层上。在层间介质层中提供位线接触开口186,以使扩散区113与位线190接触。
如前所述,制备较小沟槽尺寸的小尺寸基本规则需要较薄的轴环,以便能用多晶填充沟槽。但是,容许填充较小沟槽的较薄轴环不能将寄生漏电降低到所要求水平。
参见图2,该图示出了根据本发明的沟槽DRAM单元200。如图所示,沟槽电容器160形成在衬底101中。存储节点161用有第一导电类型的重掺杂多晶硅(多晶)来填充。在一个实施例中,第一导电类型为n型,其中n型掺杂剂包括如砷(As)或磷(P)。n型掺杂的掩埋极板包围沟槽的下部。分离存储节点和掩埋极板的是节点介质层263。
在衬底表面下设置n型掩埋阱270。掩埋n阱中掺杂剂的峰值浓度大约在掩埋极板的顶部,以将它公共连接到阵列中的DRAM单元的各掩埋极板。在掩埋n阱上面是包括第二导电类型掺杂剂的掺杂区。在一个实施例中,第二导电类型为包括硼(B)等掺杂剂的p型。p阱掺杂区用来给阵列晶体管提供合适的掺杂,在阱中通常有约3-8×1017cm-3的峰值掺杂浓度。
在沟槽的上部设置介质轴环268。该轴环包括:例如TEOS分解形成的氧化物。轴环是扩散区225和掩埋极板之间寄生MOSFET的栅氧化物,形成寄生晶体管,其栅在沟槽中用掺杂多晶表示。因此,轴环应足够厚,以提高寄生晶体管的栅阈值电压(VT)。
根据本发明的一个实施例,在邻近沟槽电容器的轴环区的衬底上设置扩散区269。扩散区包括有与掩埋极板及扩散区225相反导电类型的掺杂剂。在一个实施例中,扩散区269包括B等p型掺杂剂。扩散区中B的浓度足够高,以增加寄生晶体管的VT,由此实现降低的漏电流。在一个实施例中,B的浓度在约5×1027到2×1018cm-3之间。扩散区269允许使用较薄轴环,而不会导致大于所希望的寄生漏电。
DRAM单元还包括晶体管110,晶体管110包括栅112、源113、和漏114。通过注入如磷(P)等n型掺杂剂来形成漏和源。通过节点扩散区125来实现晶体管与电容器的连接。
为了将DRAM单元与阵列中其它器件或单元隔离开,提供浅沟槽隔离(STI)280。如图所示,由STI隔离的跨越字线220在沟槽上面,形成折合位线结构。也可使用其它位线结构,如开路(open)或开路折合(open-folded)结构。
在字线的上面是层间介质层289。层间介质层包括:例如硼磷硅玻璃(BPSG)等掺杂硅酸盐玻璃。也可以用其它掺杂硅酸盐玻璃,如磷硅玻璃(PSG)或硼硅玻璃(BSG)。或者,可以用如TEOS等不掺杂硅酸盐玻璃。位线形成在介质层上面,通过位线接触开口接触源。通过给字线和位线提供合适的电压实现DRAM单元的存取,使数据能写入沟槽电容器或从其中读出。
图3a-e表示根据本发明的一个实施例形成DRAM单元的工艺。如前面所说,该工艺形成n沟道DRAM单元。但是,本领域的技术人员知道,该工艺可以容易地用来形成p沟道DRAM单元。
参见图3a,提供其上制备了DRAM单元的衬底301。例如,衬底可以是硅晶片。也可以用其它衬底,如绝缘体上的硅(SOI)或其它半导体材料。例如,衬底可以是轻掺杂或重掺杂,掺杂剂有预定导电类型,以得到所需的电特性。衬底的主表面不重要,可以用任何晶向,如(100)、(110)、或(111)。在一个例示实施例中,衬底用如B等p型掺杂剂轻掺杂(P-)。B的浓度约为1-2×1016cm-3在衬底中还形成包括P或As掺杂剂的n型掩埋阱370。已知有各种形成掩埋阱的技术。约1×1017-2×1018cm-3的n型掺杂剂的峰值浓度的位置在其下面将是绝缘轴环氧化物底部的衬底区内。
在衬底表面形成基层堆叠体395。基层堆叠体包括:例如,基层氧化层396、抛光停止层397、硬掩模层397。抛光停止层包括如氮化物,硬掩模包括TEOS。其它材料如BPSG、BSG、或SAUSG也可用于硬掩模层。
用常规光刻技术构图硬掩模层,以限定将要形成存储沟槽的区315。这种技术包括淀积光刻胶层399、用曝光源和掩模对它选择性曝光。根据是正胶还是负胶,在显影中来去除光刻胶的曝光部分或未曝光部分。因此,区315中的基层堆叠体不受光刻胶层的保护。然后去除区315中的基层堆叠体(硬掩模、基层氮化物、基层氧化物),暴露下面的硅衬底。例如用反应离子刻蚀(RIE)来去除基层堆叠层。
用光刻胶和基层堆叠层作为注入掩模,向衬底注入掺杂剂,增加垂直寄生晶体管的阈值电压(VT)。注入到衬底中的掺杂剂的导电类型与掩模板中的相反。在一个实施例中,导电类型为包括B掺杂剂的p型。用足够的能量和剂量进行注入,使B掺杂剂的峰值浓度位于沟槽电容器的轴环区。由此可以增加寄生晶体管的VT,将寄生漏电减小到所需的水平。寄生漏电减小到小于或等于1fa/单元。在一个实施例中,能量和剂量约为200-350keV和约1.5-3.5×1013cm-2,为220-300keV和约1.5-2.5×1013cm-2更好。这样,寄生晶体管VT调节注入的好处是自对准。即VT注入使用基层堆叠体作为注入掩模,因此不需要另外的光刻步骤来形成扩散区。
注入后,去除光刻胶层。然后,对衬底进行足够长的退火,使B掺杂剂从沟槽区横向扩散,形成扩散区369。如图所示,扩散区369横向延伸超过作为沟槽侧壁轮廓的垂直点线368。延伸超过点线的部分扩散区用于增加寄生晶体管的VT。进行足够的退火,将掺杂剂从侧壁(用点线368表示)推进20-150nm。通常,在约850-950℃退火约1-10min,最好在约850℃退火约5min。也可以使用快速热退火(RTA)。
参见图3b,用常规技术继续进行形成沟槽电容器DRAM单元的工艺。例如Nesbit等在
有自对准掩埋条(BEST)0.6μm 2 256Mb沟槽DRAM单元,IEDM 93-627中说明过这些技术,这里已经引用作为参考。用基层堆叠体作为RIE掩模,进行各向异性腐蚀,如RIE。RIE去除衬底材料,形成深沟槽303。如图所示,扩散区369保留在要形成轴环的衬底区中。由于用RIE去除注入离子的衬底区域,在器件的有源区没有注入损伤。这样,注入对掩埋条结漏电没有不良影响,和产生硅缺陷的覆盖式注入一样。
参照图3c,形成n型掩埋极板365。例如通过提供掺杂源并将掺杂剂外扩散进衬底中形成掩埋极板。这包括用一层砷硅玻璃(ASG)作为掺杂源来衬垫沟槽。在ASG上形成TEOS薄层。TEOS确保填充沟槽的光刻胶的粘附性。然后用光刻胶填充沟槽。随后使光刻胶凹下,暴露沟槽上部的ASG层。用湿法腐蚀工艺去除暴露的ASG。对ASG选择性地从沟槽去除剩下部分的光刻胶。介质层包括,例如,在沟槽上淀积TEOS。TEOS层用于防止砷自掺杂暴露的上部硅侧壁。进行退火将砷从ASG外扩散进硅中,产生掩埋极板365。也可以用其它形成掩埋极板的技术。
在晶片表面上形成介质层363,覆盖沟槽的内部。介质层作为分开电容器的板的节点介质。在一个实施例中,介质层包括所淀积且随后被氧化的氮化物。例如在FTP设备中用CVD形成氮化物层。然后,在约900℃的温度生长热氧化物。使用氮化物/氧化物(NO)层改进了节点介质的质量。然后淀积重掺杂n型多晶347,填充沟槽并覆盖衬底的表面。
通常将衬底表面向下平面化到节点介质层,使它与多晶有共面的表面。然后用湿法腐蚀去除衬底表面的节点介质和硬掩模层。湿法腐蚀对氮化物和多晶有选择性,留下凸出于基层氮化物上的多晶凸头。然后用如化学机械抛光(CMP)方法向下抛光多晶,直到基层氮化物层。
参见图3d,进行对氮化物有选择性的RIE,使沟槽中的多晶凹下。多晶凹下到要形成的轴环处的底部。随后,用湿法腐蚀去除节点介质层。湿法腐蚀对硅有选择性。这样,去除节点介质层而不去除多晶。
在衬底和沟槽的表面上形成介质层。在一个实施例中,首先生长热氧化薄层,然后在其上淀积TEOS层,由此形成介质层。例如用RIE腐蚀介质层。RIE从基层氮化物堆叠体和凹口底部去除介质层,暴露掺杂的多晶。介质层残留在硅侧壁,形成轴环368。由于扩散区369的存在,介质层不需厚到将寄生漏电流减小到希望的水平。例如,介质轴环可以为约15-25nm厚。
淀积第二层n型重掺杂多晶348,填充沟槽和衬底的表面。进行CMP,使多晶348与基层氮化物层342有共面的表面。然后,以对氮化物和氧化物有选择性的方式,使多晶凹下。凹下的深度应足够确保在掺杂多晶342上形成掩埋条。然后使氧化物轴环的上部凹下,使掺杂剂可以从掺杂多晶扩散到衬底中。然后,在衬底表面上淀积一层本征多晶,覆盖基层氮化物并填充沟槽。用RIE抛光,并凹下,形成掩埋条349。
参见图3e,限定DRAM单元的有源区。用如RIE各向异性腐蚀单元的无源区,提供STI的浅沟槽。如图所示,浅沟槽与约≤一半沟槽重叠,最好是重叠一半的沟槽。然后用包括如TEOS等SiO2的介质材料填充浅沟槽。可以提供氮化物衬垫以来衬垫浅沟槽,防止氧扩散进硅和多晶侧壁。可以退火介质材料,使其致密。退火也使掺杂剂从掺杂多晶中通过条349外扩散进沟槽中,形成扩散区325。
在晶片表面形成氧化层。称为“栅牺牲层”的氧化层作为随后注入的掩蔽氧化物。然后,形成DRAM单元的n沟道存取晶体管的p阱。为了形成p阱,在氧化层的上面淀积光刻胶层,并合适地构图以暴露p阱区。如图所示,将p型掺杂剂如硼(B)注入到阱区。掺杂剂注入足够深,以防止穿通,并降低薄层电阻。掺杂分布被特定,以实现所需的电特性,如栅阈值电压(VT)。
另外,形成n沟道支持电路的p阱。关于互补金属氧化物硅(CMOS)器件中的互补阱,形成n阱。n阱的形成需要另外的光刻和注入步骤来限定和形成n阱。由于用了p阱,n阱的分布被特定以实现所需的PEFTs的电特性。形成阱后,去除栅牺牲层。
在衬底表面形成存取晶体管的各层。这包括栅氧化层、n掺杂多晶层、作为腐蚀停止层的氮化物层。另外,多晶层可以包括多晶化(polycide)层,即多晶层上有硅化物层。可以用各种金属硅化物,如WSix。然后构图这些层,形成DRAM单元的晶体管460的栅堆叠体465。跨越栅(passing gate)堆叠体470通常形成在沟槽上,并用STI彼此隔离。注入如P或As等n型掺杂剂,形成漏472和源471。在一个实施例中,P注入到源和漏区。选择剂量和能量,以产生实现所需工作特性的掺杂分布,例如使短沟道效应和结漏电最小化。为了改进源漏与栅的扩散和对准,可以使用氮化物间隔层(未示出)。为了将晶体管连接到沟槽,通过条440外扩散掺杂剂形成节点结441。
在晶片表面上形成介质层488,覆盖栅和衬底表面。例如介质层包括BPSG。也可以用其它介质层,如TEOS。如图所示,腐蚀不宽的接触开口482以暴露源461。然后用导电材料如n+掺杂多晶硅填充接触开口,于其中形成接触凸头。在介质层上形成作为位线的金属层,使之通过接触凸头与源接触。
在另一个实施例中,使用非自对准工艺形成增加寄生MOSFET的VT的扩散区,以降低垂直寄生漏电。非自对准工艺例如包括:在形成基层堆叠体之前于衬底表面上形成光刻胶层。用曝光光源和限定沟槽以形成沟槽电容器的掩模来选择地曝光光刻胶。显影后去除部分光刻胶,暴露要形成沟槽的衬底表面。然后用合适的掺杂剂、剂量和能量注入衬底,实现所需的分布。注入后去除光刻胶。进行退火,使掺杂剂扩散延伸成所要求的扩散区。再后,在衬底表面形成基层堆叠体,继续处理,形成沟槽电容器存储单元。
尽管根据各实施例已经具体展示和说明了本发明,但本领域的技术人员知道,在不偏离本发明的范围的情况下,可以有变形和改变。本发明的范围不限于在上述说明中,而由本发明的权利要求和其等同物的整个范围所限定。
Claims (1)
1.一种存储器单元,包括:
晶体管,晶体管包括栅极及第一和第二扩散区;
形成在衬底中的沟槽电容器,其中沟槽电容器包括沟槽上部的介质轴环、衬底中包围沟槽电容器下部的掩埋扩散区、在轴环上面电连接晶体管与电容器的节点扩散区;
第三扩散区,第三扩散区位于邻近轴环的衬底中并且包括掺杂剂,该掺杂剂包括浓度在5×1011到2×1018cm-3之间的硼,该浓度足够增加寄生晶体管的栅阈值电压,由此降低漏电流,寄生晶体管由轴环、掩埋扩散区和节点扩散区形成。
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JPS60152058A (ja) * | 1984-01-20 | 1985-08-10 | Toshiba Corp | 半導体記憶装置 |
JPH0616549B2 (ja) * | 1984-04-17 | 1994-03-02 | 三菱電機株式会社 | 半導体集積回路装置 |
JPS6155957A (ja) * | 1984-08-27 | 1986-03-20 | Toshiba Corp | 半導体記憶装置 |
US4864375A (en) * | 1986-02-05 | 1989-09-05 | Texas Instruments Incorporated | Dram cell and method |
DE3851649T2 (de) * | 1987-03-20 | 1995-05-04 | Nec Corp | Aus einer Vielzahl von Eintransistorzellen bestehende dynamische Speichervorrichtung mit wahlfreiem Zugriff. |
JPS63232459A (ja) * | 1987-03-20 | 1988-09-28 | Nec Corp | Mos型メモリ半導体装置およびその製造方法 |
KR910000246B1 (ko) * | 1988-02-15 | 1991-01-23 | 삼성전자 주식회사 | 반도체 메모리장치 |
US5334547A (en) * | 1988-12-27 | 1994-08-02 | Nec Corporation | Method of manufacturing a semiconductor memory having an increased cell capacitance in a restricted cell area |
US5185284A (en) * | 1989-05-22 | 1993-02-09 | Mitsubishi Denki Kabushiki Kaisha | Method of making a semiconductor memory device |
US5225698A (en) * | 1989-08-12 | 1993-07-06 | Samsung Electronics Co., Inc. | Semi-conductor device with stacked trench capacitor |
US5234856A (en) * | 1992-04-15 | 1993-08-10 | Micron Technology, Inc. | Dynamic random access memory cell having a stacked-trench capacitor that is resistant to alpha particle generated soft errors, and method of manufacturing same |
US5508541A (en) * | 1992-09-22 | 1996-04-16 | Kabushiki Kaisha Toshiba | Random access memory device with trench-type one-transistor memory cell structure |
US5406515A (en) * | 1993-12-01 | 1995-04-11 | International Business Machines Corporation | Method for fabricating low leakage substrate plate trench DRAM cells and devices formed thereby |
US5593912A (en) * | 1994-10-06 | 1997-01-14 | International Business Machines Corporation | SOI trench DRAM cell for 256 MB DRAM and beyond |
US5521422A (en) * | 1994-12-02 | 1996-05-28 | International Business Machines Corporation | Corner protected shallow trench isolation device |
US5543348A (en) * | 1995-03-29 | 1996-08-06 | Kabushiki Kaisha Toshiba | Controlled recrystallization of buried strap in a semiconductor memory device |
US5905279A (en) * | 1996-04-09 | 1999-05-18 | Kabushiki Kaisha Toshiba | Low resistant trench fill for a semiconductor device |
US6008103A (en) * | 1998-02-27 | 1999-12-28 | Siemens Aktiengesellschaft | Method for forming trench capacitors in an integrated circuit |
US5945704A (en) * | 1998-04-06 | 1999-08-31 | Siemens Aktiengesellschaft | Trench capacitor with epi buried layer |
-
1997
- 1997-09-30 US US08/940,237 patent/US5981332A/en not_active Expired - Lifetime
-
1998
- 1998-09-17 TW TW087115486A patent/TW402807B/zh not_active IP Right Cessation
- 1998-09-28 KR KR1019980040206A patent/KR100560647B1/ko not_active IP Right Cessation
- 1998-09-28 CN CNB981197752A patent/CN1158711C/zh not_active Expired - Lifetime
- 1998-09-29 EP EP98307874A patent/EP0905784A3/en not_active Withdrawn
- 1998-09-30 JP JP10277289A patent/JPH11168190A/ja active Pending
- 1998-12-17 US US09/215,011 patent/US6163045A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR19990030194A (ko) | 1999-04-26 |
TW402807B (en) | 2000-08-21 |
KR100560647B1 (ko) | 2006-05-25 |
EP0905784A2 (en) | 1999-03-31 |
US6163045A (en) | 2000-12-19 |
EP0905784A3 (en) | 2003-01-29 |
JPH11168190A (ja) | 1999-06-22 |
US5981332A (en) | 1999-11-09 |
CN1218295A (zh) | 1999-06-02 |
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