CN1152436C - 绝缘体基硅场效应晶体管及其形成工艺和绝缘体基硅网络 - Google Patents
绝缘体基硅场效应晶体管及其形成工艺和绝缘体基硅网络 Download PDFInfo
- Publication number
- CN1152436C CN1152436C CNB991261062A CN99126106A CN1152436C CN 1152436 C CN1152436 C CN 1152436C CN B991261062 A CNB991261062 A CN B991261062A CN 99126106 A CN99126106 A CN 99126106A CN 1152436 C CN1152436 C CN 1152436C
- Authority
- CN
- China
- Prior art keywords
- grid
- transistor
- source
- technology
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 11
- 229910052710 silicon Inorganic materials 0.000 title description 7
- 239000010703 silicon Substances 0.000 title description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 230000008569 process Effects 0.000 claims abstract description 10
- 230000005669 field effect Effects 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 44
- 229910052760 oxygen Inorganic materials 0.000 claims description 44
- 239000001301 oxygen Substances 0.000 claims description 44
- 238000010168 coupling process Methods 0.000 claims description 26
- 238000005859 coupling reaction Methods 0.000 claims description 26
- 230000008878 coupling Effects 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 22
- 238000005516 engineering process Methods 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- QVGXLLKOCUKJST-NJFSPNSNSA-N oxygen-18 atom Chemical compound [18O] QVGXLLKOCUKJST-NJFSPNSNSA-N 0.000 claims description 8
- 230000003068 static effect Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims 2
- 230000001052 transient effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
- H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
提供静电泻放保护的SOI场效应晶体管。该结构有源，漏，体和栅。该栅用厚氧层和金属接触形成。该晶体管可以是p型晶体管或n型晶体管。该晶体管漏可以同栅和体之一相连，也可以同栅和体都相连。当作为保护器件使用时，该漏同信号焊盘相连，源同参考电位相连。
Description
本发明一般涉及绝缘体基硅(SOI)型半导体器件，尤其涉及提供网络静电泻放(ESD)保护的体栅耦合的厚氧结构。
保护电路一般应用于集成电路来使内部部件避免发生ESD。在体半导体材料中，可以制造部件来消耗ESD事件中的过量电荷。用于ESD保护的普通类型部件包括金属氧化物半导体场效应晶体管(MOSFET)和厚场氧(TFO)穿通器件。在每个这样的器件中，该器件的击穿电压由其内部的p-n结的击穿电压决定。该p-n结面积通常足够大，使其能够消耗ESD事件中的过量电荷。
随着对半导体器件更高速度工作要求的增长，在SOI衬底上形成的集成电路正引起注意。用于体半导体器件的ESD保护器件本身不能容易地用于SOI器件。因为扩散区下立即是埋氧层，该p-n结的大部分面积损失了。导致只有小得多的面积来消耗ESD事件中的过量电荷。因为能量不能有效消耗，器件可能过热并发生永久损伤。
已经制造出能够提供ESD保护的不同SOI结构。1998年6月2日授予Okumura的第5760444号美国专利上公开了这样的一个结构。Okumura描述了在制造过程中与MOSFET集成在一起的单独的ESD二极管器件。该二极管通过漏区与该MOSFET电相连。当在该MOSFET的漏区施加过高电位时，该二极管被正向偏置，为在该二极管内流动的电荷提供通路。结果，该SOI半导体器件对静电击穿具有抵抗力。该器件的缺点是在制造时需要额外的工艺步骤；同时，当其仍提供ESD保护，在怎样与其它器件相连方面，该器件缺乏灵活性。
1998年6月30日授予Gilbert等人的第5773326号美国专利上公开了另一个结构。Gilbert等人描述了这样的SOI结构，它被分成ESD保护部分和电路部分。ESD保护部分需要厚SOI层来工作。该厚SOI层作用是将ESD电流和热量分散在大面积内，从而改善该SOI结构的抗ESD事件的能力。
1998年3月10日授予Smith的第5726844号美国专利上公开了另一个结构。Smith描述了用于SOI器件的保护电路，在该保护电路中用了体连接的MOSFET和齐纳二极管。因为该MOSFET有薄栅氧，所以需要几个齐纳二极管来保护过压和欠压情况。
1997年11月4日授予Smith等人的第5683918号美国专利上公开了另一个结构。Smith等人描述了用于保护SOI器件网络的体连接的MOSFET。该ESD保护器件有易损坏的薄栅氧，需要大的硅版图面积使其有效。
在第5811857号美国专利中发现了保护SOI电路免于ESD的另一种方法。1998年9月22日该`857号专利授予Assaderaghi等人，在此作为参考。Assaderaghi等人公开了SOI电路，其中包括提供ESD保护的由SOI MOSFET形成的体栅耦合(BCG)的二极管。NMOSFET和PMOSFET都能用来产生该二极管的正向偏置工作。参见图1a-1d(同Assaderaghi等人的图2，3，5和6相对应)，公开了该BCG二极管的两种配置。图1a示出了NMOSFET100的电路图。如图所示，NMOSFET100包括源108，漏106，体104和栅102。漏，体和栅连接在节点A。当节点A的电压高于节点B时，NMOSFET100开启，从而提供ESD保护。如图1b所示，NMOSFET100可以等效成二极管图型。
类似地，如图1c和1d所示，PMOSFET110包括源108，漏106，体104和栅102。漏，体和栅连接在节点A。当节点B的电压高于节点A时，PMOSFET110开启，从而提供ESD保护。如图1d所示，PMOSFET110可以等效成二极管图型。
然而，应该理解，由Assaderaghi等人公开的NMOSFET和PMOSFET都是用薄栅氧形成的，因此，都易受高压ESD事件的损坏。而且，MOSFET需要体接触栅和漏。该要求限制了这些MOSFET的灵活性。
仍然存在形成SOI器件保护电路的需要，它允许该器件被保护以远离可能到达集成电路输入/输出焊盘的ESD电位。如果有能提供合适的ESD保护，但只需要小面积散热的半导体结构，那将是有利的。如果该结构能够容易地用与现存半导体工艺集成的工艺制造，那同样是有利的。
为满足这个和其它需求，并从目的来看，本发明涉及提供ESD保护的SOI场效应晶体管结构。该结构有源，漏，体和栅。该栅由厚氧层和金属接触形成。该栅在引线后端(BEOL)工艺中形成。该晶体管可以是n型晶体管或p型晶体管。该晶体管的漏区可以同栅或体相连，或同栅和体都相连。当作为保护器件使用时，该漏同信号焊盘相连，源同参考电位相连。
形成该厚氧场效应晶体管的工艺包括以下步骤。首先，通过浅沟槽隔离形成具有半导体岛的SOI结构；该半导体岛为第一导电类型。接着，用具有第二导电类型的掺杂物形成单独的源区和独立的漏区；第一导电类型的剩余区域形成体区。在该岛上淀积绝缘层。刻蚀该绝缘层形成体区上的厚氧栅区。最后，形成金属引线来接触源，漏，体和栅区。
应当理解本发明的前述概要描述和接下来的具体描述都是示例性的，不是对本发明的限制。
结合附图阅读以下的具体描述，会更好地理解本发明。这些附图中包括以下图形：
图1a和1b是根据`857号专利的图2和3中配置成体耦合和栅耦合二极管的n沟FET(NFET)的电路图；
图1c和1d是根据`857号专利的图5和6中配置成体耦合和栅耦合二极管的p沟FET(PFET)的电路图；
图2a-2d是根据本发明的优选实施例的SOI NMOSFET结构在不同制作阶段中的横截面图，；
图2e是根据本发明优选实施例的SOI PMOSFET结构的横截面图；
图2f是显示体，厚氧和栅区之间关系的SOI MOSFET结构的横截面图；
图3a和3b是图2d中的SOI NMOSFET的电路图；
图4a和4b是图2e中的SOI PMOSFET的电路图；
图5a-5c是根据本发明优选实施例的显示不同耦合方式的图2d中的SOI NMOSFET的电路图；
图6是根据本发明优选实施例的显示体耦合和栅耦合方式的图2e中的SOI PMOSFET的电路图；以及
图7是用图5c的NMOSFET和图6的PMOSFET构成的ESD保护器件的示例性电路图。
图8和9是显示厚氧器件同薄氧器件不同组合的ESD保护器件的示例性电路。
根据本发明优选实施例，图2a-2d显示了在不同制作阶段的NMOSFET器件10。如图2a所示，NMOSFET器件10包括半导体衬底层12，绝缘层14和半导体层18。半导体衬底层12是轻掺杂p型硅片。在本实施例中，绝缘层14是二氧化硅层。半导体衬底层12，绝缘层14和半导体层18的组合被认为是SOI结构。该SOI结构可以用任何制造SOI结构的常规工艺形成。例如，可以用常规注入氧隔离(SIMOX)工艺在半导体衬底层12内注入高浓度氧来形成该SOI结构。此外，可以用常规键合和深刻蚀工艺形成该SOI结构。
如图2a所示，形成场隔离区16a和16b。尽管举例的是浅沟槽隔离(STI)区，也可以用其它场隔离工艺。通过用常规方法形成STI区，半导体层18被分割成几个岛(其一显示在图2a中)。薄氧层(未显示)，例如二氧化硅，可以在半导体层18的岛上生长。该薄氧层可以用本领域熟练人员知道的光刻胶和掩模工艺形成。
接着，在半导体层18上放置掩埋电阻(BR)掩模(未显示)，以便随后通过该掩模的未覆盖区域用离子注入形成图2b的源区20和漏区22。砷(As)离子注入是在70Kev和大约5×1015原子/cm2的剂量下进行的。结果，形成重掺杂n+型区域20和22。n+型区域20和22的形成是非自对准的。因为BR掩模防止在体区24内离子注入，体区24仍为轻掺杂p型区。因此，体区24形成介于NMOSFET10源区20和漏区22之间的体。
接下来的制造步骤如图2c所示。绝缘层26，例如二氧化硅，被淀积在场隔离区16a和16b，源区20，漏区22和体区24上。绝缘层26可以在引线后端(BEOL)制造过程中形成为层间介质。绝缘层26厚度大约在2000至3000埃之间，优选厚度约为2500埃。
如图2c所示，绝缘层26淀积后，通过向下刻蚀到源区20和漏区22形成接触孔或通孔19。最后，如图2d所示，淀积金属引线以形成源引线28，漏引线32和栅引线30。通孔19和金属引线的形成是在BEOL制造过程中用常规方法完成的。尽管没有作为一个工艺步骤显示，衬底引线25形成为具有同体区24的金属接触的常规T型结构。
类似地，如图2e所示，在SOI结构上形成厚氧PMOSFET40，该结构具有半导体衬底层12；绝缘层14；场隔离区16a和16b；重掺杂p+型源区20和漏区22；轻掺杂n型体区24；和体区24上形成绝缘层26的厚氧层。最后，淀积金属引线形成源引线28，漏引线32，栅引线30和体引线25。
因此，描述了形成厚氧SOI MOSFET的工艺，其中栅由金属薄膜形成，而绝缘体是BEOL层间介质(ILD)。如图2f所示，发明人也发现通过改变栅宽“W”，可以改进熔融硅和短路源，漏及体区的失效机制。W做的越宽，失效发生的概率越小。更进一步，通过在体区24上以预定长度“L”重叠形成绝缘层26，如所示，可以改善ESD保护。
在淀积该厚氧绝缘体前，可以在SOI结构上淀积，掩模和刻蚀一多晶硅层来确定栅区。淀积该厚氧绝缘体后，可以执行金属化工艺来确定到不同区域的接触。
图3a中显示了图2d的厚氧NMOSFET的电路图。如图，厚氧NMOSFET10包括源引线28，漏引线32，体引线25以及栅引线30。源引线28同端子B相连；漏引线32同端子A相连；体引线25连接于VB；栅引线30连接于Vg。如图3b所示，NMOSFET10可以用二极管符号来表示。
类似地，图4a中显示了图2e的厚氧PMOSFET的电路图。如图，厚氧PMOSFET40包括源引线28，漏引线32，体引线25以及栅引线30。如图4b所示，PMOSFET40可以用二极管符号来表示。
现在将说明在NMOSFET10开启并提供ESD保护时的动作。当NMOSFET10的体电压超过NMOSFET10的源电压时，产生第一开启状态。当产生该状态时，正向偏置二极管属性允许电流从体端向源端流动。当NMOSFET10的栅电压超过NMOSFET10的阈值电压时，产生第二开启状态。当产生该状态时，开启的晶体管属性允许电流从漏端向源端流动。
在类似的方式下，对于图4a和4b所示的PMOSFET40，当在A端施加的负脉冲比体电压低过二极管正向偏置电压时，正向偏置二极管属性允许电流从体端向PMOSFET40的漏端流动。当PMOSFET40的栅电压低于PMOSFET40的阈值电压时，产生第二开启状态。当产生该状态时，开启的晶体管属性允许电流从源端向漏端流动。
图5a-5c是根据本发明实施例的在不同ESD应用中所使用的上述厚氧NMOSFET10。如图5a所示，NMOSFET10中体引线25同漏引线32在A端相连。A端连向焊盘34，源引线28在B端连向VSS(通常是地电位)；栅引线30未连。在这种ESD应用中，厚氧NMOSFET10体与漏端耦合，当焊盘34的电压上升超过存在于体和源端之间的二极管正向偏置电压时，提供ESD保护。
图5b示出了在栅耦合方式下的厚氧NMOSFET10。如图，NMOSFET10中栅引线30同漏引线32在A端相连。A端连向焊盘34，源引线28在B端连向VSS；体引线25未连。在这种ESD应用中，厚氧NMOSFET10栅与漏端耦合，当焊盘34的电压上升超过NMOSFET10的阈值电压时提供ESD保护。当焊盘34的电压超过阈值电压时，电流从该焊盘流向电源VSS。
图5c示出了在体和栅都耦合的方式下的厚氧NMOSFET10。如图，NMOSFET10中栅引线30同体引线25连向A端。A端连向焊盘34，源引线28在B端连向VSS。在这种ESD应用中，厚氧NMOSFET10在前述的第一开启状态和第二开启状态时提供ESD保护。
因此，体和栅都耦合方式下的厚氧NMOSFET10如下工作。当在焊盘34上施加正电压时，电流通过由体和源形成的p-n二极管泻放。并行地，当体电压上升，该NMOSFET10的阈值电压下降，产生动态阈值。当阈值电压下降，NMOSFET的栅耦合开启与二极管并联的NMOSFET。这是体栅耦合器件独特的方面，它具有二极管属性和晶体管属性的并行工作。NMOSFET10利用体耦合来减少阈值电压的绝对值，同时利用栅耦合在阈值电压急速返回前开启晶体管元件。
在概念上可以将NMOSFET10的体栅耦合看成大电流增益的双极晶体管。漏电流可以看成收集极电流，体(栅)电流看成基极电流，而源电流可以看成发射极电流。尽管为了分析方便，该器件可以看成双极器件，但实际上它是NMOSFET，因为导电电流通过表面沟道并由栅控制。该“双极”器件的“显式”增益大，因为该NMOSFET的阈值电压受施加在硅膜的偏置调制。这表现出小偏置下的大双极增益。
该NMOSFET的阈值电压可以受沟道尺寸控制。小长度沟道有小阈值电压。通过改变调整阈值的注入(用来控制阈值电压的常规注入)，阈值电压可以轻易地改变。
尽管以上参照厚氧NMOSFET器件描述，类似的描述也适用于PMOSFET器件。因此，PMOSFET器件可以配置成体耦合方式，栅耦合方式，或体栅耦合方式。图6示出了在体和栅耦合方式的PMOSFET40。如图，体引线25，栅引线30，以及漏引线32在A端相连。源引线28在B端连向VSS而A端连向焊盘34。
当在焊盘34上施加负脉冲时，电流通过由PMOSFET结构的体和源形成的n-p二极管泻放。并行地，当体电压下降，该PMOSFET40的阈值电压的幅度下降，同样产生动态阈值。当阈值电压下降，PMOSFET的栅耦合开启与二极管并联的晶体管。即，PMOSFET40利用体耦合来减少阈值电压的绝对值，同时利用栅耦合在PFET急速返回前开启该晶体管。
图7示出了第一级ESD保护器件50中一起工作的NMOSFET10和PMOSFET40。NMOSFET10在B端与VDD耦合，在A端与焊盘34耦合。PMOSFET40在B端与VSS耦合，在A端与焊盘34耦合。VDD是预定的高电压电源，例如3.4伏，VSS是预定的低电压电源，例如地电压。当在焊盘34上施加输入信号时，NMOSFET10通过吸纳更多电流到B端将输入信号变为VDD(加阈值电压)。当输入信号低于VSS时，PMOSFET40将输入信号箝位于VSS(减阈值电压)。当输入信号比VSS低一个阈值电压时，PMOSFET40从VSS电源驱动更多电流到该器件。在这种方式下，当输入信号分别上升高于预定高电压电源或下降低于预定低电压电源时提供ESD保护。
如图7所示，当牵涉到混合电压接口时，可以在第一级ESD保护器件50上增加其它级，例如第二级ESD保护器件60。第一级连接在信号焊盘和其后级之间，并避免高于VDD和低于VSS的ESD事件。第二级60连接在第一级50和也许是另一级(未显示)之间，并避免高于VEE(例如4.1伏)和低于VSS的ESD事件。因此，信号输出62被箝位在4.1伏(例如)和0伏地电压(例如)之间。
参见附图，应该理解，尽管显示的是特定的例子和元件，其它合适元件的组合也可以使用。例如，如图7所示的第一级ESD保护器件50，可以包括两个NMOSFET，两个PMOSFET，或一个NMOSFET和一个PMOSFET。此外，可以使用多级不同元件的组合。在`857号专利中Assaderaghi等人公开了ESD保护网络的不同组合；那些组合在此作为参考。
图8显示了另一个元件组合。如图，第一级保护器件50包括厚氧NMOSFET10和厚氧PMOSFET40。第二级保护器件60包括薄氧NMOSFET66和薄氧PMOSFET68。第二级通过串联电阻64与第一级耦合。
图9显示了另一提供ESD保护的具有厚氧晶体管70的实施例。该厚氧晶体管70与第一级相连，第一级包括薄氧NMOSFET66和薄氧PMOSFET68。应当理解厚氧晶体管70的体和栅连向VSS(或参考地电位)并且不同晶体管70的源或漏相连。因此在该实施例中，该晶体管不是体栅耦合的。
尽管此处参照特定实施例举例和描述，然而并不意味着本发明应局限于所示的细节。在本权利要求书等价的范围和领域内，在不离开本发明的精神下，可以对细节做不同的修改。
Claims (19)
1.用于静电泻放保护的SOI场效应晶体管，包括：
提供第一端的源，
提供第二端的漏，
提供第三端的体，所述源、漏和体位于SOI结构中，以及
提供第四端的栅，具有直接位于所述SOI结构顶部上的厚氧层和直接位于所述厚氧层顶部上的金属接触，
其中该厚氧层是通过引线后端工艺形成的层间介质。
2.权利要求1的晶体管，其中该晶体管是p型晶体管和n型晶体管之一。
3.权利要求2的晶体管，其中漏同栅和体之一相连。
4.权利要求3的晶体管，其中漏同栅和体相连。
5.权利要求4的晶体管，其中漏连接至信号焊盘，源连向参考电位。
6.从信号焊盘接收信号的SOI网络，包括：
具有SOI结构的至少一个场效应晶体管，所述SOI结构具有源，漏，体和厚氧栅，所述漏，体和栅连接在一起，所述厚氧层是通过引线后端工艺形成的层间介质，
同漏耦合的第一端，
同源耦合的第二端，以及
与第一端和第二端之一耦合的信号焊盘，
其中该晶体管响应接收到的信号，通过只产生预定电压范围内的电压从接收到的信号提供静电泻放保护。
7.形成厚氧场效应晶体管的工艺，包括以下步骤：
a)通过浅沟槽隔离提供具有半导体岛的绝缘体基硅结构，其中半导体岛为第一导电类型；
b)用具有第二导电类型的掺杂物在半导体岛上形成独立的源区和独立的漏区，其中剩下的第一导电类型区域是体区；
c)在源区、漏区和体区上形成连续的绝缘层；
d)刻蚀该连续的绝缘层来形成体区上的厚氧栅区；以及
e)形成分别接触源，漏，体和栅区的金属引线。
8.权利要求7的工艺，其中步骤d)包括远离栅区覆盖绝缘层用于改善静电泻放保护。
9.权利要求8的工艺，其中步骤e)包括加宽接触栅区的金属引线用于改善静电泻放保护。
10.权利要求9的工艺，其中用厚度范围从2000到3000埃之间的二氧化硅形成该绝缘层。
11.权利要求10的工艺，其中该绝缘层在引线后端制作工艺中形成。
12.权利要求11的工艺，其中步骤e)包括将栅，体和漏区连接至第一端，源区连接至第二端。
13.权利要求12的工艺，其中步骤e)包括形成与第一端和第二端之一电相连的焊盘。
14.权利要求13的工艺，其中步骤e)包括形成与第一端和第二端的另一个电相连的参考电压端。
15.权利要求14的工艺，其中步骤b)包括离子注入n+杂质作为第二导电类型掺杂物。
16.权利要求14的工艺，其中步骤b)包括离子注入p+杂质作为第二导电类型掺杂物。
17.从信号焊盘接收信号的SOI网络，包括：
至少一个厚氧晶体管，响应所述信号用于静电泻放保护，所述厚氧晶体管具有：SOI结构；位于SOI结构中的源、漏和体；和厚氧层，所述厚氧层是通过引线后端工艺形成的层间介质。
18.权利要求17的网络，其中所述厚氧晶体管具有源，漏，体和栅，
同漏耦合的第一端，
同栅和体耦合的第二端，以及
和源耦合的信号焊盘。
19.权利要求17的网络，其中所述厚氧晶体管具有源，漏，体和栅，以及
其中所述体和栅同所述漏和源之一耦合。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/227,695 | 1999-01-08 | ||
| US09/227,695 US6323522B1 (en) | 1999-01-08 | 1999-01-08 | Silicon on insulator thick oxide structure and process of manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1260597A CN1260597A (zh) | 2000-07-19 |
| CN1152436C true CN1152436C (zh) | 2004-06-02 |
Family
ID=22854114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991261062A Expired - Lifetime CN1152436C (zh) | 1999-01-08 | 1999-12-10 | 绝缘体基硅场效应晶体管及其形成工艺和绝缘体基硅网络 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US6323522B1 (zh) |
| JP (1) | JP3537035B2 (zh) |
| KR (1) | KR100351648B1 (zh) |
| CN (1) | CN1152436C (zh) |
| SG (1) | SG83758A1 (zh) |
| TW (1) | TW457585B (zh) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001244469A (ja) * | 2000-03-02 | 2001-09-07 | Oki Electric Ind Co Ltd | 半導体装置およびその製造方法 |
| JP2002305254A (ja) * | 2001-04-05 | 2002-10-18 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| US6621288B1 (en) * | 2001-05-23 | 2003-09-16 | Advanced Micro Devices, Inc. | Timing margin alteration via the insulator of a SOI die |
| US6414335B1 (en) * | 2001-05-23 | 2002-07-02 | Advanced Micro Devices, Inc. | Selective state change analysis of a SOI die |
| US7166876B2 (en) * | 2004-04-28 | 2007-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOSFET with electrostatic discharge protection structure and method of fabrication |
| US7084462B1 (en) * | 2005-04-15 | 2006-08-01 | International Business Machines Corporation | Parallel field effect transistor structure having a body contact |
| JP5586819B2 (ja) * | 2006-04-06 | 2014-09-10 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
| US20080246062A1 (en) * | 2007-03-26 | 2008-10-09 | Elizabeth Brauer | Semiconductor based controllable high resistance device |
| US8208233B2 (en) * | 2008-03-18 | 2012-06-26 | Mediatek Inc. | ESD protection circuit and method thereof |
| US8669146B2 (en) | 2011-01-13 | 2014-03-11 | International Business Machines Corporation | Semiconductor structures with thinned junctions and methods of manufacture |
| US8710908B2 (en) * | 2011-01-28 | 2014-04-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Charge pump and method of biasing deep N-well in charge pump |
| US8749223B2 (en) * | 2011-06-22 | 2014-06-10 | Nxp B.V. | Galvanic isolation device and method |
| CN117176098A (zh) * | 2023-11-01 | 2023-12-05 | 上海安其威微电子科技有限公司 | 限幅电路和无线收发装置 |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1518984A (en) | 1974-07-16 | 1978-07-26 | Nippon Electric Co | Integrated circuit |
| JPS6048106B2 (ja) * | 1979-12-24 | 1985-10-25 | 富士通株式会社 | 半導体集積回路 |
| US4408245A (en) | 1981-12-28 | 1983-10-04 | Rca Corporation | Protection and anti-floating network for insulated-gate field-effect circuitry |
| US4626882A (en) | 1984-07-18 | 1986-12-02 | International Business Machines Corporation | Twin diode overvoltage protection structure |
| JP2812388B2 (ja) | 1988-01-18 | 1998-10-22 | 富士通株式会社 | Ｓｏｉ半導体装置の製造方法 |
| US4989057A (en) | 1988-05-26 | 1991-01-29 | Texas Instruments Incorporated | ESD protection for SOI circuits |
| US4946799A (en) | 1988-07-08 | 1990-08-07 | Texas Instruments, Incorporated | Process for making high performance silicon-on-insulator transistor with body node to source node connection |
| US5144390A (en) | 1988-09-02 | 1992-09-01 | Texas Instruments Incorporated | Silicon-on insulator transistor with internal body node to source node connection |
| US5023692A (en) | 1989-12-07 | 1991-06-11 | Harris Semiconductor Patents, Inc. | Power MOSFET transistor circuit |
| US5159518A (en) | 1990-01-17 | 1992-10-27 | Vlsi Technology, Inc. | Input protection circuit for CMOS devices |
| US5436183A (en) * | 1990-04-17 | 1995-07-25 | National Semiconductor Corporation | Electrostatic discharge protection transistor element fabrication process |
| JPH0473970A (ja) | 1990-07-16 | 1992-03-09 | Fuji Electric Co Ltd | Ｍｏｓ型半導体装置 |
| GB9115699D0 (en) | 1991-07-19 | 1991-09-04 | Philips Electronic Associated | An overvoltage protected semiconductor switch |
| JP3405364B2 (ja) * | 1993-03-08 | 2003-05-12 | セイコーインスツルメンツ株式会社 | 半導体装置 |
| KR0169157B1 (ko) | 1993-11-29 | 1999-02-01 | 기다오까 다까시 | 반도체 회로 및 mos-dram |
| US5382818A (en) | 1993-12-08 | 1995-01-17 | Philips Electronics North America Corporation | Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode |
| US5489792A (en) * | 1994-04-07 | 1996-02-06 | Regents Of The University Of California | Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility |
| JP2770784B2 (ja) | 1995-05-31 | 1998-07-02 | 日本電気株式会社 | シリコン・オン・インシュレータ半導体装置 |
| US5708288A (en) | 1995-11-02 | 1998-01-13 | Motorola, Inc. | Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method |
| US5597747A (en) * | 1995-12-15 | 1997-01-28 | Industrial Technology Research Institute | Method of making inverted thin film transistor using backsick exposure and negative photoresist |
| US5683918A (en) | 1996-04-01 | 1997-11-04 | Motorola, Inc. | Method of making semiconductor-on-insulator device with closed-gate electrode |
| US5726844A (en) | 1996-04-01 | 1998-03-10 | Motorola, Inc. | Protection circuit and a circuit for a semiconductor-on-insulator device |
| JPH09282552A (ja) * | 1996-04-17 | 1997-10-31 | Sanyo Electric Co Ltd | コーヒー飲料の製造装置 |
| US5773326A (en) | 1996-09-19 | 1998-06-30 | Motorola, Inc. | Method of making an SOI integrated circuit with ESD protection |
| US5811857A (en) | 1996-10-22 | 1998-09-22 | International Business Machines Corporation | Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications |
| US5952695A (en) * | 1997-03-05 | 1999-09-14 | International Business Machines Corporation | Silicon-on-insulator and CMOS-on-SOI double film structures |
-
1999
- 1999-01-08 US US09/227,695 patent/US6323522B1/en not_active Expired - Lifetime
- 1999-12-09 SG SG9906260A patent/SG83758A1/en unknown
- 1999-12-10 CN CNB991261062A patent/CN1152436C/zh not_active Expired - Lifetime
- 1999-12-23 TW TW088122779A patent/TW457585B/zh not_active IP Right Cessation
- 1999-12-28 JP JP37312699A patent/JP3537035B2/ja not_active Expired - Fee Related
-
2000
- 2000-01-04 KR KR1020000000188A patent/KR100351648B1/ko not_active IP Right Cessation
-
2001
- 2001-07-12 US US09/903,820 patent/US6426244B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| TW457585B (en) | 2001-10-01 |
| KR20000053384A (ko) | 2000-08-25 |
| JP2000208779A (ja) | 2000-07-28 |
| US6323522B1 (en) | 2001-11-27 |
| SG83758A1 (en) | 2001-10-16 |
| JP3537035B2 (ja) | 2004-06-14 |
| KR100351648B1 (ko) | 2002-09-11 |
| US20010041393A1 (en) | 2001-11-15 |
| CN1260597A (zh) | 2000-07-19 |
| US6426244B2 (en) | 2002-07-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101506974B (zh) | 利用沟槽隔离形成的无闭锁垂直瞬态电压抑制二极管阵列结构 | |
| US6445044B2 (en) | Apparatus improving latchup immunity in a dual-polysilicon gate | |
| US8455315B2 (en) | Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch | |
| US20050148124A1 (en) | ESD protection for semiconductor products | |
| CN1152436C (zh) | 绝缘体基硅场效应晶体管及其形成工艺和绝缘体基硅网络 | |
| JP2006523965A (ja) | シリコンオンインシュレータ技術を対象とする静電放電（ｅｓｄ）保護用低電圧シリコン制御整流器（ｓｃｒ） | |
| US6177346B1 (en) | Integrated circuitry and method of forming a field effect transistor | |
| US20070241421A1 (en) | Semiconductor structure and method of manufacture | |
| US8107203B2 (en) | Electrostatic discharge protection device | |
| CN104851919A (zh) | 双向穿通半导体器件及其制造方法 | |
| US7309638B2 (en) | Method of manufacturing a semiconductor component | |
| US7462885B2 (en) | ESD structure for high voltage ESD protection | |
| KR20090098237A (ko) | 높은 홀딩 전압을 갖는 스택형 실리콘 제어 정류기를구비한 정전기 방전 보호소자 | |
| US9627210B2 (en) | Method of fabricating electrostatic discharge protection structure | |
| US7955923B1 (en) | I/O ESD protection device for high performance circuits | |
| US8294218B2 (en) | Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection | |
| CN116387363B (zh) | 一种ldmos工艺tvs器件及其制造方法 | |
| JP3120440B2 (ja) | 半導体双方向スイッチ | |
| JP2011222971A (ja) | 半導体装置およびその製造方法 | |
| KR0145119B1 (ko) | 다링톤 접속 반도체소자 및 그의 제조방법 | |
| JP2004071677A (ja) | 半導体装置およびその製造方法 | |
| JPS6235666A (ja) | Ｍｏｓトランジスタ | |
| KR100218263B1 (ko) | 반도체 장치 및 그 제조 방법 | |
| JPH06252355A (ja) | 半導体装置 | |
| JPH07147382A (ja) | 半導体装置およびその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20171117 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171117 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20171123 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES INC. Address before: American New York Patentee before: Core USA second LLC Effective date of registration: 20171123 Address after: American New York Patentee after: Core USA second LLC Address before: American New York Patentee before: International Business Machines Corp. |
|
| TR01 | Transfer of patent right | ||
| CX01 | Expiry of patent term |
Granted publication date: 20040602 |
|
| CX01 | Expiry of patent term |