CN1148261A - 制造半导体器件的方法 - Google Patents
制造半导体器件的方法 Download PDFInfo
- Publication number
- CN1148261A CN1148261A CN96106922A CN96106922A CN1148261A CN 1148261 A CN1148261 A CN 1148261A CN 96106922 A CN96106922 A CN 96106922A CN 96106922 A CN96106922 A CN 96106922A CN 1148261 A CN1148261 A CN 1148261A
- Authority
- CN
- China
- Prior art keywords
- tungsten silicide
- silicide film
- film
- semiconductor device
- going
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 39
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000001301 oxygen Substances 0.000 claims abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 235000012431 wafers Nutrition 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 7
- 238000002425 crystallisation Methods 0.000 claims description 6
- 230000008025 crystallization Effects 0.000 claims description 6
- 229910052731 fluorine Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 239000007792 gaseous phase Substances 0.000 claims description 2
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims 1
- 238000010276 construction Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 125000001153 fluoro group Chemical group F* 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000007850 degeneration Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明揭示的制造半导体器件的方法尤其适用于高集成度的半导体器件。在该方法中,在形成于半导体衬底栅氧化膜上的多硅晶膜上形成有非晶构造的下硅化钨膜。在下硅化钨膜上,形成具有多个小晶粒的上硅化钨膜,在各小晶粒之间限定有间隙。然后,在氧环境下通过热处理在结晶的晶粒上形成氧化膜。
Description
本发明涉及一种制造半导体器件的方法,特别涉及利用具有不同构造的双层硅化钨膜形成栅极来制造半导体器件的方法,该方法尤其适用于制造高集成度的半导体器件。
通常,当仅用多硅晶在半导体器件上形成栅极时,则半导体器件的集成度越高,字线(work line)的电阻将越大,因而,半导体器件的工作速度越低。
如上所述,已经发现一种能防止上述电阻增加,工作速度降低的制造半导体器件的方法。在这种方法中,用诸如钨等具有低电阻的金属硅化物层叠在栅极上。
下文将更详细地描述上述传统的制造方法。
图1是半导体器件的剖面图,它示出制造具有用硅化钨膜形成栅极的半导体器件的传统方法。
在该传统的方法中,首先用LOCOS方法在硅衬底1上形成元件隔离氧化膜(未示出)。
然后,如图1所示,在硅衬底1上形成栅氧化膜2,并沉积多硅晶膜3于栅氧化膜2上。此后,在多硅晶膜3上沉积具有低阻抗的硅化钨膜4。
下面讨论制造半导体器件传统方法中存在的上述问题。
首先,因为栅电阻必须较低以实现半导体器件的高集成度和高速工作,故在传统的制造半导体器件的方法中,与多硅晶膜相比,必须相对较厚。
而且,在传统的制造半导体器件的方法中,当多硅晶膜为了改善其形貌布局而必须降低厚度时,硅化钨膜的厚度必须增加。
因此,当在高温下进行后续工艺时,包含在硅化钨内的氟原子将扩散到栅氧化膜内,以至于加快了栅氧化膜的退化,从而使半导体器件的得益率和可靠性降低。
本发明已提出克服现有技术的上述问题,因此,本发明的目的在于提供一种制造半导体器件的方法,用以降低器件的栅极电阻,改善其形貌布局。另外,该方法应使器件的得益率和可靠性有所改进,从而适用于器件的高集成度。
为了实现上述目的,本发明提供一种制造半导体器的方法,该方法包含下列步骤:准备半导体衬底;在半导体衬底上形成栅氧化膜,在栅氧化膜上形成多硅晶膜;在多硅晶膜上形成具有非晶构造的下硅化钨膜,并形成具有非晶构造和多个小晶粒的上硅化钨膜,在小晶粒之间限定有间隙,上硅化钨膜顺序形成在下硅化钨膜上,下硅化钨膜和上硅化钨膜均用低压化学沉淀方法形成;借助上、下硅化钨的热处理使下硅化钨膜和上硅化钨膜的非晶构造同时结晶,并伴随有氧化膜形成在上硅化钨膜中多个结晶的小晶粒表面。
从下面参照附图对实施例的描述,本发明的其它目的和方面将变得明了,其中:
图1是半导体器件的剖面图,它示出制造具有用硅化钨膜形成栅极的半导体器件的传统方法;
图2A至2C是半导体器件的剖面图,它们示出用根据本发明的制造半导体器件的方法形成栅极的工艺。
下文将参照附图详细描述本发明。
图2A至2C示出用根据本发明制造半导体器件的方法形成栅极的工艺。
在根据本发明制造半导体器件的方法中,首先,在硅衬底11上用LOCOS方法形成元件隔离氧化膜(未示出)。
此后,如图2A所示,在硅衬底11上形成栅氧化膜12,并在栅氧化膜12上沉积多硅晶13。
然后,在约440℃和480℃之间的温度下用低压化学气相沉淀(LPVCD)法把WF6和SiH4气体沉积在多硅晶膜13上,以便形成总厚度约在1300到1500之间的膜。除这两层膜之外,在多硅晶膜13上形成厚度约在700至800之间的非晶构造的下硅化钨膜14。另外,在下硅化钨膜14上形成厚度约在500至800之间的非晶构造的上硅化钨膜15,后者如图2B所示,具有多个晶粒。
然后,如图2C所示,把下硅化钨膜14和上硅化钨膜15在氧环境下用约700℃至900℃的温度进行热处理,以便进行结晶。
在这种情况下,氧在上述结晶过程中,被注入到上硅化钨膜15内小晶粒的非晶硅层之间,同时薄薄地氧化结晶的晶粒系统的表面,从而在表面上形成薄的氧化膜16。
氧化膜16捕获上硅化钨膜15内的氟原子,从而防止后续工艺过程中氟原子从上硅化钨膜15扩散到栅氧化膜12上。
另一方面,观察到的栅极的电阻值Rs相对于多硅晶膜和成双形成硅化钨膜的厚度如下。
首先,当多硅晶膜13的厚度约为700,上和下硅化钨膜整体厚度约为1300时,测得电阻Rs约在9Ω/□。
而,当多硅晶膜13的厚度约为1000,上和下硅化钨膜整体厚度约为1000时,测得电阻Rs约在13Ω/□。
另外,当多硅晶膜13的厚度约为700,上和下硅化钨膜整体厚度约为1300时,测得电阻Rs约在11Ω/□。
同时,在使用双硅化物膜的半导体器件中,根据时间测得栅氧化膜的击穿几乎与现有技术的情况相同。
也即,在用根据本发明方法制造的半导体器件中,栅电阻被显著地降低,而与现有技术的半导体器件相比,栅氧化膜的击穿特性并没有降低。
如上所述,根据本发明制造半导体器的方法具有如下的有利效果。
在根据本发明的制造半导体器件的方法中,当把双层硅化钨膜在氧环境下进行热处理时,周围的氟注入到氧化膜中,并被氧化膜捕获,从而在上硅化钨膜内小晶粒的表面上形成薄的氧化膜,所以使在后继的高温工艺过程期间,包含于上硅化钨膜内的氟原子向下面栅氧化膜的扩散得以防止。
因此,根据用本发明制造半导体器件的方法,不仅降低了栅极的电阻,而且改善了形貌布局,因为硅化钨膜甚至在它们的厚度增加时也使栅极氧化膜的退化得以防止。
所以,由于本发明能降低栅极的电阻,改善布局,而使本发明的制造半导体器件的方法适用于高集成度的半导体器件。
虽然为了图示说明揭示了本发明的较佳实施例,但该技术领域的熟练人员将理解,可以进行各种变化、补充和替换,而不偏离如所附权利要求书中揭示的本发明的范围和精神。
Claims (8)
1.一种制造半导体器件的方法,其特征在于,该方法包含下列步骤:
准备半导体衬底;
在所述半导体衬底上形成栅氧化膜,并在所述栅氧化膜上形成多硅晶膜;
在所述多硅晶膜上形成非晶构造的下硅化钨膜,并形成非晶构造的具有多个小晶粒的上硅化钨膜,在各小晶粒之间限定有间隙,其中所述上硅化钨膜顺序形成在所述下硅化钨膜上,所述下硅化钨膜和所述上硅化钨膜均用化学气相沉淀方法形成;
通过把所述下硅化钨膜和所述上硅化钨膜进行热处理,使所述下硅化钨膜和所述上硅化钨膜的非晶构造同时结晶,并伴随有氧化膜形成所述上硅化钨膜内多个结晶的小晶粒的表面。
2.如权利要求1所述的方法,其特征在于,所述化学气相沉积法使用低压化学气相沉积法。
3.如权利要求1所述的方法,其特征在于,用于形成所述下硅化钨膜和所述上硅化钨膜的气体包含WF6和SiH4。
4.如权利要求1所述的方法,其特征在于,用于形成所述下硅化钨膜和所述上硅化钨膜的气体包含WF6和SiH2Cl2。
5.如权利要求1所述的方法,其特征在于,所述下硅化钨膜和上硅化钨膜均在400℃至500℃之间的温度下形成。
6.如权利要求1所述的方法,其特征在于,所述氧化膜包含有存在于所述上硅化钨膜内的氟。
7.如权利要求1所述的方法,其特征在于,所述热处理在700℃至900℃之间的温度下进行。
8.如权利要求1所述的方法,其特征在于,所述热处理在氧环境下进行。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950018866A KR0161735B1 (ko) | 1995-06-30 | 1995-06-30 | 반도체 소자의 제조방법 |
KR18866/1995 | 1995-06-30 | ||
KR18866/95 | 1995-06-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1148261A true CN1148261A (zh) | 1997-04-23 |
CN1050222C CN1050222C (zh) | 2000-03-08 |
Family
ID=19419288
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN96106922A Expired - Fee Related CN1050222C (zh) | 1995-06-30 | 1996-07-01 | 制造半导体器件的方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US5837600A (zh) |
JP (1) | JPH0922884A (zh) |
KR (1) | KR0161735B1 (zh) |
CN (1) | CN1050222C (zh) |
DE (1) | DE19626386A1 (zh) |
TW (1) | TW314642B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111593325A (zh) * | 2020-07-01 | 2020-08-28 | 西安微电子技术研究所 | 一种低压化学气相淀积法淀积两层钨硅的方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000150416A (ja) * | 1998-09-01 | 2000-05-30 | Tokyo Electron Ltd | タングステンシリサイド膜及びその成膜方法 |
KR100500935B1 (ko) * | 1998-10-01 | 2005-10-14 | 주식회사 하이닉스반도체 | 물리기상증착법으로 형성된 텅스텐막을 확산방지막으로서 이용하는 반도체 소자 제조 방법 |
KR100505409B1 (ko) * | 1999-11-04 | 2005-08-05 | 주식회사 하이닉스반도체 | 반도체 소자의 게이트 형성방법 |
US6642119B1 (en) | 2002-08-08 | 2003-11-04 | Advanced Micro Devices, Inc. | Silicide MOSFET architecture and method of manufacture |
KR100745604B1 (ko) * | 2006-07-03 | 2007-08-02 | 삼성전자주식회사 | 반도체 소자 및 그 형성 방법 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6292448A (ja) * | 1985-10-18 | 1987-04-27 | Nec Corp | 半導体集積回路装置の製造方法 |
US4684542A (en) * | 1986-08-11 | 1987-08-04 | International Business Machines Corporation | Low pressure chemical vapor deposition of tungsten silicide |
JPH0616556B2 (ja) * | 1987-04-14 | 1994-03-02 | 株式会社東芝 | 半導体装置 |
US4935380A (en) * | 1987-08-04 | 1990-06-19 | Mitsubishi Denki Kabushiki Kaisha | Method for manufacturing semiconductor device |
US4833099A (en) * | 1988-01-07 | 1989-05-23 | Intel Corporation | Tungsten-silicide reoxidation process including annealing in pure nitrogen and subsequent oxidation in oxygen |
JPH02113532A (ja) * | 1988-10-21 | 1990-04-25 | Matsushita Electron Corp | 半導体装置 |
US5541131A (en) * | 1991-02-01 | 1996-07-30 | Taiwan Semiconductor Manufacturing Co. | Peeling free metal silicide films using ion implantation |
JP3248222B2 (ja) * | 1991-06-18 | 2002-01-21 | ソニー株式会社 | ドライエッチング方法 |
JP2723396B2 (ja) * | 1991-09-19 | 1998-03-09 | シャープ株式会社 | 不揮発性メモリ装置の製造方法 |
US5278096A (en) * | 1991-12-23 | 1994-01-11 | At&T Bell Laboratories | Transistor fabrication method |
US5231056A (en) * | 1992-01-15 | 1993-07-27 | Micron Technology, Inc. | Tungsten silicide (WSix) deposition process for semiconductor manufacture |
JPH05267300A (ja) * | 1992-03-19 | 1993-10-15 | Sony Corp | 半導体装置 |
JP2599560B2 (ja) * | 1992-09-30 | 1997-04-09 | インターナショナル・ビジネス・マシーンズ・コーポレイション | ケイ化タングステン膜形成方法 |
JPH06232391A (ja) * | 1992-12-11 | 1994-08-19 | Kawasaki Steel Corp | 半導体装置及びその製造方法 |
JPH06283612A (ja) * | 1993-03-26 | 1994-10-07 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
US5350698A (en) * | 1993-05-03 | 1994-09-27 | United Microelectronics Corporation | Multilayer polysilicon gate self-align process for VLSI CMOS device |
US5441904A (en) * | 1993-11-16 | 1995-08-15 | Hyundai Electronics Industries, Co., Ltd. | Method for forming a two-layered polysilicon gate electrode in a semiconductor device using grain boundaries |
JPH07312353A (ja) * | 1994-05-17 | 1995-11-28 | Fuji Electric Co Ltd | 半導体装置の製造方法 |
-
1995
- 1995-06-30 KR KR1019950018866A patent/KR0161735B1/ko not_active IP Right Cessation
-
1996
- 1996-06-25 US US08/669,916 patent/US5837600A/en not_active Expired - Lifetime
- 1996-06-26 TW TW085107676A patent/TW314642B/zh not_active IP Right Cessation
- 1996-07-01 JP JP8171231A patent/JPH0922884A/ja active Pending
- 1996-07-01 CN CN96106922A patent/CN1050222C/zh not_active Expired - Fee Related
- 1996-07-01 DE DE19626386A patent/DE19626386A1/de not_active Ceased
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111593325A (zh) * | 2020-07-01 | 2020-08-28 | 西安微电子技术研究所 | 一种低压化学气相淀积法淀积两层钨硅的方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1050222C (zh) | 2000-03-08 |
KR970003719A (ko) | 1997-01-28 |
KR0161735B1 (ko) | 1999-02-01 |
JPH0922884A (ja) | 1997-01-21 |
DE19626386A1 (de) | 1997-01-02 |
TW314642B (zh) | 1997-09-01 |
US5837600A (en) | 1998-11-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6096640A (en) | Method of making a gate electrode stack with a diffusion barrier | |
JPH07283411A (ja) | 半導体素子のゲート電極の形成方法 | |
KR100281887B1 (ko) | 반도체장치의 제조방법 | |
CN1050222C (zh) | 制造半导体器件的方法 | |
US6239492B1 (en) | Semiconductor structure with a titanium aluminum nitride layer and method for fabricating same | |
US5652181A (en) | Thermal process for forming high value resistors | |
KR950009926A (ko) | 반도체 소자의 금속배선 형성방법 | |
JPH11274468A (ja) | オーミック電極およびその形成方法ならびにオーミック電極形成用積層体 | |
US6551928B2 (en) | Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure | |
CN1069150C (zh) | 用于制造半导体器件的方法 | |
JP2554634B2 (ja) | 半導体装置の製造方法 | |
KR100846391B1 (ko) | 반도체 소자의 텅스텐 실리사이드 게이트 제조 방법 | |
JP3357456B2 (ja) | 半導体集積回路装置の製造方法および半導体集積回路装置 | |
JP2737470B2 (ja) | 半導体装置の製造方法 | |
JP2673673B2 (ja) | 緻密なチタン窒化膜の形成方法及びこれを用いた半導体素子の製造方法 | |
JPH02113532A (ja) | 半導体装置 | |
JPH0799193A (ja) | 半導体装置の製造方法 | |
JPH02235372A (ja) | 半導体装置とその製造方法 | |
KR940000505B1 (ko) | 반도체 소자의 다층텅스텐 실리사이드 및 그제조방법 | |
JPH0243726A (ja) | 接続配線形成法 | |
JP2817209B2 (ja) | 半導体装置の製造方法 | |
JPH0738103A (ja) | 半導体装置およびその製造方法 | |
JPH05275424A (ja) | 半導体装置の製造方法 | |
JP2001291718A (ja) | 半導体装置及びその製造方法 | |
JPS62291146A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20000308 Termination date: 20130701 |