CN111593325A - 一种低压化学气相淀积法淀积两层钨硅的方法 - Google Patents

一种低压化学气相淀积法淀积两层钨硅的方法 Download PDF

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CN111593325A
CN111593325A CN202010621624.0A CN202010621624A CN111593325A CN 111593325 A CN111593325 A CN 111593325A CN 202010621624 A CN202010621624 A CN 202010621624A CN 111593325 A CN111593325 A CN 111593325A
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李博
折宇
陈宝忠
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Xian Microelectronics Technology Institute
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Abstract

本发明一种低压化学气相淀积法淀积两层钨硅的方法,方法包括如下步骤:步骤1,将待淀积的硅片传入缓冲腔,待缓冲腔的真空度小于300mTorr后,再将待淀积的硅片传入工艺腔中;步骤2,在底压小于100mTorr的工艺腔中通入WF6、SiH4和载气,之后进行低压化学气相淀积反应,在待淀积的硅片上生成一层钨硅;步骤3,将淀积有一层钨硅的硅片传入步骤1所述的缓冲腔中,待工艺腔完成自清洁工艺后,将淀积有一层钨硅的硅片传入工艺腔中按照步骤2进行第二次低压化学气相淀积反应,得到淀积有两层钨硅的硅片,从而有效降低MOS产品的多晶电阻,同时提高产品器件的开关速度。

Description

一种低压化学气相淀积法淀积两层钨硅的方法
技术领域
本发明涉及半导体MOS产品制造技术领域,具体为一种低压化学气相淀积法淀积两层钨硅的方法。
背景技术
钨硅是一种金属化物,难熔、耐高温,化学性质不活泼。在半导体MOS产品制造技术中,通过在多晶硅上淀积一层钨硅,经过退火工艺后形成Polycide复合栅结构,有效降低多晶电阻,提高器件的开关速度。
受到低压化学气相淀积法的工艺能力限制,一次淀积的钨硅较薄,一般在
Figure BDA0002565359000000011
钨硅厚度太薄得到的多晶电阻较大,器件的开关速度较慢。
发明内容
针对现有技术中存在的问题,本发明提供一种低压化学气相淀积法淀积两层钨硅的方法,从而有效降低MOS产品的多晶电阻,同时提高产品器件的开关速度。
本发明是通过以下技术方案来实现:
一种低压化学气相淀积法淀积两层钨硅的方法,包括如下步骤:
步骤1,将待淀积的硅片传入缓冲腔,待缓冲腔的真空度小于300mTorr后,再将待淀积的硅片传入工艺腔中;
步骤2,在底压小于100mTorr的工艺腔中通入WF6、SiH4和载气,之后进行低压化学气相淀积反应,在待淀积的硅片上生成一层钨硅,WF6、SiH4和载气的体积比为(2~3):(400~500):(350~450);
步骤3,将淀积有一层钨硅的硅片传入步骤1所述的缓冲腔中,待工艺腔完成自清洁工艺后,将淀积有一层钨硅的硅片传入工艺腔中按照步骤2进行第二次低压化学气相淀积反应,得到淀积有两层钨硅的硅片。
优选的,步骤1先将待淀积的硅片放入机台的载片台上,之后使用传输手臂将待淀积的硅片从载片台传入缓冲腔。
优选的,步骤2中,WF6、SiH4和载气在0.45Torr~0.75Torr的压力下反应。
进一步,WF6、SiH4和载气在所述的压力下反应25s~120s。
优选的,步骤2中所述的载气为氩气。
优选的,步骤3中使用传输手臂将淀积有一层钨硅的硅片传入步骤1所述的缓冲腔中。
优选的,步骤3得到的硅片中钨硅的厚度为
Figure BDA0002565359000000021
优选的,步骤3得到淀积有两层钨硅的硅片后,先将所述的硅片传入缓冲腔中进行冷却,之后对缓冲腔充保护气体,待缓冲腔的压力达到大气压后将该硅片传至机台的载片台。
进一步,所述的保护气体为氮气。
再进一步,将所述的硅片冷却15s~30s。
与现有技术相比,本发明具有以下有益的技术效果:
本发明一种低压化学气相淀积法淀积两层钨硅的方法,考虑到在半导体制造中,厚度在
Figure BDA0002565359000000022
的范围内,在硅片上淀积的钨硅越厚,多晶电阻越低,因此先将待淀积的硅片传入具有一定真空度的缓冲腔,再将待淀积的硅片传入工艺腔中,按照WF6、SiH4和载气一定的比例在底压小于100mTorr的工艺腔中进行低压化学气相淀积反应;之后将淀积有一层钨硅的硅片再次传入缓冲腔中,待工艺腔完成自清洁工艺后,再将该硅片传入工艺腔中按照之前的步骤进行第二次低压化学气相淀积反应,得到淀积有两层钨硅的硅片,由于硅片未接触到空气,能免于两层钨硅之间产生杂质,从而使两层钨硅的热膨胀系数匹配,避免了热应力的产生,得到的钨硅两层钨硅接触紧密无缝隙,经后续多次热过程不会出现钨硅翘起现象,应用于MOS产品的多晶层中时可有效降低MOS产品的多晶电阻,从而提高器件的开关速度。
附图说明
图1为本发明所述设备的连接示意图。
图2为本发明实施例所述淀积两层钨硅的SEM图。
图中:1-硅片,2-传输手臂,3-缓冲腔,4-工艺气体,5-工艺腔体,6-加热灯,7-干泵,8-载片台。
具体实施方式
下面结合具体的实施例对本发明做进一步的详细说明,所述是对本发明的解释而不是限定。
本发明一种低压化学气相淀积法淀积两层钨硅的方法,具体设备连接如图1所示,包括如下步骤:
步骤1,先将待淀积的硅片放入机台的载片台后,使用传输手臂将硅片从载片台传入缓冲腔。对缓冲腔进行抽真空,待真空度小于300mTorr后,再将硅片传入工艺腔体中。
步骤2,在工艺温度为350℃~400℃、腔体底压小于100mTorr的工艺腔中通入六氟化钨(WF6)、硅烷(SiH4)气体和载气氩气,在0.45Torr~0.75Torr的压力下发生低压化学气相反应25秒~120秒,底压即反应前的压力,在待淀积的硅片上生成第一层钨硅。六氟化钨、硅烷和载气的体积比为(2~3):(400~500):(350~450)。
步骤3,第一次钨硅淀积后,为避免第一层钨硅与大气接触,将硅片使用传输手臂再次传入真空度小于300mTorr的缓冲腔中。待工艺腔完成自清洁工艺后,再将硅片使用传输手臂第二次传入工艺腔中进行第二次钨硅淀积。第二次钨硅的工艺与第一层相同。
步骤4,第二次钨硅淀积完成后将硅片使用传输手臂传入缓冲腔停留15秒~30秒钟进行冷却。冷却完成后对缓冲腔充入氮气,待缓冲腔的压力达到大气压后将硅片使用传输手臂传至机台的载片台,从而在硅片上淀积两层钨硅。
本发明的两层钨硅淀积之间由于硅片未接触到空气,钨硅的厚度从现有的
Figure BDA0002565359000000041
增加至
Figure BDA0002565359000000042
既能增大钨硅厚度又能让多晶电阻降低,提高了MOS产品的质量。
实施例
本发明一种低压化学气相淀积法淀积两层钨硅的方法,包括如下步骤:
步骤1,先将待淀积的硅片放入机台的载片台后,使用传输手臂将硅片从载片台传入缓冲腔。对缓冲腔进行抽真空,待真空度为250mTorr后,再将硅片传入工艺腔体中。
步骤2,在工艺温度为400℃、腔体底压为50mT的工艺腔中通入六氟化钨(WF6)、硅烷(SiH4)气体和载气氩气(Ar),在0.6Torr的压力下发生低压化学气相淀积反应102秒,在待淀积的硅片上生成第一层钨硅。六氟化钨、硅烷和载气的体积比为2.5:450:400。
步骤3,第一次钨硅淀积后,为避免第一层钨硅与大气接触,将硅片使用传输手臂再次传入真空度为250mTorr的缓冲腔中。待工艺腔完成自清洁工艺后,再将硅片使用传输手臂第二次传入工艺腔中进行第二次钨硅淀积。第二次钨硅的工艺与第一层相同。
步骤4,第二次钨硅淀积完成后将硅片使用传输手臂传入缓冲腔停留15秒钟进行冷却。冷却完成后对缓冲腔充入氮气,待缓冲腔的压力达到大气压后将硅片使用传输手臂传至机台的载片台,从而在硅片上淀积两层钨硅。
本发明的钨硅厚度为
Figure BDA0002565359000000043
既能增大又能让多晶电阻降低,提高了MOS产品的质量。在钨硅淀积后经后续多次热过程均未见钨硅翘起现象,SEM图如图2所示,两层钨硅接触紧密无缝隙,该产品多晶电阻从钨硅厚度增加前的27欧姆/平方米降至20欧姆/平方米。
经验证,使用本方法后多晶层上的两层钨硅之间接触紧密无缝隙。该方法有效提高了低压化学气相淀积法一次淀积钨硅的厚度,同时免于两层钨硅之间产生杂质,从而使两层钨硅的热膨胀系数匹配,避免了热应力的产生。应用于MOS产品中,降低了MOS产品的多晶电阻,同时提高了器件的开关速度。

Claims (10)

1.一种低压化学气相淀积法淀积两层钨硅的方法,其特征在于,包括如下步骤:
步骤1,将待淀积的硅片传入缓冲腔,待缓冲腔的真空度小于300mTorr后,再将待淀积的硅片传入工艺腔中;
步骤2,在底压小于100mTorr的工艺腔中通入WF6、SiH4和载气,之后进行低压化学气相淀积反应,在待淀积的硅片上生成一层钨硅,WF6、SiH4和载气的体积比为(2~3):(400~500):(350~450);
步骤3,将淀积有一层钨硅的硅片传入步骤1所述的缓冲腔中,待工艺腔完成自清洁工艺后,将淀积有一层钨硅的硅片传入工艺腔中按照步骤2进行第二次低压化学气相淀积反应,得到淀积有两层钨硅的硅片。
2.根据权利要求1所述的低压化学气相淀积法淀积两层钨硅的方法,其特征在于,步骤1先将待淀积的硅片放入机台的载片台上,之后使用传输手臂将待淀积的硅片从载片台传入缓冲腔。
3.根据权利要求1所述的低压化学气相淀积法淀积两层钨硅的方法,其特征在于,步骤2中,WF6、SiH4和载气在0.45Torr~0.75Torr的压力下反应。
4.根据权利要求3所述的低压化学气相淀积法淀积两层钨硅的方法,其特征在于,WF6、SiH4和载气在所述的压力下反应25s~120s。
5.根据权利要求1所述的低压化学气相淀积法淀积两层钨硅的方法,其特征在于,步骤2中所述的载气为氩气。
6.根据权利要求1所述的低压化学气相淀积法淀积两层钨硅的方法,其特征在于,步骤3中使用传输手臂将淀积有一层钨硅的硅片传入步骤1所述的缓冲腔中。
7.根据权利要求1所述的低压化学气相淀积法淀积两层钨硅的方法,其特征在于,步骤3得到的硅片中钨硅的厚度为
Figure FDA0002565358990000011
8.根据权利要求1所述的低压化学气相淀积法淀积两层钨硅的方法,其特征在于,步骤3得到淀积有两层钨硅的硅片后,先将所述的硅片传入缓冲腔中进行冷却,之后对缓冲腔充保护气体,待缓冲腔的压力达到大气压后将该硅片传至机台的载片台。
9.根据权利要求8所述的低压化学气相淀积法淀积两层钨硅的方法,其特征在于,所述的保护气体为氮气。
10.根据权利要求8所述的低压化学气相淀积法淀积两层钨硅的方法,其特征在于,将所述的硅片冷却15s~30s。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113308676A (zh) * 2021-05-25 2021-08-27 西安微电子技术研究所 一种实现物理气相淀积铝硅铜厚金属薄膜的腔体处理方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5112435A (en) * 1985-10-11 1992-05-12 Applied Materials, Inc. Materials and methods for etching silicides, polycrystalline silicon and polycides
CN1148261A (zh) * 1995-06-30 1997-04-23 现代电子产业株式会社 制造半导体器件的方法
CN1222754A (zh) * 1997-12-19 1999-07-14 西门子公司 在硅化物膜上进行化学汽相淀积的方法和设备
JPH11330005A (ja) * 1998-05-15 1999-11-30 Nec Corp 半導体装置の製造方法
JP2004091813A (ja) * 2002-08-29 2004-03-25 Applied Materials Inc タングステン膜の形成方法およびcvd装置
CN101090065A (zh) * 2006-06-02 2007-12-19 应用材料股份有限公司 尤其在闪存中用于刻蚀多晶硅上钨硅化物的方法
CN101189709A (zh) * 2005-06-01 2008-05-28 朗姆研究公司 具有降低的蚀刻率微负载的钨硅化物蚀刻处理
CN102925874A (zh) * 2011-08-09 2013-02-13 无锡华润上华科技有限公司 一种cvd反应腔体的清洁方法和系统
CN103352205A (zh) * 2013-05-31 2013-10-16 上海华力微电子有限公司 化学气相沉积室的清洁方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5112435A (en) * 1985-10-11 1992-05-12 Applied Materials, Inc. Materials and methods for etching silicides, polycrystalline silicon and polycides
CN1148261A (zh) * 1995-06-30 1997-04-23 现代电子产业株式会社 制造半导体器件的方法
CN1222754A (zh) * 1997-12-19 1999-07-14 西门子公司 在硅化物膜上进行化学汽相淀积的方法和设备
JPH11330005A (ja) * 1998-05-15 1999-11-30 Nec Corp 半導体装置の製造方法
JP2004091813A (ja) * 2002-08-29 2004-03-25 Applied Materials Inc タングステン膜の形成方法およびcvd装置
CN101189709A (zh) * 2005-06-01 2008-05-28 朗姆研究公司 具有降低的蚀刻率微负载的钨硅化物蚀刻处理
CN101090065A (zh) * 2006-06-02 2007-12-19 应用材料股份有限公司 尤其在闪存中用于刻蚀多晶硅上钨硅化物的方法
CN102925874A (zh) * 2011-08-09 2013-02-13 无锡华润上华科技有限公司 一种cvd反应腔体的清洁方法和系统
CN103352205A (zh) * 2013-05-31 2013-10-16 上海华力微电子有限公司 化学气相沉积室的清洁方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113308676A (zh) * 2021-05-25 2021-08-27 西安微电子技术研究所 一种实现物理气相淀积铝硅铜厚金属薄膜的腔体处理方法

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