CN114093812A - 使用光刻-冷冻-光刻-蚀刻工艺的细长接触件 - Google Patents
使用光刻-冷冻-光刻-蚀刻工艺的细长接触件 Download PDFInfo
- Publication number
- CN114093812A CN114093812A CN202111376507.3A CN202111376507A CN114093812A CN 114093812 A CN114093812 A CN 114093812A CN 202111376507 A CN202111376507 A CN 202111376507A CN 114093812 A CN114093812 A CN 114093812A
- Authority
- CN
- China
- Prior art keywords
- contact
- trench
- mask
- forming
- interconnect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 117
- 229910052751 metal Inorganic materials 0.000 claims description 71
- 239000002184 metal Substances 0.000 claims description 71
- 229920002120 photoresistant polymer Polymers 0.000 claims description 57
- 239000000463 material Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 17
- 230000009977 dual effect Effects 0.000 claims description 6
- 230000008014 freezing Effects 0.000 claims description 4
- 238000007710 freezing Methods 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 238000007654 immersion Methods 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 206010010144 Completed suicide Diseases 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- BGTBFNDXYDYBEY-FNORWQNLSA-N 4-(2,6,6-Trimethylcyclohex-1-enyl)but-2-en-4-one Chemical compound C\C=C\C(=O)C1=C(C)CCCC1(C)C BGTBFNDXYDYBEY-FNORWQNLSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Engineering & Computer Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Geometry (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
本申请公开使用光刻‑冷冻‑光刻‑蚀刻工艺的细长接触件。在所描述的示例中,一种方法使用用于接触蚀刻掩模的光刻‑冷冻‑光刻‑蚀刻工艺来形成一种集成电路(1000),该集成电路包括:连接到三个有源区(1002)和/或MOS栅极(1012)的细长接触件(1034);以及连接到两个有源区(1002)和/或MOS栅极(1012)并直接连接到第一级互连件的细长接触件。
Description
本申请是国际申请日为2014年12月17日、进入国家阶段日为2016年06月16日的名称为“使用光刻-冷冻-光刻-蚀刻工艺的细长接触件”的中国专利申请201480068941.7(PCT/US2014/070954)的分案申请。
技术领域
本发明总体涉及集成电路领域,并且尤其涉及集成电路中的互连件。
背景技术
集成电路中的接触件和第一级互连件可以通过利用光刻法定义待蚀刻的区域来形成。例如,接触件可以通过以下步骤来形成:曝光接触光敏层中的接触区,然后对接触光敏层进行显影以形成接触蚀刻掩模,随后蚀刻介电层以形成接触孔并且使用接触金属填充接触孔。类似地,可以通过曝光互连光敏层中的互连区且随后对第一级互连光敏层进行显影以形成沟槽蚀刻掩模而在接触件之上形成金属第一级互连件。可能期望使用光刻设备来曝光接触光敏层和互连光敏层,其具有大于一些接触件和/或一些第一级互连件之间的间距的空间分辨率极限,例如在具有更小空间分辨率极限的光刻设备更昂贵的一些实例中。
发明内容
在所描述的示例中,一种集成电路可以使用光刻-冷冻-光刻-蚀刻工艺通过在两次曝光操作中形成接触件蚀刻图案和/或通过在两次曝光操作中形成第一沟槽蚀刻图案来制造。在一种光刻-冷冻-光刻-蚀刻工艺中,通过对第一光敏层进行曝光和显影来产生第一子图案,随后对第一子图案进行处理以使其在随后的光刻工艺序列中保持完整。第二光敏层在集成电路上形成并且第二曝光和显影步骤被执行用于产生第二子图案。第一子图案与第二子图案结合起来提供蚀刻掩模。接触件蚀刻掩模被用来形成接触件,其包括细长接触件,所述细长接触件与多于一个有源区或MOS晶体管栅极连接并且不在存储单元内。第一互连沟槽蚀刻掩模被用于在所述接触件正上方形成金属第一级互连件。精确地连接到两个有源区和/或MOS栅极的细长接触件也直接连接到第一级互连件。
附图说明
图1A至图1H是根据一个示例形成的集成电路的俯视图,其以连续的制造阶段来描述。
图2A至图2K是根据一个示例形成的集成电路的横截面图,其以连续的制造阶段来描述。
图3A至图3H是根据一个示例形成的集成电路的横截面图,其以连续的制造阶段来描述。
具体实施方式
出于本说明书的目的,术语“接触件”指连接到集成电路中的有源区和/或金属氧化半导体(MOS)晶体管栅极(以下被称为MOS栅极)的金属元件。有源区和/或MOS栅极可以包括一层金属硅化物,使得接触件与金属硅化物层接触。MOS栅极包括在场氧化物上方的相邻栅极材料。
集成电路可以使用光刻-冷冻-光刻-蚀刻工艺通过对接触蚀刻子掩模执行两次曝光和显影循环来形成。一种可选的接触硬掩模层可以被用于制造序列中。所述接触件包括细长接触件,其为连接到集成电路中的多于一个有源区或MOS栅极的接触件并且不在存储单元内。通过在接触件之上形成金属间电介质(IMD)层并且使用光刻-冷冻-光刻-蚀刻工艺对沟槽蚀刻子掩模执行两次曝光和显影循环,可以在接触件正上方形成金属镶嵌(Damascene)第一级互连件。一种可选的沟槽硬掩模层可以被用在制造序列中。互连沟槽被蚀刻在IMD层中并穿过互连沟槽硬掩模层。所述互连沟槽填充有互连材料,例如衬层金属和铜填充金属。精确地连接到两个有源区和/或MOS栅极的细长接触件也直接连接到第一级互连元件。
图1A至图1H是根据一个示例形成的集成电路的俯视图,其以连续的制造阶段来描述。参考图1A,集成电路1000包括有源区1002(其不是存储单元的一部分)、反相器p型有源区1004和反相器n型有源区1006(其为互补金属氧化物半导体(CMOS)反相器的一部分),并且可能包括双输入逻辑门p型有源区1008和双输入逻辑门n型有源区1010(其为CMOS双输入逻辑门的一部分)。集成电路1000也包括MOS栅极1012(其不是存储单元的一部分)、反相器MOS栅极1014(其为CMOS反相器的一部分并且横跨反相器p型有源区1004和反相器n型有源区1006),并且如果存在CMOS双输入逻辑门,则包括两个双输入逻辑门MOS栅极1016(其横跨双输入逻辑门p型有源区1008和双输入逻辑门n型有源区1010)。PMD(金属前电介质)层(未示出)被形成在集成电路1000的已有顶层上方,其覆盖有源区1002、1004、1008和1010以及MOS栅极1012、1014和1016。接触硬掩模层(未示出)可以被形成在PMD层上方。该接触硬掩模层可以包括能够抵抗PMD主层的蚀刻剂的材料(例如,氮化硅、碳化硅、氧化铝和在氮氧化硅之下的无定形碳)的一个或多个子层。
用于接触件的区域在集成电路1000内被定义。参考图1A,期望的接触区可以包括小型/紧凑型(compact)单节点接触区1018,其长宽比在0.8至1.0之间。长宽比是指接触区的横向维度。该接触区也可以包括细长单节点接触图案1020,其长宽比大于2。该接触区进一步包括细长接触区1022,其定义用于直接连接到多于一个有源区和/或MOS栅极的细长接触件的区域。细长接触图案1022的一些实例可以是线性的。如图1A所描述,细长接触图案1022的一些实例可以是非线性的,例如具有一个或多个弯曲部。
参考图1B,第一接触蚀刻子掩模1024被形成在集成电路1000上方。为清楚起见,没有在图1B中示出图1A中描述的有源区和MOS栅极。第一接触蚀刻子掩模1024在图1B中被描述为具有阴影线图案,并且接触区1018、1020和1022被描述为无阴影线。第一接触蚀刻子掩模1024的边缘形成接触区1018、1020和1022的部分边界。第一接触蚀刻子掩模1024可以例如通过以下步骤来形成:在集成电路1000上形成底部抗反射涂层(BARC),然后在BARC上形成第一接触光刻胶层,随后在第一接触光刻胶层上形成减阻顶层(其减小在浸润式曝光操作中的阻力)。在第一接触曝光操作中使用第一接触子图案对第一接触光刻胶层进行曝光(例如通过浸润式扫描仪光刻工具)并进行显影。已显影的第一接触光刻胶层在被称为“冷冻”的工艺中被处理以形成第一接触蚀刻子掩模1024,从而在生产第二接触蚀刻子掩模的后续工艺序列中使其保持完整。可以执行例如由Masafumi Hori等人在“Sub-40nm Half-Pitch Double Patterning with Resist Freezing Process,”Advances in ResistMaterials and Processing Technology XXV,Proc.Of SPIE Vol.6923,69230H,2008中所描述的冷冻步骤。用于处理已显影的第一接触光刻胶层以使其在形成第二接触蚀刻子掩模的过程中保持完整的其他工艺也在当前示例的范围内。
参考图1C,第二接触蚀刻子掩模1026被形成在集成电路1000上方,因此第一接触蚀刻子掩模1024与第二接触蚀刻子掩模1026结合形成接触蚀刻掩模,其暴露出位于接触区1018、1020和1022中的集成电路1000的顶表面。接触区1018、1020和1022的边界由第一接触蚀刻子掩模1024和第二接触蚀刻子掩模1026的组合边缘形成。可以例如通过以下步骤形成第二接触蚀刻子掩模1026:形成包含BARC、第二接触光刻胶层和减阻顶层的层堆叠,接着在第二接触曝光操作中使用第二接触子图案对第二接触光刻胶层进行曝光,并且对第二接触光刻胶层进行显影。在当前示例的一个版本中,在生产接触蚀刻掩模时不执行额外的曝光和显影序列。在当前示例的一个版本中,接触区1018、1020和1022的一些构件可以被分开小于用来执行第一接触曝光操作和/或第二接触曝光操作的光刻设备的空间分辨率极限。
利用组合式接触蚀刻掩模(1024+1026)在PMD层中形成接触孔。在使用接触硬掩模层的当前示例的版本中,通过第一接触蚀刻工艺例如反应离子蚀刻(RIE)工艺从接触硬掩模层上移除接触硬掩模材料。然后通过使用蚀刻的硬掩模层作为模板的第二接触蚀刻工艺在PMD层中形成接触孔。组合式接触蚀刻掩模(1024+1026)可以在第一接触蚀刻工艺之后、在第二接触蚀刻工艺期间或者在第二接触蚀刻工艺之后被移除。在不具有接触硬掩模层的当前示例的版本中,通过使用接触蚀刻工艺例如RIE工艺,利用接触蚀刻掩模作为模板来移除PMD材料,从而在PMD层中形成接触孔。接触蚀刻掩模可以在接触蚀刻工艺期间或之后被移除。
参考图1D,PMD层中的接触孔被填充接触金属以形成多个接触件,包括:小型单节点接触件1028,其长宽比在0.8至1.0之间;细长单节点接触件1030,其长宽比大于2;双节点细长接触件1032,其精确地连接到两个有源区1002和/或MOS栅极1012并且随后被直接连接到第一级互连件;以及多节点细长接触件1034,其连接到三个或更多有源区1002和/或MOS栅极1012。一些双节点细长接触件1032是CMOS反相器中的反相器输出节点细长接触件,其将反相器p型有源区1004的输出节点与反相器n型有源区1006的输出节点相连。如果形成了CMOS双输入逻辑门,则双节点细长接触件中的一个是CMOS双输入逻辑门接触件1036,其将CMOS双输入逻辑门p型有源区1008的输出节点与CMOS双输入逻辑门n型有源区1010的输出节点相连。可以例如通过以下步骤形成接触件1028、1030、1032、1034和1036:用接触衬层金属例如钛或氮化钛填充接触孔,接着用接触填充金属例如钨填充接触孔,随后使用蚀刻和/或CMP方法从PMD层的顶表面上移除接触填充金属和接触衬层金属。
参考图1E,IMD层(未示出)被形成在接触件和PMD层上。该IMD层可以包括二氧化硅和/或低k介电材料,例如有机硅酸盐玻璃(OSG)、碳掺杂硅氧化物(SiCO或CDO)或甲基倍半硅氧烷(MSQ)。互连硬掩模层(未示出)可以被形成在IMD层上方。该互连硬掩模层可以包括抵抗IMD层的蚀刻剂的材料(例如,氮化硅、碳化硅、氧化铝和氮化钛)的一个或多个子层。用于期望的第一级互连件的区域1038被定义在集成电路1000内。
参考图1F,第一沟槽蚀刻子掩模1040被形成在集成电路1000的顶表面上。为清楚起见,在图1A中描述的有源区和MOS栅极未显示在图1F中。第一沟槽蚀刻子掩模1040的边缘形成期望的互连区1038的部分边界。可以例如通过以下步骤形成第一沟槽蚀刻子掩模1040:在集成电路1000上形成BARC,接着在BARC上形成第一沟槽光刻胶层,随后在第一沟槽光刻胶层上形成减阻顶层。在第一沟槽曝光操作中使用第一沟槽子图案对第一沟槽光刻胶层进行曝光(例如使用浸润式扫描仪光刻工具)并且进行显影。已显影的第一沟槽光刻胶层在形成第一沟槽蚀刻子掩模1040的冷冻工艺中被处理,以使其在生产第二沟槽蚀刻子掩模的后续工艺序列中保持完整。用于处理已显影的第一沟槽光刻胶层以使其在形成第二沟槽蚀刻子掩模期间保持完整的其他工艺也在当前示例的范围内。
参考图1G,第二沟槽蚀刻子掩模1042被形成在集成电路1000上方,因此第一沟槽蚀刻子掩模1040与第二沟槽蚀刻子掩模1042结合形成沟槽蚀刻掩模,其暴露出在互连区1038中的集成电路1000的顶表面。互连区1038的边界由第一沟槽蚀刻子掩模1040和第二沟槽蚀刻子掩模1042的组合边缘形成。可以例如通过以下步骤形成第二沟槽蚀刻子掩模1042:形成包括BARC、第二沟槽光刻胶层和减阻顶层的层堆叠,接着在第二沟槽曝光操作中利用第二沟槽子图案对第二沟槽光刻胶层进行曝光,并且对第二沟槽光刻胶层进行显影。在当前示例的一个版本中,在生产沟槽蚀刻掩模中不执行额外的曝光和显影序列。在当前示例的一个版本中,互连区1038的一些构件被分开小于用来执行第一沟槽曝光操作和/或第二沟槽曝光操作的光刻设备的空间分辨率极限。
使用沟槽蚀刻掩模在IMD层中形成互连沟槽。在使用互连硬掩模层的当前示例的版本中,通过第一沟槽蚀刻工艺例如RIE工艺从互连硬掩模层上移除互连硬掩模材料。然后通过使用已蚀刻的硬掩模层作为模板的第二沟槽蚀刻工艺在IMD层中形成沟槽。在第一沟槽蚀刻工艺之后、在第二沟槽蚀刻工艺期间或者在第二沟槽蚀刻工艺之后,可以移除沟槽蚀刻掩模。在不具有互连硬掩模层的当前示例的版本中,通过使用沟槽蚀刻工艺例如RIE工艺,利用沟槽蚀刻掩模作为模板来移除IMD材料,从而在IMD层中形成沟槽。可以在沟槽蚀刻工艺期间或者之后移除沟槽蚀刻掩模。
参考图1H,多个第一级互连件1044被形成在互连沟槽中,例如通过使用互连金属(例如包含氮化钽的衬层金属和包含至少90%的铜的填充金属)填充互连沟槽,并且利用CMP操作去除不需要的衬层金属和填充金属。至少一部分第一级互连件1044的底表面直接连接到一部分或者可能全部的接触件。双节点细长接触件1032直接连接到第一级互连件1044。额外多级介电层和互连件(未示出)(例如垂直互连件,也被称为通孔)被形成在第一级互连件1044之上。所述额外多级中的多个互连件直接连接到多个第一级互连件1044的一部分或所有构件。
图2A至图2K是根据一个示例利用接触件和沟槽硬掩模形成的集成电路的横截面图,其以连续的制造阶段来描述。参考图2A,集成电路2000被形成在衬底2002中和衬底2002上,该衬底可以是单晶硅晶片、绝缘体上硅(SOI)晶片、具有不同晶向区域的混合取向技术(HOT)晶片或者适用于制造集成电路2000的其他材料。场氧化物2004的元件被形成在衬底2002的顶表面处,例如利用浅沟槽隔离(STI)和局部硅氧化隔离(LOCOS)工艺由厚度在250到600纳米之间的二氧化硅形成。在STI工艺中,可以通过高密度等离子(HDP)或高深宽比工艺(HARP)来沉积二氧化硅。位于场氧化物2004之间的衬底2002的顶表面处的区域是集成电路2000的有源区2006。有源区2006可以包括位于衬底2002的顶表面处的一层金属硅化物。MOS栅极2008被形成在衬底2002上方。PMD层2010被形成在有源区2006和MOS栅极2008上方。PMD层2010可以是介电层堆叠,其包括PMD衬层、PMD主层和可选的PMD盖层。在至少一个示例中,PMD衬层(未示出)是厚度在10到100纳米之间的氮化硅或二氧化硅,其通过等离子体增强化学气相沉积(PECVD)沉积在有源区2006和MOS栅极2008上方。在至少一个示例中,PMD主层是厚度在100到1000纳米的一层二氧化硅、磷硅酸盐玻璃(PSG)或硼磷硅玻璃(BPSG),其通过PECVD沉积在PMD衬层的顶表面上,并且有时通过化学机械抛光(CMP)工艺来找平(leveled)。在至少一个示例中,可选的PMD盖层(未示出)是10到100纳米的硬材料(例如,氮化硅、碳氮化硅或碳化硅),其被形成在PMD主层的顶表面上。接触硬掩模层2012被形成在PMD层2010上方。接触硬掩模层2012可以具有如参考图1A所描述的材料和性质。
如下所述,第一接触蚀刻子掩模2014被形成在接触硬掩模层2012上。第一接触光敏层被形成在接触硬掩模层2012上方。第一接触光敏层可以包括BARC层、光刻胶层以及一个或多个可选层来改进光刻工艺。在集成电路2000上执行使用光刻设备(例如浸没式晶片扫描仪)的第一接触蚀刻子掩模曝光操作并执行第一接触蚀刻子掩模显影操作以生产已显影的光刻胶层。在已显影的光刻胶层上执行第一冷冻操作以形成第一接触蚀刻子掩模2014,以使其在生产第二接触蚀刻子掩模的后续工艺序列中保持完整。第一接触蚀刻子掩模2014的边缘形成为集成电路2000中的接触件定义的区域的部分边界。
参考图2B,第二接触蚀刻子掩模2016被形成在接触硬掩模层2012上,因此第一接触蚀刻子掩模2014与第二接触蚀刻子掩模2016结合形成接触蚀刻掩模,该接触蚀刻掩模暴露出接触区中的接触硬掩模层2012的顶表面。可以例如通过形成包含BARC、光刻胶层和减阻顶层的层堆叠并且随后对该光刻胶层进行曝光和显影来形成第二接触蚀刻子掩模2016。在当前示例的一个版本中,在生产接触蚀刻掩模时不执行额外的曝光和显影序列。
参考图2C,在集成电路2000上执行接触硬掩模蚀刻工艺,其从接触区中的接触硬掩模层2012上去除材料以形成接触硬掩模孔2018。在至少一个示例中,接触硬掩模蚀刻工艺可以是RIE工艺。第一接触蚀刻子掩模2014和第二接触蚀刻子掩模2016可以在接触硬掩模蚀刻工艺完成之后被移除,或者可以在后续操作期间被移除。
参考图2D,在集成电路2000上执行接触蚀刻工艺,其从接触区中的PMD层2010上移除材料以形成接触孔2020。接触蚀刻工艺使用已蚀刻的接触硬掩模层2012作为模板。接触硬掩模层2012中的剩余材料可以在接触蚀刻工艺完成之后被移除。
图2E描述在完成接触金属化工艺之后的集成电路2000,其形成接触件2022。在当前示例的一个版本中,一层接触衬层金属2024和接触填充金属2026在接触孔中相继形成。在至少一个示例中,接触衬层金属2024可以是钛、氮化钛或适用于形成接触所述有源区2006和MOS栅极2008的其他金属。在至少一个示例中,接触填充金属2026可以是钨。接触衬层金属2024可以例如通过溅射、原子层沉积(ALD)、金属有机化学气相沉积(MOCVD)或其他工艺来形成。在至少一个示例中,可以通过溅射、MOCVD或其他工艺形成接触填充金属2026。可以通过CMP和/或回蚀工艺移除PMD层2010的顶表面上的接触衬层金属和接触填充金属。接触件2022包括:双节点细长接触件,其精确地连接到两个有源区2006和/或MOS栅极2008并且随后被直接连接到第一级互连件;以及多节点细长接触件,其连接到三个或更多有源区2006和/或MOS栅极2008。
参考图2F,IMD层2028被形成在PMD层2010上和接触件2022的顶表面上。IMD层2028可以具有如参考图1E所描述的材料和性质。互连硬掩模层2030被形成在IMD层2028上。互连硬掩模层2030可以具有如参考图1E所描述的材料和性质。使用类似于参考图2A所描述的工艺序列在互连硬掩模层2030上形成第一沟槽蚀刻子掩模2032。在已显影的光刻胶层上执行第二冷冻操作以形成第一沟槽蚀刻子掩模2032,以使其在生产第二沟槽蚀刻子掩模的后续工艺序列中保持完整。第一沟槽蚀刻子掩模2032的边缘形成为集成电路2000中的互连件定义的区域的部分边界。
参考图2G,第二沟槽蚀刻子掩模2034被形成在互连硬掩模层2030上,因此第一沟槽蚀刻子掩模2032与第二沟槽蚀刻子掩模2034结合形成沟槽蚀刻掩模,该沟槽蚀刻掩模暴露出在互连区中的互连硬掩模层2030的顶表面。在至少一个示例中,可以通过形成包含BARC、光刻胶层和减阻顶层的层堆叠并且随后对光刻胶层进行曝光和显影来形成第二沟槽蚀刻子掩模2034。在当前示例的一个版本中,在生产沟槽蚀刻掩模中不执行额外的曝光和显影序列。
参考图2H,在集成电路2000上执行互连硬掩模蚀刻工艺,其将材料从互连区中的互连硬掩模层2030上移除以形成互连硬掩模孔2036。在至少一个示例中,互连硬掩模蚀刻工艺可以是RIE工艺。第一沟槽蚀刻子掩模2032和第二沟槽蚀刻子掩模2034可以在互连硬掩模蚀刻工艺完成之后被移除,或者可以在后续操作期间被移除。
参考图2I,在集成电路2000上执行互连沟槽蚀刻工艺,其将材料从互连区中的IMD层2028上移除以形成互连沟槽2038。该沟槽蚀刻工艺使用已蚀刻的互连硬掩模层2030作为模板。互连硬掩模层2030中的剩余材料可以在互连沟槽蚀刻工艺完成之后被移除。
图2J描述了在互连金属化工艺完成之后的集成电路2000,其形成互连件2040。在当前示例的一个版本中,一层沟槽衬层金属2042和沟槽填充金属2044在沟槽中相继形成。在至少一个示例中,沟槽衬层金属2042可以是氮化钽、氮化钛或适用于形成电气连接至接触件2022的其他金属。在至少一个示例中:沟槽填充金属2044可以是至少90%的铜;沟槽衬层金属2042可以通过溅射、ALD、MOCVD或其他工艺形成;并且沟槽填充金属2044可以通过溅射、镀覆或其他工艺形成。在IMD层2028的顶表面上的沟槽衬层金属和沟槽填充金属可以通过CMP和/或回蚀工艺被移除。双节点细长接触件精确地连接到两个有源区2006和/或MOS栅极2008并且直接连接到第一级互连件2040。
参考图2K,额外多级的介电层和互连件2046(例如,通孔2048和第二级连接件2050)被形成在第一级互连件2040上方。所述额外多级2046中的多个通孔2048直接连接到第一级互连件2040。
图3A至3H是根据一个示例不使用硬掩模形成的集成电路的横截面图,其以连续的制造阶段来描述。参考图3A,集成电路3000被形成在衬底3002中和衬底3002上,该衬底可以是单晶硅晶片、SOI晶片、具有不同晶向区域的HOT晶片或者适用于制造集成电路3000的其他材料。场氧化物3004的元件被形成在衬底3002的顶表面上,例如利用STI或LOCOS工艺由厚度在250至600纳米之间的二氧化硅形成。在STI工艺中,二氧化硅可以通过HDP或HARP工艺来沉积。在场氧化物3004之间的衬底3002的顶表面处的区域是集成电路3000的有源区3006。有源区3006可以包括在衬底3002的顶表面处的一层金属硅化物。MOS栅极3008被形成在衬底3002上方。PMD层3010被形成在有源区3006和MOS栅极3008上方。PMD层3010可以具有参考图2A所描述的材料和性质。如参考图2A所描述,使用第一冷冻操作在PMD层3010上形成第一接触蚀刻子掩模3012,以使得第一接触蚀刻子掩模3012在生产第二接触蚀刻子掩模的后续工艺序列中保持完整。第一接触蚀刻子掩模3012的边缘形成了为集成电路3000中的接触件定义的区域的部分边界。
参考图3B,第二接触蚀刻子掩模3014被形成在PMD层3010上,因此第一接触蚀刻子掩模3012与第二接触蚀刻子掩模3014结合形成接触蚀刻掩模,该接触蚀刻掩模暴露出在接触区中的PMD层3010的顶表面。可以例如通过形成包括BARC、光刻胶层和减阻顶层的层堆叠并且随后对光刻胶层进行曝光和显影来形成第二接触蚀刻子掩模3014。在当前示例的一个版本中,在生产接触蚀刻掩模时不执行额外的曝光和显影序列。
参考图3C,在集成电路3000上执行接触蚀刻工艺,其将材料从接触区中的PMD层3010上移除以形成接触孔3016。在至少一个示例中,接触蚀刻工艺可以是RIE工艺。第一接触蚀刻子掩模3012和第二接触蚀刻子掩模3014可以在接触蚀刻工艺完成之后被移除。
图3D描述了在接触金属化工艺完成之后的集成电路3000,其形成包括接触金属衬层3020和接触填充金属3022的接触件3018,如参考图2E所描述。接触件3018包括:双节点细长接触件,其精确地连接至到两个有源区3006和/或MOS栅极3008并且随后被直接连接到第一级互连件;以及多节点细长接触件,其连接到三个或更多有源区3006和/或MOS栅极3008。
参考图3E,IMD层3024被形成在PMD层3010上和接触件3022的顶表面上。IMD层3024可以具有参考图1E所描述的材料和性质。使用类似于参考图2A所描述的工艺序列在IMD层3024上形成第一沟槽蚀刻子掩模3026。在已显影的光刻胶上执行第二冷冻操作以形成第一沟槽蚀刻子掩模3026,以使其在生产第二沟槽蚀刻子掩模的后续工艺序列中保持完整。第一沟槽蚀刻子掩模3026的边缘形成了为集成电路3000中的互连件定义的区域的部分边界。
参考图3F,第二沟槽蚀刻子掩模3028被形成在IMD层3024上,因此第一沟槽蚀刻子掩模3026与第二沟槽蚀刻子掩模3028结合形成沟槽蚀刻掩模,该沟槽蚀刻掩模暴露出在互连区中的IMD层3024的顶表面。可以例如通过形成包括BARC、光刻胶层和减阻顶层的层堆叠并且随后对光刻胶层进行曝光和显影来形成第二沟槽蚀刻子掩模3028。在当前示例的一个版本中,在生产沟槽蚀刻掩模时不执行额外的曝光和显影序列。
参考图3G,在集成电路3000上执行互连沟槽蚀刻工艺,其将材料从互连区中的IMD层3024上移除以形成互连沟槽3030。该沟槽蚀刻工艺使用由第一沟槽蚀刻子掩模3026结合第二沟槽蚀刻子掩模3028形成的沟槽蚀刻掩模作为模板。第一沟槽蚀刻子掩模3026和第二沟槽蚀刻子掩模3028中的剩余材料可以在互连沟槽蚀刻工艺完成后被移除。
图3H描述了在互连金属化工艺完成之后的集成电路3000,其形成互连件3032。在当前示例的一个版本中,一层沟槽衬层金属3034和沟槽填充金属3036在沟槽中相继形成。沟槽衬层金属3034和沟槽填充金属3036可以如参考图2J所描述的那样形成。在IMD层3024的顶表面上的沟槽衬层金属和沟槽填充金属可以由CMP和/或回蚀工艺去除。双节点细长接触件精确地连接到两个有源区3006和/或MOS栅极3008并且直接连接到第一级互连件3032。如参考图2K所描述,额外多级的介电层和互连件被形成在第一级互连件3032上方。
修改可能存在于所描述的实施例中,并且在权利要求的范围内的其他实施例是可能的。
Claims (20)
1.一种形成集成电路的方法,包括:
在衬底的顶表面处形成场氧化物的元件,使得所述场氧化物之间的所述衬底的区域是有源区;
在所述衬底上方形成金属氧化物半导体晶体管栅极即MOS晶体管栅极;
在所述有源区和所述MOS晶体管栅极上方形成金属前介电层即PMD层,所述PMD层具有为接触件定义的接触区;
通过包括以下步骤的工艺在所述PMD层上方形成接触蚀刻掩模:
在所述PMD层上方形成第一接触光刻胶层;
在所述第一接触光刻胶层上使用第一接触子图案执行第一接触曝光操作;
对所述第一接触光刻胶层进行显影;
在所述第一接触光刻胶层上执行冷冻工艺以形成所述接触蚀刻掩模的第一接触蚀刻子掩模;
在所述PMD层上方形成第二接触光刻胶层;
在所述第二接触光刻胶层上使用第二接触子图案执行第二接触曝光操作;以及
对所述第二接触光刻胶层进行显影以形成所述接触蚀刻掩模的第二接触蚀刻子掩模,使得所述接触区的边界由所述第一接触蚀刻子掩模和所述第二接触蚀刻子掩模的组合边缘形成;
在由所述接触区定义的区域中的所述PMD层中蚀刻多个接触孔;
使用接触金属填充所述接触孔以形成多个接触件,所述多个接触件包括:
双节点细长接触件,其精确地连接到两个有源区和/或MOS栅极;和
多节点细长接触件,其连接到三个或更多有源区和/或MOS栅极;
在所述PMD层之上形成金属间介电层即IMD层,所述IMD层具有为互连件定义的互连区;
在由所述互连区定义的区域中的所述IMD层中蚀刻多个互连沟槽;以及
使用互连金属填充所述互连沟槽以形成多个第一级互连件,使得每个所述双节点细长接触件直接连接到至少一个所述第一级互连件,
其中所述接触区的相对边缘由所述第一接触蚀刻子掩模和所述第二接触蚀刻子掩模形成。
2.根据权利要求1所述的方法,其进一步包括:
在所述形成接触蚀刻掩模之前,在所述PMD层上方形成接触硬掩模层;并且
在所述形成接触蚀刻掩模之后并且在所述PMD层中蚀刻多个所述接触孔之前,在所述集成电路上执行接触硬掩模蚀刻工艺,以便从所述接触区中的所述接触硬掩模层上移除材料以形成接触硬掩模孔,从而使用所述接触硬掩模层作为模板执行在所述PMD层中蚀刻多个所述接触孔。
3.根据权利要求1所述的方法,其中所述使用接触金属填充所述接触孔包括:
在所述接触孔中形成接触衬层金属;以及
在所述接触孔中形成接触填充金属。
4.根据权利要求1所述的方法,其中所述使用互连金属填充所述互连沟槽包括:
在所述互连沟槽中形成沟槽衬层金属;以及
在所述互连沟槽中形成沟槽填充金属。
5.根据权利要求1所述的方法,其中在所述形成接触蚀刻掩模中不执行额外的曝光和显影序列。
6.根据权利要求1所述的方法,其进一步包括通过包含以下步骤的工艺形成CMOS反相器:
形成所述场氧化物的元件以在所述衬底中提供反相器p型有源区,所述反相器p型有源区包括输出节点;
形成所述场氧化物的元件以在所述衬底中邻近所述反相器p型有源区提供反相器n型有源区,所述反相器n型有源区包括输出节点;
在所述衬底之上形成反相器MOS栅极,所述反相器MOS栅极横跨所述反相器p型有源区和所述反相器n型有源区;
形成所述接触蚀刻掩模以提供连接所述反相器p型有源区的所述输出节点和所述反相器n型有源区的所述输出节点的反相器输出节点细长接触件;以及
形成所述第一级互连件中的一个,其被直接连接到所述反相器输出节点细长接触件。
7.一种形成集成电路的方法,包括:
在衬底的顶表面处形成场氧化物的元件,使得位于所述场氧化物之间的所述衬底的区域是有源区;
在所述衬底上方形成MOS晶体管栅极;
在所述有源区和所述MOS晶体管栅极上方形成PMD层,所述PMD层具有为接触件定义的接触区;
在由所述接触区定义的区域中在所述PMD层中蚀刻多个接触孔;
使用接触金属填充所述接触孔以形成多个接触件,所述多个接触件包括:
双节点细长接触件,其精确地连接到两个有源区和/或MOS栅极;和
多节点细长接触件,其连接到三个或更多有源区和/或MOS栅极;
在所述PMD层之上形成IMD层,所述IMD层具有为互连件定义的互连区;通过包括以下步骤的工艺在所述IMD层上方形成沟槽蚀刻掩模:
在所述IMD层上方形成第一沟槽光刻胶层;
在所述第一沟槽光刻胶层上使用第一沟槽子图案执行第一沟槽曝光操作;
对所述第一沟槽光刻胶层进行显影;
在所述第一沟槽光刻胶层上执行冷冻工艺以形成所述沟槽蚀刻掩模的第一沟槽蚀刻子掩模,使得所述第一沟槽蚀刻子掩模的边缘形成所述互连区的部分边界;
在所述IMD层上方形成第二沟槽光刻胶层;
在所述第二沟槽光刻胶层上使用第二沟槽子图案执行第二沟槽曝光操作;以及
对所述第二沟槽光刻胶层进行显影以形成所述沟槽蚀刻掩模的第二沟槽蚀刻子掩模,使得所述互连区的边界由所述第一沟槽蚀刻子掩模和所述第二沟槽蚀刻子掩模的组合边缘形成;
在由所述互连区定义的区域中在所述IMD层中蚀刻多个互连沟槽;以及
使用互连金属填充所述互连沟槽以形成多个第一级互连件,使得每个所述双节点细长接触件直接连接到所述第一级互连件中的至少一个,
其中所述互连区的相对边缘由所述第一沟槽蚀刻子掩模和所述第二沟槽蚀刻子掩模形成。
8.根据权利要求7所述的方法,其进一步包括:
在所述形成沟槽蚀刻掩模之前,在所述IMD层上方形成互连硬掩模层;以及
在所述形成沟槽蚀刻掩模之后并且在所述IMD层中蚀刻多个所述互连沟槽之前,在所述集成电路上执行互连硬掩模蚀刻工艺,以便从所述互连区内的所述互连硬掩模层上移除材料以形成互连硬掩模孔,从而使用所述互连硬掩模层作为模板执行在所述IMD层中蚀刻多个所述互连沟槽。
9.根据权利要求7所述的方法,其中所述使用互连金属填充所述互连沟槽包括:
在所述互连沟槽中形成沟槽衬层金属;以及
在所述互连沟槽中形成沟槽填充金属。
10.根据权利要求7所述的方法,其中在所述形成沟槽蚀刻掩模中没有执行额外的曝光和显影序列。
11.根据权利要求7所述的方法,其中:
使用具有空间分辨率极限的光刻设备来执行所述第一沟槽曝光操作;并且
所述互连区的一些构件被分开小于所述空间分辨率极限。
12.根据权利要求7所述的方法,其进一步包括通过包含以下步骤的工艺形成CMOS反相器:
形成所述场氧化物的元件以在所述衬底中提供反相器p型有源区,所述反相器p型有源区包括输出节点;
形成所述场氧化物的元件以在所述衬底中提供与所述反相器p型有源区相邻的反相器n型有源区,所述反相器n型有源区包括输出节点;
在所衬底上方形成反相器MOS栅极,所述反相器MOS栅极横跨所述反相器p型有源区和所述反相器n型有源区;
形成所述双节点细长接触件以提供连接所述反相器p型有源区的所述输出节点和所述反相器n型有源区的所述输出节点的反相器输出节点细长接触件;以及
形成接触蚀刻掩模以便使所述第一级互连件中的一个与所述反相器输出节点细长接触件直接连接。
13.一种形成集成电路的方法,其包括:
在衬底的顶表面处形成场氧化物的元件,使得所述场氧化物之间的所述衬底的区域是有源区;
在所述衬底上方形成MOS晶体管栅极;
在所述有源区和所述MOS晶体管栅极上方形成PMD层,所述PMD层具有为接触件定义的接触区;
通过包括以下步骤的工艺在所述PMD层上方形成接触蚀刻掩模:
在所述PMD层上方形成第一接触光刻胶层;
在所述第一接触光刻胶层上使用第一接触子图案执行第一接触曝光操作;
对所述第一接触光刻胶层进行显影;
在所述第一接触光刻胶层上执行冷冻工艺以形成所述接触蚀刻掩模的第一接触蚀刻子掩模,使得所述第一接触蚀刻子掩模的边缘形成所述接触区的部分边界;
在所述PMD层上方形成第二接触光刻胶层,同时所述第一接触蚀刻子掩模保留在所述PMD层上;
在所述第二接触光刻胶层上使用第二接触子图案的执行第二接触曝光操作;以及
对所述第二接触光刻胶层进行显影以形成所述接触蚀刻掩模的第二接触蚀刻子掩模,使得所述接触区的边界由所述第一接触蚀刻子掩模和所述第二接触蚀刻子掩模的组合边缘形成;
在由所述接触区定义的区域中在所述PMD层中蚀刻多个接触孔;
使用接触金属填充所述接触孔以形成多个接触件,所述多个接触件包括:
双节点细长接触件,其精确地连接到两个有源区和/或MOS栅极;和
多节点细长接触件,其连接到三个或更多有源区和/或MOS栅极;
在所述PMD层上方形成IMD层,所述IMD层具有为互连件定义的互连区;通过包括以下步骤的工艺在所述IMD层上方形成沟槽蚀刻掩模:
在所述IMD层上方形成第一沟槽光刻胶层;
在所述第一沟槽光刻胶层上使用第一沟槽蚀刻子图案执行第一沟槽曝光操作;
对所述第一沟槽光刻胶层进行显影;
在所述第一沟槽光刻胶层上执行冷冻操作以形成所述沟槽蚀刻掩模的第一沟槽蚀刻子掩模,使得所述第一沟槽蚀刻子掩模的边缘形成所述互连区的部分边界;
在所述IMD层上方形成第二沟槽光刻胶层,同时所述第一沟槽蚀刻子掩模保留在所述IMD层上方;
在所述第二沟槽光刻胶层上使用第二沟槽子图案执行第二沟槽曝光操作;以及
对所述第二沟槽光刻胶层进行显影以形成所述沟槽蚀刻掩模的第二沟槽蚀刻子掩模,使得所述互连区的边界由所述第一沟槽蚀刻子掩模和所述第二沟槽蚀刻子掩模的组合边缘形成;
在由所述互连区定义的区域中在所述IMD层中蚀刻多个互连沟槽;以及
使用互连金属填充所述互连沟槽以形成多个第一级互连件,使得每个所述双节点细长接触件直接连接到至少一个所述第一级互连件,
其中所述接触区的相对边缘由所述第一接触蚀刻子掩模和所述第二接触蚀刻子掩模形成。
14.根据权利要求13所述的方法,其进一步包括:
在所述形成接触蚀刻掩模之前在所述PMD层上方形成接触硬掩模层;以及
在所述形成接触蚀刻掩模之后并且在所述PMD层中蚀刻多个所述接触孔之前,在所述集成电路上执行接触硬掩模蚀刻工艺,以便从所述接触区中的所述接触硬掩模层上移除材料以形成接触硬掩模孔,由此使用所述接触硬掩模层作为模板执行在所述PMD层中蚀刻多个所述接触孔。
15.根据权利要求13所述的方法,其进一步包括:
在所述形成沟槽蚀刻掩模之前,在所述IMD层上方形成互连硬掩模层;以及
在所述形成沟槽蚀刻掩模之后并且在所述IMD层中蚀刻多个所述互连沟槽之前,在所述集成电路上执行互连硬掩模蚀刻工艺,以便从所述互连区中的所述互连硬掩模上移除材料以形成互连硬掩模孔,以便使用所述互连硬掩模层作为模板执行在所述IMD层中蚀刻多个所述互连沟槽。
16.根据权利要求13所述的方法,其中所述使用接触金属填充所述接触孔包括:
在所述接触孔中形成接触衬层金属;以及
在所述接触孔中形成接触填充金属。
17.根据权利要求13所述的方法,其中所述使用互连金属填充所述互连沟槽包括:
在所述互连沟槽中形成沟槽衬层金属;以及
在所述互连沟槽中形成沟槽填充金属。
18.根据权利要求13所述的方法,其中:
使用具有空间分辨率极限的光刻设备来执行所述第一接触曝光操作;并且
所述接触区的一些构件被分开小于所述空间分辨率极限。
19.根据权利要求13所述的方法,其中:
使用具有空间分辨率极限的光刻设备执行所述第一沟槽曝光操作;并且
所述互连区的一些构件被分开小于所述空间分辨率极限。
20.根据权利要求13所述的方法,其进一步包括通过包括以下步骤的工艺形成CMOS反相器:
形成所述场氧化物的元件以在所述衬底中提供反相器p型有源区,所述反相器p型有源区包括输出节点;
形成所述场氧化物的元件以在与所述反相器p型有源区相邻的衬底中提供反相器n型有源区,所述反相器n型有源区包括输出节点;
在所述衬底上方形成反相器MOS栅极,所述反相器MOS栅极横跨所述反相器p型有源区和所述反相器n型有源区;
形成所述接触蚀刻掩模以提供连接所述反相器p型有源区的所述输出节点和反相器n型有源区的所述输出节点的反相器输出节点细长接触件;以及
形成所述接触蚀刻掩模以便所述第一级互连件中的一个被直接连接到所述反相器输出节点细长接触件。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361916851P | 2013-12-17 | 2013-12-17 | |
US61/916,851 | 2013-12-17 | ||
CN201480068941.7A CN105830211A (zh) | 2013-12-17 | 2014-12-17 | 使用光刻-冷冻-光刻-蚀刻工艺的细长接触件 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201480068941.7A Division CN105830211A (zh) | 2013-12-17 | 2014-12-17 | 使用光刻-冷冻-光刻-蚀刻工艺的细长接触件 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN114093812A true CN114093812A (zh) | 2022-02-25 |
Family
ID=53369397
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111376507.3A Pending CN114093812A (zh) | 2013-12-17 | 2014-12-17 | 使用光刻-冷冻-光刻-蚀刻工艺的细长接触件 |
CN201480068941.7A Pending CN105830211A (zh) | 2013-12-17 | 2014-12-17 | 使用光刻-冷冻-光刻-蚀刻工艺的细长接触件 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201480068941.7A Pending CN105830211A (zh) | 2013-12-17 | 2014-12-17 | 使用光刻-冷冻-光刻-蚀刻工艺的细长接触件 |
Country Status (5)
Country | Link |
---|---|
US (3) | US9305848B2 (zh) |
EP (1) | EP3084823A4 (zh) |
JP (2) | JP6919131B2 (zh) |
CN (2) | CN114093812A (zh) |
WO (1) | WO2015095394A1 (zh) |
Families Citing this family (268)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9394608B2 (en) | 2009-04-06 | 2016-07-19 | Asm America, Inc. | Semiconductor processing reactor and components thereof |
US8802201B2 (en) | 2009-08-14 | 2014-08-12 | Asm America, Inc. | Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species |
US9312155B2 (en) | 2011-06-06 | 2016-04-12 | Asm Japan K.K. | High-throughput semiconductor-processing apparatus equipped with multiple dual-chamber modules |
US10854498B2 (en) | 2011-07-15 | 2020-12-01 | Asm Ip Holding B.V. | Wafer-supporting device and method for producing same |
US20130023129A1 (en) | 2011-07-20 | 2013-01-24 | Asm America, Inc. | Pressure transmitter for a semiconductor processing environment |
US9017481B1 (en) | 2011-10-28 | 2015-04-28 | Asm America, Inc. | Process feed management for semiconductor substrate processing |
US10714315B2 (en) | 2012-10-12 | 2020-07-14 | Asm Ip Holdings B.V. | Semiconductor reaction chamber showerhead |
US20160376700A1 (en) | 2013-02-01 | 2016-12-29 | Asm Ip Holding B.V. | System for treatment of deposition reactor |
JP6919131B2 (ja) * | 2013-12-17 | 2021-08-18 | テキサス インスツルメンツ インコーポレイテッド | リソ・フリーズ・リソ・エッチプロセスを用いる伸長コンタクト |
US10683571B2 (en) | 2014-02-25 | 2020-06-16 | Asm Ip Holding B.V. | Gas supply manifold and method of supplying gases to chamber using same |
US10167557B2 (en) | 2014-03-18 | 2019-01-01 | Asm Ip Holding B.V. | Gas distribution system, reactor including the system, and methods of using the same |
US11015245B2 (en) | 2014-03-19 | 2021-05-25 | Asm Ip Holding B.V. | Gas-phase reactor and system having exhaust plenum and components thereof |
US10858737B2 (en) | 2014-07-28 | 2020-12-08 | Asm Ip Holding B.V. | Showerhead assembly and components thereof |
US9890456B2 (en) | 2014-08-21 | 2018-02-13 | Asm Ip Holding B.V. | Method and system for in situ formation of gas-phase compounds |
US9657845B2 (en) | 2014-10-07 | 2017-05-23 | Asm Ip Holding B.V. | Variable conductance gas distribution apparatus and method |
US10941490B2 (en) | 2014-10-07 | 2021-03-09 | Asm Ip Holding B.V. | Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same |
US10276355B2 (en) | 2015-03-12 | 2019-04-30 | Asm Ip Holding B.V. | Multi-zone reactor, system including the reactor, and method of using the same |
US10458018B2 (en) | 2015-06-26 | 2019-10-29 | Asm Ip Holding B.V. | Structures including metal carbide material, devices including the structures, and methods of forming same |
US10600673B2 (en) | 2015-07-07 | 2020-03-24 | Asm Ip Holding B.V. | Magnetic susceptor to baseplate seal |
US9397049B1 (en) | 2015-08-10 | 2016-07-19 | International Business Machines Corporation | Gate tie-down enablement with inner spacer |
US10211308B2 (en) | 2015-10-21 | 2019-02-19 | Asm Ip Holding B.V. | NbMC layers |
US11139308B2 (en) | 2015-12-29 | 2021-10-05 | Asm Ip Holding B.V. | Atomic layer deposition of III-V compounds to form V-NAND devices |
US10529554B2 (en) | 2016-02-19 | 2020-01-07 | Asm Ip Holding B.V. | Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches |
EP3420584B1 (en) * | 2016-02-25 | 2020-12-23 | INTEL Corporation | Methods of fabricating conductive connectors having a ruthenium/aluminum-containing liner |
US10190213B2 (en) | 2016-04-21 | 2019-01-29 | Asm Ip Holding B.V. | Deposition of metal borides |
US10865475B2 (en) | 2016-04-21 | 2020-12-15 | Asm Ip Holding B.V. | Deposition of metal borides and silicides |
US10032628B2 (en) | 2016-05-02 | 2018-07-24 | Asm Ip Holding B.V. | Source/drain performance through conformal solid state doping |
US10367080B2 (en) | 2016-05-02 | 2019-07-30 | Asm Ip Holding B.V. | Method of forming a germanium oxynitride film |
US11453943B2 (en) * | 2016-05-25 | 2022-09-27 | Asm Ip Holding B.V. | Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor |
US9859151B1 (en) | 2016-07-08 | 2018-01-02 | Asm Ip Holding B.V. | Selective film deposition method to form air gaps |
US10612137B2 (en) | 2016-07-08 | 2020-04-07 | Asm Ip Holdings B.V. | Organic reactants for atomic layer deposition |
US10714385B2 (en) | 2016-07-19 | 2020-07-14 | Asm Ip Holding B.V. | Selective deposition of tungsten |
US9812320B1 (en) | 2016-07-28 | 2017-11-07 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
US9887082B1 (en) | 2016-07-28 | 2018-02-06 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
KR102532607B1 (ko) | 2016-07-28 | 2023-05-15 | 에이에스엠 아이피 홀딩 비.브이. | 기판 가공 장치 및 그 동작 방법 |
US10643826B2 (en) | 2016-10-26 | 2020-05-05 | Asm Ip Holdings B.V. | Methods for thermally calibrating reaction chambers |
US11532757B2 (en) | 2016-10-27 | 2022-12-20 | Asm Ip Holding B.V. | Deposition of charge trapping layers |
US10714350B2 (en) | 2016-11-01 | 2020-07-14 | ASM IP Holdings, B.V. | Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures |
US10229833B2 (en) | 2016-11-01 | 2019-03-12 | Asm Ip Holding B.V. | Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures |
US10643904B2 (en) | 2016-11-01 | 2020-05-05 | Asm Ip Holdings B.V. | Methods for forming a semiconductor device and related semiconductor device structures |
US10134757B2 (en) | 2016-11-07 | 2018-11-20 | Asm Ip Holding B.V. | Method of processing a substrate and a device manufactured by using the method |
KR102546317B1 (ko) | 2016-11-15 | 2023-06-21 | 에이에스엠 아이피 홀딩 비.브이. | 기체 공급 유닛 및 이를 포함하는 기판 처리 장치 |
KR20180068582A (ko) | 2016-12-14 | 2018-06-22 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 장치 |
US11447861B2 (en) | 2016-12-15 | 2022-09-20 | Asm Ip Holding B.V. | Sequential infiltration synthesis apparatus and a method of forming a patterned structure |
US11581186B2 (en) | 2016-12-15 | 2023-02-14 | Asm Ip Holding B.V. | Sequential infiltration synthesis apparatus |
KR20180070971A (ko) | 2016-12-19 | 2018-06-27 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 장치 |
US10269558B2 (en) | 2016-12-22 | 2019-04-23 | Asm Ip Holding B.V. | Method of forming a structure on a substrate |
US10867788B2 (en) | 2016-12-28 | 2020-12-15 | Asm Ip Holding B.V. | Method of forming a structure on a substrate |
US11390950B2 (en) | 2017-01-10 | 2022-07-19 | Asm Ip Holding B.V. | Reactor system and method to reduce residue buildup during a film deposition process |
US10655221B2 (en) | 2017-02-09 | 2020-05-19 | Asm Ip Holding B.V. | Method for depositing oxide film by thermal ALD and PEALD |
US10468261B2 (en) | 2017-02-15 | 2019-11-05 | Asm Ip Holding B.V. | Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures |
US10529563B2 (en) | 2017-03-29 | 2020-01-07 | Asm Ip Holdings B.V. | Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures |
USD876504S1 (en) | 2017-04-03 | 2020-02-25 | Asm Ip Holding B.V. | Exhaust flow control ring for semiconductor deposition apparatus |
KR102457289B1 (ko) | 2017-04-25 | 2022-10-21 | 에이에스엠 아이피 홀딩 비.브이. | 박막 증착 방법 및 반도체 장치의 제조 방법 |
US10892156B2 (en) | 2017-05-08 | 2021-01-12 | Asm Ip Holding B.V. | Methods for forming a silicon nitride film on a substrate and related semiconductor device structures |
US10770286B2 (en) | 2017-05-08 | 2020-09-08 | Asm Ip Holdings B.V. | Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures |
US11306395B2 (en) | 2017-06-28 | 2022-04-19 | Asm Ip Holding B.V. | Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus |
US10685834B2 (en) | 2017-07-05 | 2020-06-16 | Asm Ip Holdings B.V. | Methods for forming a silicon germanium tin layer and related semiconductor device structures |
KR20190009245A (ko) | 2017-07-18 | 2019-01-28 | 에이에스엠 아이피 홀딩 비.브이. | 반도체 소자 구조물 형성 방법 및 관련된 반도체 소자 구조물 |
US11374112B2 (en) | 2017-07-19 | 2022-06-28 | Asm Ip Holding B.V. | Method for depositing a group IV semiconductor and related semiconductor device structures |
US10541333B2 (en) | 2017-07-19 | 2020-01-21 | Asm Ip Holding B.V. | Method for depositing a group IV semiconductor and related semiconductor device structures |
US11018002B2 (en) | 2017-07-19 | 2021-05-25 | Asm Ip Holding B.V. | Method for selectively depositing a Group IV semiconductor and related semiconductor device structures |
US10590535B2 (en) | 2017-07-26 | 2020-03-17 | Asm Ip Holdings B.V. | Chemical treatment, deposition and/or infiltration apparatus and method for using the same |
US10692741B2 (en) | 2017-08-08 | 2020-06-23 | Asm Ip Holdings B.V. | Radiation shield |
US10770336B2 (en) | 2017-08-08 | 2020-09-08 | Asm Ip Holding B.V. | Substrate lift mechanism and reactor including same |
US11139191B2 (en) | 2017-08-09 | 2021-10-05 | Asm Ip Holding B.V. | Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith |
US11769682B2 (en) | 2017-08-09 | 2023-09-26 | Asm Ip Holding B.V. | Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith |
US10249524B2 (en) | 2017-08-09 | 2019-04-02 | Asm Ip Holding B.V. | Cassette holder assembly for a substrate cassette and holding member for use in such assembly |
USD900036S1 (en) | 2017-08-24 | 2020-10-27 | Asm Ip Holding B.V. | Heater electrical connector and adapter |
US10276428B2 (en) * | 2017-08-28 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of fabricating semiconductor package |
US11830730B2 (en) | 2017-08-29 | 2023-11-28 | Asm Ip Holding B.V. | Layer forming method and apparatus |
US11056344B2 (en) | 2017-08-30 | 2021-07-06 | Asm Ip Holding B.V. | Layer forming method |
US11295980B2 (en) | 2017-08-30 | 2022-04-05 | Asm Ip Holding B.V. | Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures |
KR102491945B1 (ko) | 2017-08-30 | 2023-01-26 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 장치 |
KR102401446B1 (ko) | 2017-08-31 | 2022-05-24 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 장치 |
KR102630301B1 (ko) | 2017-09-21 | 2024-01-29 | 에이에스엠 아이피 홀딩 비.브이. | 침투성 재료의 순차 침투 합성 방법 처리 및 이를 이용하여 형성된 구조물 및 장치 |
US10844484B2 (en) | 2017-09-22 | 2020-11-24 | Asm Ip Holding B.V. | Apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods |
US10658205B2 (en) | 2017-09-28 | 2020-05-19 | Asm Ip Holdings B.V. | Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber |
US10403504B2 (en) | 2017-10-05 | 2019-09-03 | Asm Ip Holding B.V. | Method for selectively depositing a metallic film on a substrate |
US10319588B2 (en) | 2017-10-10 | 2019-06-11 | Asm Ip Holding B.V. | Method for depositing a metal chalcogenide on a substrate by cyclical deposition |
US10923344B2 (en) | 2017-10-30 | 2021-02-16 | Asm Ip Holding B.V. | Methods for forming a semiconductor structure and related semiconductor structures |
KR102443047B1 (ko) | 2017-11-16 | 2022-09-14 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 장치 방법 및 그에 의해 제조된 장치 |
US10910262B2 (en) | 2017-11-16 | 2021-02-02 | Asm Ip Holding B.V. | Method of selectively depositing a capping layer structure on a semiconductor device structure |
US11022879B2 (en) | 2017-11-24 | 2021-06-01 | Asm Ip Holding B.V. | Method of forming an enhanced unexposed photoresist layer |
TWI791689B (zh) | 2017-11-27 | 2023-02-11 | 荷蘭商Asm智慧財產控股私人有限公司 | 包括潔淨迷你環境之裝置 |
WO2019103613A1 (en) | 2017-11-27 | 2019-05-31 | Asm Ip Holding B.V. | A storage device for storing wafer cassettes for use with a batch furnace |
US10872771B2 (en) | 2018-01-16 | 2020-12-22 | Asm Ip Holding B. V. | Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures |
US11482412B2 (en) | 2018-01-19 | 2022-10-25 | Asm Ip Holding B.V. | Method for depositing a gap-fill layer by plasma-assisted deposition |
TWI799494B (zh) | 2018-01-19 | 2023-04-21 | 荷蘭商Asm 智慧財產控股公司 | 沈積方法 |
USD903477S1 (en) | 2018-01-24 | 2020-12-01 | Asm Ip Holdings B.V. | Metal clamp |
US11018047B2 (en) | 2018-01-25 | 2021-05-25 | Asm Ip Holding B.V. | Hybrid lift pin |
USD880437S1 (en) | 2018-02-01 | 2020-04-07 | Asm Ip Holding B.V. | Gas supply plate for semiconductor manufacturing apparatus |
US11081345B2 (en) | 2018-02-06 | 2021-08-03 | Asm Ip Holding B.V. | Method of post-deposition treatment for silicon oxide film |
US10896820B2 (en) | 2018-02-14 | 2021-01-19 | Asm Ip Holding B.V. | Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process |
CN111699278B (zh) | 2018-02-14 | 2023-05-16 | Asm Ip私人控股有限公司 | 通过循环沉积工艺在衬底上沉积含钌膜的方法 |
US10731249B2 (en) | 2018-02-15 | 2020-08-04 | Asm Ip Holding B.V. | Method of forming a transition metal containing film on a substrate by a cyclical deposition process, a method for supplying a transition metal halide compound to a reaction chamber, and related vapor deposition apparatus |
US10658181B2 (en) | 2018-02-20 | 2020-05-19 | Asm Ip Holding B.V. | Method of spacer-defined direct patterning in semiconductor fabrication |
KR102636427B1 (ko) | 2018-02-20 | 2024-02-13 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 방법 및 장치 |
US10975470B2 (en) | 2018-02-23 | 2021-04-13 | Asm Ip Holding B.V. | Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment |
US11473195B2 (en) | 2018-03-01 | 2022-10-18 | Asm Ip Holding B.V. | Semiconductor processing apparatus and a method for processing a substrate |
US11629406B2 (en) | 2018-03-09 | 2023-04-18 | Asm Ip Holding B.V. | Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate |
US11114283B2 (en) | 2018-03-16 | 2021-09-07 | Asm Ip Holding B.V. | Reactor, system including the reactor, and methods of manufacturing and using same |
KR102646467B1 (ko) | 2018-03-27 | 2024-03-11 | 에이에스엠 아이피 홀딩 비.브이. | 기판 상에 전극을 형성하는 방법 및 전극을 포함하는 반도체 소자 구조 |
US11088002B2 (en) | 2018-03-29 | 2021-08-10 | Asm Ip Holding B.V. | Substrate rack and a substrate processing system and method |
US11230766B2 (en) | 2018-03-29 | 2022-01-25 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
KR102501472B1 (ko) | 2018-03-30 | 2023-02-20 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 방법 |
KR20190128558A (ko) | 2018-05-08 | 2019-11-18 | 에이에스엠 아이피 홀딩 비.브이. | 기판 상에 산화물 막을 주기적 증착 공정에 의해 증착하기 위한 방법 및 관련 소자 구조 |
TW202349473A (zh) | 2018-05-11 | 2023-12-16 | 荷蘭商Asm Ip私人控股有限公司 | 用於基板上形成摻雜金屬碳化物薄膜之方法及相關半導體元件結構 |
KR102596988B1 (ko) | 2018-05-28 | 2023-10-31 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 방법 및 그에 의해 제조된 장치 |
US11270899B2 (en) | 2018-06-04 | 2022-03-08 | Asm Ip Holding B.V. | Wafer handling chamber with moisture reduction |
US11718913B2 (en) | 2018-06-04 | 2023-08-08 | Asm Ip Holding B.V. | Gas distribution system and reactor system including same |
US11286562B2 (en) | 2018-06-08 | 2022-03-29 | Asm Ip Holding B.V. | Gas-phase chemical reactor and method of using same |
US10797133B2 (en) | 2018-06-21 | 2020-10-06 | Asm Ip Holding B.V. | Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures |
KR102568797B1 (ko) | 2018-06-21 | 2023-08-21 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 시스템 |
WO2020002995A1 (en) | 2018-06-27 | 2020-01-02 | Asm Ip Holding B.V. | Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material |
KR20210027265A (ko) | 2018-06-27 | 2021-03-10 | 에이에스엠 아이피 홀딩 비.브이. | 금속 함유 재료를 형성하기 위한 주기적 증착 방법 및 금속 함유 재료를 포함하는 막 및 구조체 |
KR20200002519A (ko) | 2018-06-29 | 2020-01-08 | 에이에스엠 아이피 홀딩 비.브이. | 박막 증착 방법 및 반도체 장치의 제조 방법 |
US10612136B2 (en) | 2018-06-29 | 2020-04-07 | ASM IP Holding, B.V. | Temperature-controlled flange and reactor system including same |
US10388513B1 (en) | 2018-07-03 | 2019-08-20 | Asm Ip Holding B.V. | Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition |
US10755922B2 (en) | 2018-07-03 | 2020-08-25 | Asm Ip Holding B.V. | Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition |
US10767789B2 (en) | 2018-07-16 | 2020-09-08 | Asm Ip Holding B.V. | Diaphragm valves, valve components, and methods for forming valve components |
US11053591B2 (en) | 2018-08-06 | 2021-07-06 | Asm Ip Holding B.V. | Multi-port gas injection system and reactor system including same |
US10883175B2 (en) | 2018-08-09 | 2021-01-05 | Asm Ip Holding B.V. | Vertical furnace for processing substrates and a liner for use therein |
US10829852B2 (en) | 2018-08-16 | 2020-11-10 | Asm Ip Holding B.V. | Gas distribution device for a wafer processing apparatus |
US11430674B2 (en) | 2018-08-22 | 2022-08-30 | Asm Ip Holding B.V. | Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods |
US11024523B2 (en) | 2018-09-11 | 2021-06-01 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
KR20200030162A (ko) | 2018-09-11 | 2020-03-20 | 에이에스엠 아이피 홀딩 비.브이. | 박막 증착 방법 |
US11049751B2 (en) | 2018-09-14 | 2021-06-29 | Asm Ip Holding B.V. | Cassette supply system to store and handle cassettes and processing apparatus equipped therewith |
CN110970344A (zh) | 2018-10-01 | 2020-04-07 | Asm Ip控股有限公司 | 衬底保持设备、包含所述设备的系统及其使用方法 |
US11232963B2 (en) | 2018-10-03 | 2022-01-25 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
KR102592699B1 (ko) | 2018-10-08 | 2023-10-23 | 에이에스엠 아이피 홀딩 비.브이. | 기판 지지 유닛 및 이를 포함하는 박막 증착 장치와 기판 처리 장치 |
US10847365B2 (en) | 2018-10-11 | 2020-11-24 | Asm Ip Holding B.V. | Method of forming conformal silicon carbide film by cyclic CVD |
US10811256B2 (en) | 2018-10-16 | 2020-10-20 | Asm Ip Holding B.V. | Method for etching a carbon-containing feature |
KR102546322B1 (ko) | 2018-10-19 | 2023-06-21 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 장치 및 기판 처리 방법 |
KR102605121B1 (ko) | 2018-10-19 | 2023-11-23 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 장치 및 기판 처리 방법 |
USD948463S1 (en) | 2018-10-24 | 2022-04-12 | Asm Ip Holding B.V. | Susceptor for semiconductor substrate supporting apparatus |
US11087997B2 (en) | 2018-10-31 | 2021-08-10 | Asm Ip Holding B.V. | Substrate processing apparatus for processing substrates |
KR20200051105A (ko) | 2018-11-02 | 2020-05-13 | 에이에스엠 아이피 홀딩 비.브이. | 기판 지지 유닛 및 이를 포함하는 기판 처리 장치 |
US11572620B2 (en) | 2018-11-06 | 2023-02-07 | Asm Ip Holding B.V. | Methods for selectively depositing an amorphous silicon film on a substrate |
US11031242B2 (en) | 2018-11-07 | 2021-06-08 | Asm Ip Holding B.V. | Methods for depositing a boron doped silicon germanium film |
US10847366B2 (en) | 2018-11-16 | 2020-11-24 | Asm Ip Holding B.V. | Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process |
US10818758B2 (en) | 2018-11-16 | 2020-10-27 | Asm Ip Holding B.V. | Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures |
US10559458B1 (en) | 2018-11-26 | 2020-02-11 | Asm Ip Holding B.V. | Method of forming oxynitride film |
US11217444B2 (en) | 2018-11-30 | 2022-01-04 | Asm Ip Holding B.V. | Method for forming an ultraviolet radiation responsive metal oxide-containing film |
KR102636428B1 (ko) | 2018-12-04 | 2024-02-13 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 장치를 세정하는 방법 |
US11158513B2 (en) | 2018-12-13 | 2021-10-26 | Asm Ip Holding B.V. | Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures |
JP2020096183A (ja) | 2018-12-14 | 2020-06-18 | エーエスエム・アイピー・ホールディング・ベー・フェー | 窒化ガリウムの選択的堆積を用いてデバイス構造体を形成する方法及びそのためのシステム |
TW202405220A (zh) | 2019-01-17 | 2024-02-01 | 荷蘭商Asm Ip 私人控股有限公司 | 藉由循環沈積製程於基板上形成含過渡金屬膜之方法 |
KR20200091543A (ko) | 2019-01-22 | 2020-07-31 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 장치 |
CN111524788B (zh) | 2019-02-01 | 2023-11-24 | Asm Ip私人控股有限公司 | 氧化硅的拓扑选择性膜形成的方法 |
KR20200102357A (ko) | 2019-02-20 | 2020-08-31 | 에이에스엠 아이피 홀딩 비.브이. | 3-d nand 응용의 플러그 충진체 증착용 장치 및 방법 |
KR102638425B1 (ko) | 2019-02-20 | 2024-02-21 | 에이에스엠 아이피 홀딩 비.브이. | 기판 표면 내에 형성된 오목부를 충진하기 위한 방법 및 장치 |
JP2020136677A (ja) | 2019-02-20 | 2020-08-31 | エーエスエム・アイピー・ホールディング・ベー・フェー | 基材表面内に形成された凹部を充填するための周期的堆積方法および装置 |
KR102626263B1 (ko) | 2019-02-20 | 2024-01-16 | 에이에스엠 아이피 홀딩 비.브이. | 처리 단계를 포함하는 주기적 증착 방법 및 이를 위한 장치 |
JP2020133004A (ja) | 2019-02-22 | 2020-08-31 | エーエスエム・アイピー・ホールディング・ベー・フェー | 基材を処理するための基材処理装置および方法 |
KR20200108248A (ko) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | SiOCN 층을 포함한 구조체 및 이의 형성 방법 |
KR20200108242A (ko) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | 실리콘 질화물 층을 선택적으로 증착하는 방법, 및 선택적으로 증착된 실리콘 질화물 층을 포함하는 구조체 |
KR20200108243A (ko) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | SiOC 층을 포함한 구조체 및 이의 형성 방법 |
JP2020167398A (ja) | 2019-03-28 | 2020-10-08 | エーエスエム・アイピー・ホールディング・ベー・フェー | ドアオープナーおよびドアオープナーが提供される基材処理装置 |
KR20200116855A (ko) | 2019-04-01 | 2020-10-13 | 에이에스엠 아이피 홀딩 비.브이. | 반도체 소자를 제조하는 방법 |
US11447864B2 (en) | 2019-04-19 | 2022-09-20 | Asm Ip Holding B.V. | Layer forming method and apparatus |
KR20200125453A (ko) | 2019-04-24 | 2020-11-04 | 에이에스엠 아이피 홀딩 비.브이. | 기상 반응기 시스템 및 이를 사용하는 방법 |
KR20200130121A (ko) | 2019-05-07 | 2020-11-18 | 에이에스엠 아이피 홀딩 비.브이. | 딥 튜브가 있는 화학물질 공급원 용기 |
KR20200130118A (ko) | 2019-05-07 | 2020-11-18 | 에이에스엠 아이피 홀딩 비.브이. | 비정질 탄소 중합체 막을 개질하는 방법 |
KR20200130652A (ko) | 2019-05-10 | 2020-11-19 | 에이에스엠 아이피 홀딩 비.브이. | 표면 상에 재료를 증착하는 방법 및 본 방법에 따라 형성된 구조 |
JP2020188254A (ja) | 2019-05-16 | 2020-11-19 | エーエスエム アイピー ホールディング ビー.ブイ. | ウェハボートハンドリング装置、縦型バッチ炉および方法 |
JP2020188255A (ja) | 2019-05-16 | 2020-11-19 | エーエスエム アイピー ホールディング ビー.ブイ. | ウェハボートハンドリング装置、縦型バッチ炉および方法 |
USD975665S1 (en) | 2019-05-17 | 2023-01-17 | Asm Ip Holding B.V. | Susceptor shaft |
USD947913S1 (en) | 2019-05-17 | 2022-04-05 | Asm Ip Holding B.V. | Susceptor shaft |
TWI714093B (zh) * | 2019-05-21 | 2020-12-21 | 友達光電股份有限公司 | 陣列基板 |
USD935572S1 (en) | 2019-05-24 | 2021-11-09 | Asm Ip Holding B.V. | Gas channel plate |
USD922229S1 (en) | 2019-06-05 | 2021-06-15 | Asm Ip Holding B.V. | Device for controlling a temperature of a gas supply unit |
KR20200141002A (ko) | 2019-06-06 | 2020-12-17 | 에이에스엠 아이피 홀딩 비.브이. | 배기 가스 분석을 포함한 기상 반응기 시스템을 사용하는 방법 |
KR20200143254A (ko) | 2019-06-11 | 2020-12-23 | 에이에스엠 아이피 홀딩 비.브이. | 개질 가스를 사용하여 전자 구조를 형성하는 방법, 상기 방법을 수행하기 위한 시스템, 및 상기 방법을 사용하여 형성되는 구조 |
USD944946S1 (en) | 2019-06-14 | 2022-03-01 | Asm Ip Holding B.V. | Shower plate |
USD931978S1 (en) | 2019-06-27 | 2021-09-28 | Asm Ip Holding B.V. | Showerhead vacuum transport |
KR20210005515A (ko) | 2019-07-03 | 2021-01-14 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 장치용 온도 제어 조립체 및 이를 사용하는 방법 |
JP2021015791A (ja) | 2019-07-09 | 2021-02-12 | エーエスエム アイピー ホールディング ビー.ブイ. | 同軸導波管を用いたプラズマ装置、基板処理方法 |
CN112216646A (zh) | 2019-07-10 | 2021-01-12 | Asm Ip私人控股有限公司 | 基板支撑组件及包括其的基板处理装置 |
KR20210010307A (ko) | 2019-07-16 | 2021-01-27 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 장치 |
KR20210010820A (ko) | 2019-07-17 | 2021-01-28 | 에이에스엠 아이피 홀딩 비.브이. | 실리콘 게르마늄 구조를 형성하는 방법 |
KR20210010816A (ko) | 2019-07-17 | 2021-01-28 | 에이에스엠 아이피 홀딩 비.브이. | 라디칼 보조 점화 플라즈마 시스템 및 방법 |
US11643724B2 (en) | 2019-07-18 | 2023-05-09 | Asm Ip Holding B.V. | Method of forming structures using a neutral beam |
JP2021019198A (ja) | 2019-07-19 | 2021-02-15 | エーエスエム・アイピー・ホールディング・ベー・フェー | トポロジー制御されたアモルファスカーボンポリマー膜の形成方法 |
TW202113936A (zh) | 2019-07-29 | 2021-04-01 | 荷蘭商Asm Ip私人控股有限公司 | 用於利用n型摻雜物及/或替代摻雜物選擇性沉積以達成高摻雜物併入之方法 |
CN112309900A (zh) | 2019-07-30 | 2021-02-02 | Asm Ip私人控股有限公司 | 基板处理设备 |
CN112309899A (zh) | 2019-07-30 | 2021-02-02 | Asm Ip私人控股有限公司 | 基板处理设备 |
US11587814B2 (en) | 2019-07-31 | 2023-02-21 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
US11587815B2 (en) | 2019-07-31 | 2023-02-21 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
US11227782B2 (en) | 2019-07-31 | 2022-01-18 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
KR20210018759A (ko) | 2019-08-05 | 2021-02-18 | 에이에스엠 아이피 홀딩 비.브이. | 화학물질 공급원 용기를 위한 액체 레벨 센서 |
USD965524S1 (en) | 2019-08-19 | 2022-10-04 | Asm Ip Holding B.V. | Susceptor support |
USD965044S1 (en) | 2019-08-19 | 2022-09-27 | Asm Ip Holding B.V. | Susceptor shaft |
JP2021031769A (ja) | 2019-08-21 | 2021-03-01 | エーエスエム アイピー ホールディング ビー.ブイ. | 成膜原料混合ガス生成装置及び成膜装置 |
USD949319S1 (en) | 2019-08-22 | 2022-04-19 | Asm Ip Holding B.V. | Exhaust duct |
USD940837S1 (en) | 2019-08-22 | 2022-01-11 | Asm Ip Holding B.V. | Electrode |
USD979506S1 (en) | 2019-08-22 | 2023-02-28 | Asm Ip Holding B.V. | Insulator |
USD930782S1 (en) | 2019-08-22 | 2021-09-14 | Asm Ip Holding B.V. | Gas distributor |
KR20210024423A (ko) | 2019-08-22 | 2021-03-05 | 에이에스엠 아이피 홀딩 비.브이. | 홀을 구비한 구조체를 형성하기 위한 방법 |
US11286558B2 (en) | 2019-08-23 | 2022-03-29 | Asm Ip Holding B.V. | Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film |
KR20210024420A (ko) | 2019-08-23 | 2021-03-05 | 에이에스엠 아이피 홀딩 비.브이. | 비스(디에틸아미노)실란을 사용하여 peald에 의해 개선된 품질을 갖는 실리콘 산화물 막을 증착하기 위한 방법 |
KR20210029090A (ko) | 2019-09-04 | 2021-03-15 | 에이에스엠 아이피 홀딩 비.브이. | 희생 캡핑 층을 이용한 선택적 증착 방법 |
KR20210029663A (ko) | 2019-09-05 | 2021-03-16 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 장치 |
US11562901B2 (en) | 2019-09-25 | 2023-01-24 | Asm Ip Holding B.V. | Substrate processing method |
CN112593212B (zh) | 2019-10-02 | 2023-12-22 | Asm Ip私人控股有限公司 | 通过循环等离子体增强沉积工艺形成拓扑选择性氧化硅膜的方法 |
TW202129060A (zh) | 2019-10-08 | 2021-08-01 | 荷蘭商Asm Ip控股公司 | 基板處理裝置、及基板處理方法 |
TW202115273A (zh) | 2019-10-10 | 2021-04-16 | 荷蘭商Asm Ip私人控股有限公司 | 形成光阻底層之方法及包括光阻底層之結構 |
KR20210045930A (ko) | 2019-10-16 | 2021-04-27 | 에이에스엠 아이피 홀딩 비.브이. | 실리콘 산화물의 토폴로지-선택적 막의 형성 방법 |
US11637014B2 (en) | 2019-10-17 | 2023-04-25 | Asm Ip Holding B.V. | Methods for selective deposition of doped semiconductor material |
KR20210047808A (ko) | 2019-10-21 | 2021-04-30 | 에이에스엠 아이피 홀딩 비.브이. | 막을 선택적으로 에칭하기 위한 장치 및 방법 |
KR20210050453A (ko) | 2019-10-25 | 2021-05-07 | 에이에스엠 아이피 홀딩 비.브이. | 기판 표면 상의 갭 피처를 충진하는 방법 및 이와 관련된 반도체 소자 구조 |
US11646205B2 (en) | 2019-10-29 | 2023-05-09 | Asm Ip Holding B.V. | Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same |
KR20210054983A (ko) | 2019-11-05 | 2021-05-14 | 에이에스엠 아이피 홀딩 비.브이. | 도핑된 반도체 층을 갖는 구조체 및 이를 형성하기 위한 방법 및 시스템 |
US11501968B2 (en) | 2019-11-15 | 2022-11-15 | Asm Ip Holding B.V. | Method for providing a semiconductor device with silicon filled gaps |
KR20210062561A (ko) | 2019-11-20 | 2021-05-31 | 에이에스엠 아이피 홀딩 비.브이. | 기판의 표면 상에 탄소 함유 물질을 증착하는 방법, 상기 방법을 사용하여 형성된 구조물, 및 상기 구조물을 형성하기 위한 시스템 |
KR20210065848A (ko) | 2019-11-26 | 2021-06-04 | 에이에스엠 아이피 홀딩 비.브이. | 제1 유전체 표면과 제2 금속성 표면을 포함한 기판 상에 타겟 막을 선택적으로 형성하기 위한 방법 |
CN112951697A (zh) | 2019-11-26 | 2021-06-11 | Asm Ip私人控股有限公司 | 基板处理设备 |
CN112885692A (zh) | 2019-11-29 | 2021-06-01 | Asm Ip私人控股有限公司 | 基板处理设备 |
CN112885693A (zh) | 2019-11-29 | 2021-06-01 | Asm Ip私人控股有限公司 | 基板处理设备 |
JP2021090042A (ja) | 2019-12-02 | 2021-06-10 | エーエスエム アイピー ホールディング ビー.ブイ. | 基板処理装置、基板処理方法 |
KR20210070898A (ko) | 2019-12-04 | 2021-06-15 | 에이에스엠 아이피 홀딩 비.브이. | 기판 처리 장치 |
TW202125596A (zh) | 2019-12-17 | 2021-07-01 | 荷蘭商Asm Ip私人控股有限公司 | 形成氮化釩層之方法以及包括該氮化釩層之結構 |
KR20210080214A (ko) | 2019-12-19 | 2021-06-30 | 에이에스엠 아이피 홀딩 비.브이. | 기판 상의 갭 피처를 충진하는 방법 및 이와 관련된 반도체 소자 구조 |
TW202140135A (zh) | 2020-01-06 | 2021-11-01 | 荷蘭商Asm Ip私人控股有限公司 | 氣體供應總成以及閥板總成 |
US11993847B2 (en) | 2020-01-08 | 2024-05-28 | Asm Ip Holding B.V. | Injector |
KR20210095050A (ko) | 2020-01-20 | 2021-07-30 | 에이에스엠 아이피 홀딩 비.브이. | 박막 형성 방법 및 박막 표면 개질 방법 |
TW202130846A (zh) | 2020-02-03 | 2021-08-16 | 荷蘭商Asm Ip私人控股有限公司 | 形成包括釩或銦層的結構之方法 |
KR20210100010A (ko) | 2020-02-04 | 2021-08-13 | 에이에스엠 아이피 홀딩 비.브이. | 대형 물품의 투과율 측정을 위한 방법 및 장치 |
US11776846B2 (en) | 2020-02-07 | 2023-10-03 | Asm Ip Holding B.V. | Methods for depositing gap filling fluids and related systems and devices |
TW202146715A (zh) | 2020-02-17 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | 用於生長磷摻雜矽層之方法及其系統 |
TW202203344A (zh) | 2020-02-28 | 2022-01-16 | 荷蘭商Asm Ip控股公司 | 專用於零件清潔的系統 |
KR20210116240A (ko) | 2020-03-11 | 2021-09-27 | 에이에스엠 아이피 홀딩 비.브이. | 조절성 접합부를 갖는 기판 핸들링 장치 |
KR20210116249A (ko) | 2020-03-11 | 2021-09-27 | 에이에스엠 아이피 홀딩 비.브이. | 록아웃 태그아웃 어셈블리 및 시스템 그리고 이의 사용 방법 |
KR20210117157A (ko) | 2020-03-12 | 2021-09-28 | 에이에스엠 아이피 홀딩 비.브이. | 타겟 토폴로지 프로파일을 갖는 층 구조를 제조하기 위한 방법 |
KR20210124042A (ko) | 2020-04-02 | 2021-10-14 | 에이에스엠 아이피 홀딩 비.브이. | 박막 형성 방법 |
TW202146689A (zh) | 2020-04-03 | 2021-12-16 | 荷蘭商Asm Ip控股公司 | 阻障層形成方法及半導體裝置的製造方法 |
TW202145344A (zh) | 2020-04-08 | 2021-12-01 | 荷蘭商Asm Ip私人控股有限公司 | 用於選擇性蝕刻氧化矽膜之設備及方法 |
US11821078B2 (en) | 2020-04-15 | 2023-11-21 | Asm Ip Holding B.V. | Method for forming precoat film and method for forming silicon-containing film |
US11996289B2 (en) | 2020-04-16 | 2024-05-28 | Asm Ip Holding B.V. | Methods of forming structures including silicon germanium and silicon layers, devices formed using the methods, and systems for performing the methods |
TW202146831A (zh) | 2020-04-24 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | 垂直批式熔爐總成、及用於冷卻垂直批式熔爐之方法 |
KR20210132600A (ko) | 2020-04-24 | 2021-11-04 | 에이에스엠 아이피 홀딩 비.브이. | 바나듐, 질소 및 추가 원소를 포함한 층을 증착하기 위한 방법 및 시스템 |
CN113555279A (zh) | 2020-04-24 | 2021-10-26 | Asm Ip私人控股有限公司 | 形成含氮化钒的层的方法及包含其的结构 |
KR20210134226A (ko) | 2020-04-29 | 2021-11-09 | 에이에스엠 아이피 홀딩 비.브이. | 고체 소스 전구체 용기 |
KR20210134869A (ko) | 2020-05-01 | 2021-11-11 | 에이에스엠 아이피 홀딩 비.브이. | Foup 핸들러를 이용한 foup의 빠른 교환 |
KR20210141379A (ko) | 2020-05-13 | 2021-11-23 | 에이에스엠 아이피 홀딩 비.브이. | 반응기 시스템용 레이저 정렬 고정구 |
TW202147383A (zh) | 2020-05-19 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | 基材處理設備 |
KR20210145078A (ko) | 2020-05-21 | 2021-12-01 | 에이에스엠 아이피 홀딩 비.브이. | 다수의 탄소 층을 포함한 구조체 및 이를 형성하고 사용하는 방법 |
KR20210145080A (ko) | 2020-05-22 | 2021-12-01 | 에이에스엠 아이피 홀딩 비.브이. | 과산화수소를 사용하여 박막을 증착하기 위한 장치 |
TW202201602A (zh) | 2020-05-29 | 2022-01-01 | 荷蘭商Asm Ip私人控股有限公司 | 基板處理方法 |
TW202218133A (zh) | 2020-06-24 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | 形成含矽層之方法 |
TW202217953A (zh) | 2020-06-30 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | 基板處理方法 |
TW202219628A (zh) | 2020-07-17 | 2022-05-16 | 荷蘭商Asm Ip私人控股有限公司 | 用於光微影之結構與方法 |
TW202204662A (zh) | 2020-07-20 | 2022-02-01 | 荷蘭商Asm Ip私人控股有限公司 | 用於沉積鉬層之方法及系統 |
TW202212623A (zh) | 2020-08-26 | 2022-04-01 | 荷蘭商Asm Ip私人控股有限公司 | 形成金屬氧化矽層及金屬氮氧化矽層的方法、半導體結構、及系統 |
USD990534S1 (en) | 2020-09-11 | 2023-06-27 | Asm Ip Holding B.V. | Weighted lift pin |
USD1012873S1 (en) | 2020-09-24 | 2024-01-30 | Asm Ip Holding B.V. | Electrode for semiconductor processing apparatus |
TW202229613A (zh) | 2020-10-14 | 2022-08-01 | 荷蘭商Asm Ip私人控股有限公司 | 於階梯式結構上沉積材料的方法 |
KR20220053482A (ko) | 2020-10-22 | 2022-04-29 | 에이에스엠 아이피 홀딩 비.브이. | 바나듐 금속을 증착하는 방법, 구조체, 소자 및 증착 어셈블리 |
TW202223136A (zh) | 2020-10-28 | 2022-06-16 | 荷蘭商Asm Ip私人控股有限公司 | 用於在基板上形成層之方法、及半導體處理系統 |
TW202235675A (zh) | 2020-11-30 | 2022-09-16 | 荷蘭商Asm Ip私人控股有限公司 | 注入器、及基板處理設備 |
CN114639631A (zh) | 2020-12-16 | 2022-06-17 | Asm Ip私人控股有限公司 | 跳动和摆动测量固定装置 |
TW202231903A (zh) | 2020-12-22 | 2022-08-16 | 荷蘭商Asm Ip私人控股有限公司 | 過渡金屬沉積方法、過渡金屬層、用於沉積過渡金屬於基板上的沉積總成 |
USD980814S1 (en) | 2021-05-11 | 2023-03-14 | Asm Ip Holding B.V. | Gas distributor for substrate processing apparatus |
USD1023959S1 (en) | 2021-05-11 | 2024-04-23 | Asm Ip Holding B.V. | Electrode for substrate processing apparatus |
USD981973S1 (en) | 2021-05-11 | 2023-03-28 | Asm Ip Holding B.V. | Reactor wall for substrate processing apparatus |
USD980813S1 (en) | 2021-05-11 | 2023-03-14 | Asm Ip Holding B.V. | Gas flow control plate for substrate processing apparatus |
US20220367253A1 (en) * | 2021-05-13 | 2022-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and methods of forming the same |
USD990441S1 (en) | 2021-09-07 | 2023-06-27 | Asm Ip Holding B.V. | Gas flow control plate |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US727131A (en) * | 1902-09-06 | 1903-05-05 | Frank Haack | Anchor for check-row wires. |
US6017813A (en) * | 1998-01-12 | 2000-01-25 | Vanguard International Semiconductor Corporation | Method for fabricating a damascene landing pad |
JP2001319928A (ja) * | 2000-05-08 | 2001-11-16 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP3914452B2 (ja) * | 2001-08-07 | 2007-05-16 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
JP4121356B2 (ja) * | 2002-10-31 | 2008-07-23 | 富士通株式会社 | 半導体装置 |
TW200425298A (en) * | 2003-05-01 | 2004-11-16 | Nanya Technology Corp | Fabrication method for a damascene bitline contact |
JP2005072185A (ja) * | 2003-08-22 | 2005-03-17 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP5096669B2 (ja) * | 2005-07-06 | 2012-12-12 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
CN101512753B (zh) * | 2006-09-04 | 2011-06-15 | Nxp股份有限公司 | 半导体器件上自组装的纳米线型互连的制作 |
US8148052B2 (en) * | 2006-11-14 | 2012-04-03 | Nxp B.V. | Double patterning for lithography to increase feature spatial density |
US11133350B2 (en) * | 2007-08-29 | 2021-09-28 | Texas Instruments Incorporated | Integrated circuit with thermoelectric power supply |
US7981592B2 (en) * | 2008-04-11 | 2011-07-19 | Sandisk 3D Llc | Double patterning method |
US20100187611A1 (en) * | 2009-01-27 | 2010-07-29 | Roberto Schiwon | Contacts in Semiconductor Devices |
US10163911B2 (en) * | 2009-06-05 | 2018-12-25 | Texas Instruments Incorporated | SRAM cell with T-shaped contact |
US8304172B2 (en) * | 2009-11-12 | 2012-11-06 | Advanced Micro Devices, Inc. | Semiconductor device fabrication using a multiple exposure and block mask approach to reduce design rule violations |
US8446175B2 (en) * | 2009-12-23 | 2013-05-21 | Texas Instruments Incorporated | Logic-cell-compatible decoupling capacitor |
JP2011049601A (ja) * | 2010-12-03 | 2011-03-10 | Renesas Electronics Corp | 半導体装置 |
KR20130006736A (ko) * | 2011-02-28 | 2013-01-18 | 에스케이하이닉스 주식회사 | 반도체 소자의 콘택홀 형성용 마스크 제조방법 |
US8987831B2 (en) * | 2012-01-12 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM cells and arrays |
JP6919131B2 (ja) * | 2013-12-17 | 2021-08-18 | テキサス インスツルメンツ インコーポレイテッド | リソ・フリーズ・リソ・エッチプロセスを用いる伸長コンタクト |
US9312170B2 (en) * | 2013-12-17 | 2016-04-12 | Texas Instruments Incorporated | Metal on elongated contacts |
-
2014
- 2014-12-17 JP JP2016541067A patent/JP6919131B2/ja active Active
- 2014-12-17 WO PCT/US2014/070954 patent/WO2015095394A1/en active Application Filing
- 2014-12-17 US US14/572,891 patent/US9305848B2/en active Active
- 2014-12-17 CN CN202111376507.3A patent/CN114093812A/zh active Pending
- 2014-12-17 CN CN201480068941.7A patent/CN105830211A/zh active Pending
- 2014-12-17 EP EP14872482.6A patent/EP3084823A4/en not_active Withdrawn
-
2016
- 2016-03-03 US US15/059,732 patent/US9620419B2/en active Active
-
2017
- 2017-03-02 US US15/447,873 patent/US10043714B2/en active Active
-
2020
- 2020-12-21 JP JP2020210909A patent/JP7137045B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2017500744A (ja) | 2017-01-05 |
EP3084823A1 (en) | 2016-10-26 |
WO2015095394A1 (en) | 2015-06-25 |
US20150170975A1 (en) | 2015-06-18 |
EP3084823A4 (en) | 2017-08-02 |
JP7137045B2 (ja) | 2022-09-14 |
JP2021061419A (ja) | 2021-04-15 |
CN105830211A (zh) | 2016-08-03 |
US20170178966A1 (en) | 2017-06-22 |
US10043714B2 (en) | 2018-08-07 |
US9305848B2 (en) | 2016-04-05 |
JP6919131B2 (ja) | 2021-08-18 |
US20160190016A1 (en) | 2016-06-30 |
US9620419B2 (en) | 2017-04-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7137045B2 (ja) | リソ・フリーズ・リソ・エッチプロセスを用いる伸長コンタクト | |
US9099530B2 (en) | Methods of patterning small via pitch dimensions | |
US20210265272A1 (en) | Method of Forming an Interconnect Structure Having an Air Gap and Structure Thereof | |
KR101711264B1 (ko) | 반도체 디바이스용 상호 접속 구조체를 형성하는 방법 | |
US10854542B2 (en) | Via structure and methods thereof | |
US9543193B2 (en) | Non-hierarchical metal layers for integrated circuits | |
US8404581B2 (en) | Method of forming an interconnect of a semiconductor device | |
JP2004186697A (ja) | 単一波状形状バイアあるいは溝空洞の形成方法および二重波状形状バイア空洞の形成方法 | |
TWI595597B (zh) | 形成金屬內連接之方法 | |
KR20190100975A (ko) | 상호 접속 구조체 및 그 형성 방법 | |
US8841214B2 (en) | Dual damascene process | |
US11158536B2 (en) | Patterning line cuts before line patterning using sacrificial fill material | |
US9312170B2 (en) | Metal on elongated contacts | |
US20230377956A1 (en) | Method of forming an interconect structure of a semiconductor device | |
KR100835414B1 (ko) | 반도체 소자의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |