CN113611736A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN113611736A
CN113611736A CN202010472945.9A CN202010472945A CN113611736A CN 113611736 A CN113611736 A CN 113611736A CN 202010472945 A CN202010472945 A CN 202010472945A CN 113611736 A CN113611736 A CN 113611736A
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epitaxial layer
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semiconductor device
protrusion
layer
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CN113611736B (zh
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黄世贤
刘昇旭
谈文毅
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United Semi Integrated Circuit Manufacture Xiamen Co ltd
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United Semi Integrated Circuit Manufacture Xiamen Co ltd
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Abstract

本发明公开一种半导体元件及其制作方法，其中该制作半导体元件的方法为先形成一栅极结构于基底上，然后形成一间隙壁于栅极结构旁，形成凹槽于间隙壁旁，修整部分间隙壁，再形成一外延层于凹槽内。半导体元件又包含第一突起部设于外延层一侧以及第二突起部设于外延层另一侧，其中第一突起部包含一V形设于间隙壁下方且V形的夹角大于30度以及小于90度。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种于形成外延层前利用蚀刻制作工艺修整间隙壁的方法。
背景技术
为了能增加半导体结构的载流子迁移率，可以选择对于栅极通道施加压缩应力或是伸张应力。举例来说，若需要施加的是压缩应力，现有技术常利用选择性外延成长(selective epitaxial growth,SEG)技术于一硅基底内形成晶格排列与该硅基底相同的外延结构，例如硅锗(silicon germanium,SiGe)外延结构。利用硅锗外延结构的晶格常数(lattice constant)大于该硅基底晶格的特点，对P型金属氧化物半导体晶体管的通道区产生应力，增加通道区的载流子迁移率(carrier mobility)，并用于增加金属氧化物半导体晶体管的速度。反之，若是N型半导体晶体管则可选择于硅基底内形成硅碳(siliconcarbide,SiC) 外延结构，对栅极通道区产生伸张应力。
现今以外延成长方式形成具有外延层的MOS晶体管过程中通常会先于成长外延层之前利用轻掺杂离子注入制作工艺于间隙壁两侧的基底内形成轻掺杂漏极，然而以离子注入制作工艺形成轻掺杂漏极的作法不容易精准控制轻掺杂漏极的浓度分布并容易造成漏电及短通道效应(short channel effect, SCE)。因此，如何改良现有制作工艺技术以解决现有瓶颈即为现今一重要课题。
发明内容
本发明一实施例揭露一种制作半导体元件的方法，其主要先形成一栅极结构于基底上，然后形成一间隙壁于栅极结构旁，形成凹槽于间隙壁旁，修整部分间隙壁，再形成一外延层于凹槽内。半导体元件又包含第一突起部设于外延层一侧以及第二突起部设于外延层另一侧，其中第一突起部包含一V 形设于间隙壁下方且V形的夹角大于30度以及小于90度。
本发明另一实施例揭露一种半导体元件，其主要包含一栅极结构设于基底上、一间隙壁设于栅极结构旁以及一外延层设于间隙壁旁，其中外延层包含一突起部具有一大于30度的夹角位于该间隙壁下方。
本发明又一实施例揭露一种半导体元件，其主要包含一栅极结构设于基底上、一间隙壁设于栅极结构旁、第一外延层设于间隙壁旁、第二外延层设于第一外延层上以及第三外延层设于第二外延层上，其中第二外延层包含V 形。
附图说明
图1至图6为本发明一实施例制作一半导体元件的方法示意图；
图7为本发明一实施例的一半导体元件的结构示意图。
主要元件符号说明
12:基底
14:栅极结构
16:栅极结构
18:栅极介电层
20:栅极材料层
22:硬掩模
24:轻掺杂漏极
26:袋状掺杂区
28:间隙壁
30:间隙壁
32:凹槽
34:孔洞
36:凹槽
38:缓冲层
40:外延层
42:第一突起部
44:第二突起部
46:源极/漏极区域
48:遮盖层
54:层间介电层
56:介质层
58:高介电常数介电层
60:功函数金属层
62:低阻抗金属层
64:金属栅极
66:金属栅极
68:硬掩模
70:接触插塞
72:第一外延层
74:第二外延层
76:第三外延层
具体实施方式
请参照图1至图6，图1至图6为本发明一实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，然后于基底12上形成栅极结构14、16。在本实施例中，形成栅极结构14、16的方式较佳依序形成一栅极介电层、一栅极材料层以及一硬掩模于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分硬掩模、部分栅极材料层以及部分栅极介电层，然后剥除图案化光致抗蚀剂，以于基底12上形成至少由图案化的栅极介电层18、图案化的栅极材料层20以及图案化的硬掩模22所构成的栅极结构14、16，其中栅极介电层18与栅极材料层20较佳构成栅极电极。需注意的是，为了凸显后续于栅极结构14、16之间形成外延层的相关步骤，本实施例主要以基底12上形成两个晶体管为例并仅绘示两个晶体管的部分结构与两个栅极结构14、16之间的区域。
在本实施例中，基底12例如是硅基底、外延硅基底、碳化硅基底或硅覆绝缘(silicon-on-insulator,SOI)基底等的半导体基底，但不以此为限。栅极介电层18可包含二氧化硅(SiO2)、氮化硅(SiN)或高介电常数(high dielectric constant,high-k)材料；栅极材料层20可包含金属材料、多晶硅或金属硅化物(silicide)等导电材料；硬掩模22可选自由氧化硅、氮化硅、碳化硅(SiC)以及氮氧化硅(SiON)所构成的群组，但不局限于此。
此外，在一实施例中，还可选择预先在基底12中形成多个掺杂井(未绘示)或多个作为电性隔离之用的浅沟槽隔离(shallow trench isolation,STI)。并且，本实施例虽以平面型晶体管为例，但在其他变化实施例中，本发明的半导体制作工艺也可应用于非平面晶体管，例如是鳍状结构场效晶体管 (Fin-FET)，此时，图1所标示的基底12即相对应代表为形成于一基底12上的鳍状结构。
然后形成至少一间隙壁于栅极结构14、16侧壁，再进行一离子注入制作工艺例如利用斜角离子注入方式将掺质注入栅极结构14、16两侧的基底 12内形成袋状掺杂区(pocket implant)26。在本实施例中，间隙壁较佳为一复合式间隙壁，其可细部包含一间隙壁28设于栅极结构14、16或栅极电极侧壁以及间隙壁30设于间隙壁28侧壁，其中内侧的间隙壁28与外侧的间隙壁30均较佳包含I形剖面。在本实施例中，内侧的间隙壁28可与外侧的间隙壁30包含相同或不同材料且间隙壁28、30均可包含氧化硅、氮化硅、氮氧化硅或氮碳化硅。另外袋状掺杂区26较佳与所制备的金属氧化物半导体元件包含不同导电型式。以本实施例制备P型金属氧化物半导体晶体管为例，袋状掺杂区26较佳包含N型掺质，但不局限于此。
接着如图2所示，进行一第一蚀刻制作工艺以于间隙壁30两侧的基底 12中形成初始凹槽32。在本实施例中，第一蚀刻制作工艺较佳包含干蚀刻制作工艺且第一蚀刻制作工艺又可细部包含三阶段蚀刻制作工艺，其中第一阶段蚀刻制作工艺包含进行一垂直方向蚀刻制作工艺去除部分基底12，第二阶段蚀刻制作工艺包含进行一水平方向蚀刻制作工艺去除部分基底12，而第三阶段蚀刻制作工艺则包含进行另一垂直方向蚀刻制作工艺去除部分基底 12并形成凹槽32。
从细部来看，第一阶段蚀刻制作工艺较佳包含溴化氢(hydrogen bromide, HBr)以及/或氦气(He)，其中第一阶段蚀刻制作工艺中溴化氢与氦气的流量约 200/20每分钟标准毫升(standard cubic centimeter per minute,sccm)而制作工艺时间则约11秒。第二阶段蚀刻制作工艺较佳包含氯气(Cl2)以及/或氨气 (NH3)，其中第二阶段蚀刻制作工艺中氯气与氨气的流量约50/10每分钟标准毫升(sccm)而制作工艺时间则约15秒。第三阶段蚀刻制作工艺较佳包含溴化氢(HBr)以及/或氦气(He)，其中第三阶段蚀刻制作工艺中溴化氢与氦气的流量约200/20每分钟标准毫升(sccm)而制作工艺时间则约6～10秒。
如图3所示，然后进行一第二蚀刻制作工艺修整或削薄间隙壁30并使间隙壁30的厚度略微降低。在本实施例中，第二蚀刻制作工艺较佳包含三氟甲烷(CHF3)、四氟化碳(CF4)或其组合，其中第二蚀刻制作工艺中三氟甲烷与四氟化碳的流量约35/60每分钟标准毫升(sccm)而制作工艺时间则约0.05 纳秒。需注意的是，本阶段以第二蚀刻制作工艺修整间隙壁30的时候所使用的蚀刻气体成分较佳同时去除间隙壁30两侧的部分基底12形成孔洞34于间隙壁30正下方，其中间隙壁30的侧壁厚度虽于第二蚀刻制作工艺过程中略为降低但其底部仍较佳切齐基底12表面，因此所形成的孔洞34顶部较佳切齐栅极结构14、16正下方的基底12表面或间隙壁28底部，且孔洞34 除了暴露出部分或所有间隙壁30底部外又可依据制作工艺需求向内延伸甚至暴露出间隙壁28底部，此变化型也属本发明所涵盖的范围。
如图4所示，接着进行一第三蚀刻制作工艺等向性地加大初始凹槽32 以形成另一凹槽36。在本发明一实施例中，第三蚀刻制作工艺较佳包含湿蚀刻制作工艺，其中湿蚀刻制作工艺可选择使用例如氢氧化铵(ammonium hydroxide,NH4OH)或氢氧化四甲基铵(tetramethylammonium hydroxide, TMAH)等蚀刻液体。值得注意的是，形成凹槽36的方式不限于前述湿蚀刻的方式，也可以通过单次或多次的干蚀刻及/或湿蚀刻的方式来形成。例如于一实施例中，凹槽36可具有不同的截面形状，例如是圆弧、六边形(hexagon；又称sigmaΣ)或八边形(octagon)等截面形状，本实施例是以六边形的截面形状为实施样态说明，但并不以此为限。
随后如图5所示，进行一选择性外延成长(selective epitaxial growth,SEG) 制作工艺，以于凹槽36中依序形成缓冲层38以及外延层40并填满孔洞34。在本实施例中，缓冲层38与外延层40的整体形状较佳呈现约略六角形 (hexagon；又称sigmaΣ)且外延层40的顶表面较佳略高于基底12表面。以栅极结构一侧例如栅极结构14、16之间的外延层40为例，外延层40的两侧侧壁于填满孔洞34甚至接处间隙壁30底部处较佳形成两个突起部包括第一突起部42及第二突起部44，其中第一突起部42与第二突起部44各自包含一V形位于间隙壁30正下方，V形的夹角
Figure RE-GDA0002662789890000051
较佳大于30度并小于90度，且第一突起部42与第二突起部44的深度D均小于外延层40厚度的五分之一例如但不局限于5纳米至30纳米。
在本发明优选实施例中，外延层40根据不同的金属氧化物半导体(MOS) 晶体管类型而可以具有不同的材质，举例来说，若该金属氧化物半导体晶体管为一P型金属氧化物半导体晶体管(PMOS)时，外延层40可选择包含硅化锗(SiGe)、硅化锗硼(SiGeB)或硅化锗锡(SiGeSn)。而在本发明另一实施例中，若该金属氧化物半导体晶体管为一N型金属氧化物半导体晶体管(NMOS)时，外延层40可选择包含碳化硅(SiC)、碳磷化硅(SiCP)或磷化硅(SiP)。此外，选择性外延制作工艺可以用单层或多层的方式来形成，且其异质原子(例如锗原子或碳原子)也可以渐层的方式改变，但较佳是使外延层40的表面较淡或者无锗原子，以利后续金属硅化物层的形成。以本实施例制备PMOS晶体管为例，外延层40中的锗含量较佳介于30％至50％而硼的浓度则较佳介于 1.0×1020原子/立方厘米至1.0×1021原子/立方厘米。
需注意的是，相较于现行以离子注入方式形成轻掺杂漏极，本实施例主要省略以离子注入制作工艺形成轻掺杂漏极的手段而改利用同步(in-situ)掺杂的方式于形成外延层40的同时形成具有均匀浓度分布的掺杂区，其中位于第一突起部42及第二突起部44位置的掺杂区较佳作为轻掺杂漏极24。随后可进行一离子注入制作工艺，以于外延层40的约略中心部分特别是第一突起部42及第二突起部44以外或间隙壁30两侧而非间隙壁30正下方的外延层40内形成源极/漏极区域46，其中源极/漏极区域46的掺质浓度较佳大于第一突起部42及第二突起部44的轻掺杂漏极24掺质浓度且具有相同导电型式。然后形成一遮盖层48于外延层40上，其中由硅所构成的遮盖层48 较佳沿着由间隙壁30侧壁向上成长延伸且遮盖层48顶部较佳包含一平坦上表面。
接着如图6所示，先依序形成一接触洞蚀刻停止层(图未示)以及一层间介电层54于各栅极结构14、16上，然后进行一平坦化制作工艺，例如利用化学机械研磨(chemicalmechanical polishing,CMP)去除部分层间介电层54 与部分接触洞蚀刻停止层并暴露出由多晶硅材料所构成的栅极材料层20，使各硬掩模22上表面与层间介电层54上表面齐平。
随后进行一金属栅极置换制作工艺将栅极结构14、16转换为金属栅极。举例来说，可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水 (ammonium hydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液依序去除栅极结构14、16中的硬掩模22、栅极材料层20甚至栅极介电层18，以于层间介电层54中形成凹槽(图未示)。之后依序形成一选择性介质层56或栅极介电层(图未示)、一高介电常数介电层58、一功函数金属层60以及一低阻抗金属层62于各凹槽内，然后进行一平坦化制作工艺，例如利用CMP去除部分低阻抗金属层62、部分功函数金属层60与部分高介电常数介电层58以形成金属栅极64、66所构成的栅极结构14、16。以本实施例利用后高介电常数介电层制作工艺所制作的栅极结构为例，各栅极结构14、16较佳包含一介质层56或栅极介电层(图未示)、一U型高介电常数介电层58、一U型功函数金属层60以及一低阻抗金属层 62。
在本实施例中，高介电常数介电层58包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide, HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝 (aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物 (strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(lead zirconate titanate, PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其组合所组成的群组。
功函数金属层60较佳用以调整形成金属栅极的功函数，使其适用于N 型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层60可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛 (TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层60可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层60与低阻抗金属层62之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层62则可选自铜(Cu)、铝(Al)、钨 (W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。
之后可选择性去除部分高介电常数介电层58、部分功函数金属层60与部分低阻抗金属层62形成凹槽(图未示)，然后再填入一硬掩模68于凹槽内并使硬掩模68与层间介电层54表面齐平，其中硬掩模68可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。
随后可进行一接触插塞制作工艺形成接触插塞70分别电连接源极/漏极区域46。在本实施例中，形成接触插塞70的方式可先去除部分层间介电层 54与部分接触洞蚀刻停止层形成接触洞(图未示)，然后依序沉积一阻隔层(图未示)与一金属层(图未示)于基底12上并填满接触洞。接着利用一平坦化制作工艺，例如CMP去除部分金属层、部分阻隔层甚至部分层间介电层54，以于接触洞中形成接触插塞70，其中接触插塞70上表面较佳与层间介电层 54上表面切齐。在本实施例中，阻隔层较佳选自由钛、钽、氮化钛、氮化钽以及氮化钨所构成的群组，金属层较佳选自由铝、钛、钽、钨、铌、钼以及铜所构成的群组，但不局限于此。
请再参照图6，图6又揭露本发明一实施例的一半导体元件的结构示意图。如图6所示，半导体元件主要包含一由金属栅极64所构成的栅极结构 14设于基底12上、间隙壁28、30设于栅极结构14旁、袋状掺杂区26分别设于栅极结构14两侧的基底12内以及外延层40设于间隙壁30旁的基底12 内，其中各外延层40包含两个突起部且各突起部具有大于30度的夹角位于各间隙壁30下方。
以栅极结构一侧例如栅极结构14、16之间的外延层40为例，半导体元件包含第一突起部42设于外延层40一侧以及第二突起部44设于外延层40 另一侧，其中第一突起部42又设于栅极结构14一侧的基底12内而第二突起部44则设于栅极结构16一侧的基底12内。从细部来看第一突起部42直接接触栅极结构14旁的间隙壁30底部，第二突起部44直接接触栅极结构 16旁的间隙壁30底部，第一突起部42与第二突起部44各自包含一V形位于间隙壁30下方，V形的夹角
Figure RE-GDA0002662789890000081
较佳大于30度并小于90度，且第一突起部42与第二突起部44的深度D均小于外延层40厚度的五分之一例如但不局限于5纳米至15纳米。
请继续参照图7，图7为本发明一实施例的一半导体元件的结构示意图。如图7所示，本发明一实施例可于图5形成缓冲层38之后先形成第一外延层72于凹槽32内并可填满或不填满孔洞34，然后进行一第四蚀刻制作工艺利用例如盐酸(HCl)去除部分第一外延层72，形成具有V形剖面的第二外延层74于第一外延层72上，形成第三外延层76于第二外延层74上，再形成遮盖层48于第三外延层76上。
值得注意的是，为了改善元件的漏电流，本实施例可于第一外延层72 与第三外延层76内以同步掺植(in-situ doping)方式注入掺质作为源极/漏极区域46，并于第二外延层74中再以同步掺植(in-situ doping)方式注入与第一外延层72或源极/漏极区域46相反导电型式的掺质作为轻掺杂漏极24。以本实施例制备PMOS晶体管为例，第一外延层72以及第三掺杂区76中的源极 /漏极区域46较佳包含P型掺质而第二外延层74则较佳包含N型掺质，但不局限于此。
整体来看，第二外延层74本身呈现一约略V形的剖面，另外如同前述实施例的外延层40，第二外延层74的两侧于填满孔洞34处较佳形成两个突起部包括第一突起部42及第二突起部44作为轻掺杂漏极24，其中第一突起部42与第二突起部44各自包含一V形位于间隙壁30正下方，V形的夹角
Figure RE-GDA0002662789890000091
较佳大于30度并小于90度，且第一突起部42与第二突起部44的深度D 均小于第一外延层72至第三外延层76厚度的五分之一例如但不局限于5纳米至30纳米。在本实施例中，第一外延层72以及/或第三外延层76中的锗含量较佳介于30％至50％而其中所包含的P型掺质例如硼的浓度则较佳介于 1.0×1020原子/立方厘米至1.0×1021原子/立方厘米，第二外延层74中的锗含量较佳介于30％至50％而其中所包含的N形掺质例如磷的浓度较佳介于 1.0×1016原子/立方厘米至1.0×1021原子/立方厘米。
一般而言，现行以离子注入制作工艺形成袋状掺杂区26之后以及利用前述第一蚀刻制作工艺形成凹槽32之前通常会额外进行一道轻掺杂离子注入制作工艺于间隙壁两侧的基底内形成轻掺杂漏极。考虑以离子注入制作工艺形成轻掺杂漏极的作法不容易精准控制轻掺杂漏极的浓度分布并容易造成漏电及短通道效应(short channel effect,SCE)，本发明主要省略以离子注入制作工艺形成轻掺杂漏极的手段而改利用同步(in-situ)掺杂的方式于形成外延层(例如前述实施例中的第二外延层74)的同时形成具有均匀浓度分布的轻掺杂漏极24(例如第一突起部42及第二突起部44)。此外，本发明另一实施例又可选择于基底内形成凹槽32后额外进行一道蚀刻制作工艺修整或削薄最外侧的间隙壁30，使后续利用同步掺杂方式所形成的轻掺杂漏极与外延层等更为接近栅极结构以提升元件整体效能。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种制作半导体元件的方法，其特征在于，包含：
形成栅极结构于基底上；
形成间隙壁于该栅极结构旁；
形成第一凹槽于该间隙壁旁；
修整部分该间隙壁；以及
形成第一外延层于该第一凹槽内。
2.如权利要求1所述的方法，另包含：
进行第一蚀刻制作工艺去除该基底以形成第二凹槽；
进行第二蚀刻制作工艺以修整该间隙壁；
进行第三蚀刻制作工艺扩大该第二凹槽以形成该第一凹槽；以及
形成该第一外延层于该第一凹槽内。
3.如权利要求2所述的方法，其中该第一蚀刻制作工艺包含干蚀刻制作工艺。
4.如权利要求2所述的方法，其中该第二蚀刻制作工艺包含干蚀刻制作工艺。
5.如权利要求2所述的方法，其中该第三蚀刻制作工艺包含湿蚀刻制作工艺。
6.如权利要求2所述的方法，另包含：
进行第四蚀刻制作工艺去除该第一外延层；
形成第二外延层包含现场掺质于该第一外延层上；以及
形成第三外延层于该第二外延层上。
7.如权利要求6所述的方法，其中该第一外延层以及该第二外延层包含相反掺质。
8.如权利要求6所述的方法，其中该第二外延层包含第一V形。
9.如权利要求1所述的方法，另包含：
形成第一突起部于该第一外延层一侧；以及
形成第二突起部于该第一外延层另一侧。
10.如权利要求9所述的方法，其中该第一突起部包含第二V形设于该间隙壁下方。
11.如权利要求10所述的方法，其中该第二V形的夹角大于30度以及小于90度。
12.一种半导体元件，其特征在于，包含：
栅极结构，设于基底上；
间隙壁，设于该栅极结构旁；以及
外延层，设于该间隙壁旁，其中该外延层包含突起部具有大于30度的夹角位于该间隙壁下方。
13.如权利要求12所述的半导体元件，另包含：
第一突起部，设于该外延层一侧；以及
第二突起部，设于该外延层另一侧。
14.如权利要求13所述的半导体元件，其中该第一突起部包含V形位于该间隙壁下方。
15.如权利要求14所述的半导体元件，其中该V形的夹角大于30度以及小于90度。
16.如权利要求13所述的半导体元件，其中该第一突起部深度小于该外延层厚度的五分之一。
17.一种半导体元件，其特征在于，包含：
栅极结构，设于基底上；
间隙壁，设于该栅极结构旁；
第一外延层，设于该间隙壁旁；
第二外延层，设于该第一外延层上，其中该第二外延层包含V形；以及
第三外延层，设于该第二外延层上。
18.如权利要求17所述的半导体元件，其中该第一外延层以及该第二外延层包含相反掺质。
19.如权利要求17所述的半导体元件，其中该第二外延层以及该第三外延层包含相反掺质。
20.如权利要求17所述的半导体元件，其中该V形位于该间隙壁正下方。
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