CN114334655A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN114334655A
CN114334655A CN202011082680.8A CN202011082680A CN114334655A CN 114334655 A CN114334655 A CN 114334655A CN 202011082680 A CN202011082680 A CN 202011082680A CN 114334655 A CN114334655 A CN 114334655A
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gate
layer
stop layer
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gate structure
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林俊贤
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US17/088,522 priority patent/US11552181B2/en
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Priority to US18/075,396 priority patent/US20230100606A1/en
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Abstract

本发明公开一种半导体元件及其制作方法，其中该制作半导体元件的方法为，首先形成一鳍状结构于基底上，然后形成一栅极材料层于鳍状结构上，进行一蚀刻制作工艺图案化栅极材料层以形成一栅极结构以及一硅残留，对该硅残留进行灰化制作工艺，再进行一清洗制作工艺将该硅残留转换为聚合物停止层于鳍状结构顶部及侧壁。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种于栅极结构旁形成聚合物停止层的方法。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
一般而言，半导体制作工艺在进入10纳米世代后金属栅极的电阻值对整个鳍状场效晶体管的效能扮演了一重要角色。由于现今的金属栅极晶体管架构对整个电阻值的表现仍不尽理想，因此如何在现今场效晶体管的架构下改良此问题即为现今一重要课题。
发明内容
本发明一实施例揭露一种制作半导体元件的方法。首先形成一鳍状结构于基底上，然后形成一栅极材料层于鳍状结构上，进行一蚀刻制作工艺图案化栅极材料层以形成一栅极结构以及一硅残留，对该硅残留进行灰化制作工艺，再进行一清洗制作工艺将该硅残留转换为聚合物停止层于鳍状结构顶部及侧壁。
本发明另一实施例揭露一种半导体元件，其主要包含一鳍状结构设于基底上，一栅极结构设于鳍状结构上以及图案化该栅极材料层以形成一栅极结构以及一聚合物停止层设于该栅极结构旁的鳍状结构顶部及侧壁。
本发明又一实施例揭露一种半导体元件，其主要包含一鳍状结构依据上视角度沿着第一方向延伸于一基底上，第一栅极结构沿着第二方向延伸于鳍状结构一侧且第一栅极结构紧邻鳍状结构的第一角落包含第一聚合物停止层以及第二栅极结构沿着第二方向延伸于鳍状结构另一侧。
附图说明
图1至图6为本发明优选实施例制作一半导体元件的方法示意图；
图7为本发明一实施例的一半导体元件的结构上视图。
主要元件符号说明
12:基底
14:鳍状结构
16:浅沟隔离
18:栅极结构
20:介质层
22:栅极材料层
24:硬掩模
26:硬掩模
28:聚合物停止层
30:第一遮盖层
32:第二遮盖层
34:第一间隙壁
36:第二间隙壁
38:外延层
40:源极/漏极区域
42:接触洞蚀刻停止层
44:层间介电层
46:金属栅极
48:高介电常数介电层
50:功函数金属层
52:低阻抗金属层
54:硬掩模
56:接触插塞
62:栅极结构
64:栅极结构
66:聚合物停止层
68:聚合物停止层
70:聚合物停止层
72:聚合物停止层
具体实施方式
请参照图1至图6，图1至图6为本发明优选实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，其上可定义有一晶体管区，例如一PMOS晶体管区或一NMOS晶体管区。基底12上具有至少一鳍状结构14及一绝缘层(图未示)，其中鳍状结构14的底部是被绝缘层，例如氧化硅所包覆而形成浅沟隔离16。需注意的是，本实施例虽以制作非平面型场效晶体管(non-planar)例如鳍状结构场效晶体管为例，但不局限于此，本发明又可应用至一般平面型(planar)场效晶体管，此实施例也属本发明所涵盖的范围。
依据本发明一实施例，鳍状结构14较佳通过侧壁图案转移(sidewall imagetransfer,SIT)技术制得，其程序大致包括：提供一布局图案至计算机系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构14的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构。另外，鳍状结构的形成方式也可以先形成一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构。这些形成鳍状结构的实施例均属本发明所涵盖的范围。
接着可于基底12上形成至少一栅极结构18或虚置栅极。在本实施例中，栅极结构18的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。以本实施例的后高介电常数介电层制作工艺为例，可先依序形成一栅极介电层或介质层20、一由多晶硅所构成的栅极材料层22、一硬掩模24以及另一硬掩模26于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分硬掩模26、24、部分栅极材料层22以及部分介质层20，然后剥除图案化光致抗蚀剂，以于基底12上形成由介质层20、图案化的栅极材料层22以及图案化的硬掩模24、26所构成的栅极结构18。在本实施例中，介质层20较佳由氧化硅所构成，硬掩模24较佳由氮化硅所构成，而硬掩模26则较佳由氧化硅所构成。
值得注意的是，本实施例于上述图案化制作工艺形成栅极结构18的过程中较佳先进行一蚀刻制作工艺图案化硬掩模26、硬掩模24、栅极材料层22、甚至介质层20以形成栅极结构18并同时形成硅残留(图未示)于栅极结构18两侧的鳍状结构14顶部及侧壁，其中蚀刻制作工艺所使用的气体可包含但不局限于四氟化碳(CF4)、四氯化碳(CCl4)、氮气(N2)、二氟甲烷(CH2F2)、二溴甲烷(CH2Br2)以及/或二氯甲烷(CH2Cl2)，且蚀刻制作工艺较佳形成包含碳、氮以及氟等成分或更具体而言包含SiCNFx的硅残留以及氟(F2)。
接着对硅残留进行一灰化制作工艺并将原本由SiCNFx所构成的硅残留经由氧气等离子体转换为SiCONF。之后再进行一清洗制作工艺，利用过氧化氢(H2O2)将具有SiCONF成分的硅残留转换为一聚合物停止层28，其中聚合物停止层28包含碳、氧、氮、氢以及氟等成分或更具体而言包含SiCONHF组成。换句话说，图案化形成栅极结构18的步骤较佳包含前述用来形成硅残留的蚀刻制作工艺、灰化制作工艺以及清洗制作工艺，且在形成栅极结构18的过程中聚合物停止层28同时形成于栅极结构18两侧的鳍状结构14顶部及侧壁。
请同时参照图1及图2，图2为本发明一实施例制作半导体元件的立体结构示意图而图1则为图2中沿着箭头方向所视的结构示意图，其中图1中两个聚合物停止层28向下延伸至鳍状结构14侧壁表面之间的部分实际上应为栅极结构18横跨并重叠鳍状结构14的部位但为了不使图示过于复杂在此仅标注鳍状结构14。如图1及图2所示，本发明依据前述一连串蚀刻、灰化及清洗制作工艺所形成的聚合物停止层28较佳形成于栅极结构18两侧的鳍状结构14顶部及侧壁。从细部来看，聚合物停止层28较佳由栅极结构18两侧的鳍状结构14顶部沿着栅极结构18两侧的鳍状结构二侧侧壁向下延伸至略鳍状结构14底部与浅沟隔离16交界的位置。换句话说，所形成的聚合物停止层28在图2中较佳呈现一约略倒U形跨在栅极结构18两侧的鳍状结构14上，其中聚合物停止层28仅设于栅极结构18两侧的鳍状结构14表面而不设于栅极结构18正下方及鳍状结构14之间。
如图3所示，接着进行一再氧化(re-oxidation)制作工艺以形成一第一遮盖层30于栅极结构18侧壁。更具体而言，本阶段所进行的再氧化制作工艺较佳利用炉管或干氧方式于约略摄氏750度的环境下通入氧气，以于栅极结构18顶部及侧壁，包括栅极材料层22侧壁、硬掩模24侧壁以及硬掩模26侧壁与顶部形成一由氧化硅所构成的第一遮盖层30。需注意的是，本阶段所进行的氧化制作工艺在通入氧气时较佳穿过聚合物停止层28来氧化栅极结构18的所有侧壁，因此所形成的第一遮盖层30较佳形成于聚合物停止层28的内侧侧壁，或从另一角度来看第一遮盖层30的内侧侧壁较佳接触栅极结构18而外侧侧壁则接触聚合物停止层28的内侧侧壁。
如图4所示，随后先形成一第二遮盖层32于第一遮盖层30及聚合物停止层28侧壁，再利用蚀刻去除部分第二遮盖层32及部分第一遮盖层30以形成第一间隙壁34及第二间隙壁36于栅极结构18侧壁。在本实施例中，第一间隙壁34与第二间隙壁36较佳包含不同材料，其中第一间隙壁34较佳由氧化硅所构成而第二间隙壁36则较佳由氮碳氧化硅(SiOCN)所构成，但不局限于此，依据本发明其他实施例第二间隙壁36又可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。
然后进行一干蚀刻及/或湿蚀刻制作工艺，利用栅极结构18与第二间隙壁36作为蚀刻掩模，沿着第二间隙壁36向下单次或多次蚀刻基底12，以于栅极结构18两侧的基底12中形成一凹槽(图未示)。接着进行一选择性外延成长(selective epitaxial growth,SEG)制作工艺，以于凹槽中形成一外延层38。在本实施例中，外延层38的一顶表面较佳与鳍状结构14一顶表面齐平，且较佳与第一凹槽具有相同的截面形状，如圆弧、六边形(hexagon；又称sigmaΣ)或八边形(octagon)的截面形状，但也可以是其他截面形状。在本发明优选实施例中，外延层38根据不同的金属氧化物半导体(MOS)晶体管类型而可以具有不同的材质，举例来说，若该金属氧化物半导体晶体管为一P型晶体管(PMOS)时，外延层38可选择包含硅化锗(SiGe)、硅化锗硼(SiGeB)或硅化锗锡(SiGeSn)。而于本发明另一实施例中，若该金属氧化物半导体晶体管为一N型晶体管(NMOS)时，外延层38可选择包含碳化硅(SiC)、碳磷化硅(SiCP)或磷化硅(SiP)。此外，选择性外延制作工艺可以用单层或多层的方式来形成，且其异质原子(例如锗原子或碳原子)也可以渐层的方式改变，但较佳是使外延层38的表面较淡或者无锗原子，以利后续金属硅化物层的形成。另一方面，本实施例虽是以顶表面与鳍状结构14顶表面齐平的外延层38为实施样态说明，但在本发明的其他实施例中，也可选择使外延层38进一步向上延伸至高于鳍状结构14顶表面。
后续可进行一离子注入制作工艺，以于外延层38的一部分或全部形成一源极/漏极区域40。在另一实施例中，源极/漏极区域40的形成也可同步(in-situ)于选择性外延成长制作工艺进行，例如金属氧化物半导体是PMOS时，形成硅化锗外延层、硅化锗硼外延层或硅化锗锡外延层，可以伴随着注入P型掺质；或是当金属氧化物半导体是NMOS时，形成硅化碳外延层、硅化碳磷外延层或硅化磷外延层，可以伴随着注入N型掺质。藉此可省略后续利用额外离子注入步骤形成P型/N型晶体管的源极/漏极区域。此外在另一实施例中，源极/漏极区域40的掺质也可以渐层的方式形成。
接着如图5所示，先形成一接触洞蚀刻停止层42于基底12表面与栅极结构18上，再形成一层间介电层44于接触洞蚀刻停止层42上。然后进行一平坦化制作工艺，例如利用化学机械研磨(chemical mechanical polishing,CMP)去除部分层间介电层44与部分接触洞蚀刻停止层42并暴露出由硬掩模26，使硬掩模26上表面与层间介电层44上表面齐平。在本实施例中接触洞蚀刻停止层42可包含例如氮化硅而层间介电层44可包含例如氧化硅，但均不局限于此。
如图6所示，随后进行一金属栅极置换制作工艺将栅极结构18转换为金属栅极46。举例来说，可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammoniumhydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除栅极结构18中的硬掩模26、24及栅极材料层22，以于层间介电层44中形成凹槽(图未示)。之后依序形成一高介电常数介电层48、一功函数金属层50以及一低阻抗金属层52于凹槽内，然后进行一平坦化制作工艺，例如利用CMP去除部分低阻抗金属层52、部分功函数金属层50与部分高介电常数介电层48以形成金属栅极46。以本实施例利用后高介电常数介电层制作工艺所制作的金属栅极46为例，金属栅极46较佳包含一介质层20或栅极介电层、一U型高介电常数介电层48、一U型功函数金属层50以及一低阻抗金属层52。随后可去除部分低阻抗金属层52、部分功函数金属层50以及部分高介电常数介电层48以形成一凹槽，再填入一硬掩模54于凹槽内并搭配进行一平坦化制作工艺，使硬掩模54上表面切齐层间介电层44上表面。
在本实施例中，高介电常数介电层48包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层50较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层50可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层50可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层50与低阻抗金属层52之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层48则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。之后可依据制作工艺需求进行接触插塞制作工艺，例如可于层间介电层44与接触洞蚀刻停止层42中形成接触插塞56电连接第二间隙壁36两侧的源极/漏极区域40。至此即完成本发明一实施例的半导体元件的制作。
请继续参照图6及前述的图2，图2及图6分别揭露本发明一实施例的一半导体元件的结构示意图。如图2及图6所示，半导体元件主要包含一栅极结构18设于基底12上，第一间隙壁34设于栅极结构18侧壁，第二间隙壁36设于第一间隙壁34侧壁，一聚合物停止层28设于第一间隙壁34与第二间隙壁36之间以及一源极/漏极区域40设于栅极结构18两侧，其中聚合物停止层28较佳设于栅极结构18两侧的鳍状结构14顶部及侧壁。
从图2的3D立体结构来看，即使后续形成第一间隙壁34、第二间隙壁36以及源极/漏极区域40等元件后聚合物停止层28仍较佳由栅极结构18两侧的鳍状结构14顶部沿着栅极结构18两侧的鳍状结构14两侧侧壁向下延伸至约略鳍状结构14底部与浅沟隔离16交界的位置。而从图6剖面来看，聚合物停止层28较佳介于第一间隙壁34及第二间隙壁36之间，其中本实施例位于鳍状结构14上方的聚合物停止层28顶部虽以约略三角形为例，但不局限于此形状，依据本发明其他实施例聚合物停止层28顶部又可依据前述蚀刻过程中所使用气体成分的变化而有所不同，例如又可包含圆形、矩形或其他不规则形状。此外本实施例突出于鳍状结构14上方的聚合物停止层28整体高度较佳低于栅极结构18整体高度的十分之一甚至二十分之一。
从材料面来看，第一间隙壁34与聚合物停止层28较佳包含不同材料，第二间隙壁36与聚合物停止层28较佳包含不同材料，其中本实施例的第一间隙壁34较佳包含氧化硅，第二间隙壁36较佳包含氮碳氧化硅，而聚合物停止层28则可依据图案化制作工艺形成栅极结构18时所使用气体成分而有所不同，例如可包含碳、氧、氮、氢以及氟等成分或更具体而言包含SiCONHF组成。
请继续参照图7，图7揭露本发明一实施例的一半导体元件的结构上视图。如图7所示，本发明可于前述金属栅极置换制作工艺以平坦化制作工艺形成金属栅极46时去除设于鳍状结构14正上方的所有栅极结构18或金属栅极46或更具体而言通过平坦化制作工艺例如化学机械研磨制作工艺将原本横跨在鳍状结构14正上方的栅极结构18完全磨平并将栅极结构18分隔为两部分，例如图7设于鳍状结构14两侧的栅极结构62及栅极结构64。换句话说，原本横跨在鳍状结构14上方的栅极结构18经由平坦化制作工艺较佳被分隔为两部分分别设于鳍状结构14两侧而鳍状结构14正上方则无任何栅极结构18。另外原本设于栅极结构18两侧的聚合物停止层28经由平坦化制作工艺后则在上视角度下较佳被分隔为四个聚合物停止层66、68、70、72并设于鳍状结构14与栅极结构62、64之间的四个角落。
整体来看，上视角度下的鳍状结构14较佳沿着第一方向例如Y方向延伸于基底12上，鳍状结构14正上方并无任何栅极结构18，由栅极结构18分隔出的栅极结构62是沿着第二方向例如X方向延伸于鳍状结构14一侧，同样由栅极结构18分隔出的栅极结构64一样沿着第二方向如X方向延伸于鳍状结构14另一侧，鳍状结构14两侧与栅极结构62、64之间另设有介质层20，栅极结构62紧邻鳍状结构14的第一角落包含聚合物停止层66，栅极结构62紧邻鳍状结构14的第二角落包含聚合物停止层68，栅极结构64紧邻鳍状结构14的第三角落包含聚合物停止层70，栅极结构64紧邻鳍状结构14的第四角落包含聚合物停止层72，而第二间隙壁36则环绕整个鳍状结构14及栅极结构62、64外侧。
在本实施例中分别设于栅极结构62、64角落的聚合物停止层66、68、70、72在上视角度下较佳直接接触鳍状结构14、介质层20以及各栅极结构62、64，其中本实施例的各聚合物停止层66、68、70、72在上视角度下虽以三角形为例，但不局限于此形状，依据本发明其他实施例聚合物停止层66、68、70、72又可依据前述蚀刻过程中所使用气体成分的变化而有所不同，例如又可包含圆形、矩形或其他不规则形状。如前所述聚合物停止层66、68、70、72较佳包含相同材料例如可包含碳、氧、氮、氢以及氟等成分或更具体而言包含SiCONHF组成。
一般而言，现行鳍状场效晶体管制作工艺中图案化形成栅极结构时如前面所述均较佳于栅极结构与基底之间的夹角形成聚合块或鳍状结构角落氧化物(FCO)，然后再利用沉积制作工艺于栅极结构侧壁形成间隙壁将聚合块包覆于栅极电极与间隙壁之间。由于现行制作工艺中聚合块的内侧侧壁是紧邻或直接接触多晶硅所构成的栅极材料层或栅极电极，因此于后续以金属栅极置换制作工艺掏空多晶硅所构成的栅极材料层时通常会一同去除聚合块造成漏电。为了改善此缺点，本发明较佳于栅极结构两侧的鳍状结构顶部及侧壁形成聚合物停止层，之后利用再氧化制作工艺于聚合物停止层内侧的栅极结构侧壁形成第一遮盖层30或后续的第一间隙壁34作为聚合物停止层与栅极结构间的一阻隔或阻挡层，如此后续以金属栅极置换制作工艺掏空多晶硅所构成的栅极材料层时便不致一同去除聚合物停止层造成漏电流的现象。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种制作半导体元件的方法，其特征在于，包含：
形成鳍状结构于基底上；
形成栅极材料层于该鳍状结构上；以及
图案化该栅极材料层以形成栅极结构以及聚合物停止层于该鳍状结构顶部及侧壁。
2.如权利要求1所述的方法，另包含：
进行蚀刻制作工艺图案化该栅极材料层以形成硅残留；
对该硅残留进行灰化制作工艺；以及
进行清洗制作工艺将该硅残留转换为该聚合物停止层。
3.如权利要求2所述的方法，其中该硅残留包含碳、氮以及氟。
4.如权利要求1所述的方法，其中该聚合物停止层包含碳、氧、氮、氢以及氟。
5.如权利要求1所述的方法，另包含：
形成第一硬掩模于该栅极材料层上；
形成第二硬掩模于该第一硬掩模上；以及
图案化该第二硬掩模、该第一硬掩模以及该栅极材料层以形成该栅极结构以及该聚合物停止层。
6.如权利要求1所述的方法，另包含进行氧化制作工艺将该栅极结构侧壁氧化以形成第一遮盖层。
7.如权利要求6所述的方法，另包含形成该第一遮盖层于该栅极结构侧壁以及该聚合物停止层内侧侧壁。
8.如权利要求6所述的方法，另包含：
形成第二遮盖层于该第一遮盖层侧壁以及该聚合物停止层侧壁；
去除该第二遮盖层以及该第一遮盖层以形成第一间隙壁以及第二间隙壁；
形成源极/漏极区域于该第二间隙壁两侧；
形成层间介电层于该栅极结构上；以及
进行金属栅极置换制作工艺将该栅极结构转换为金属栅极。
9.如权利要求8所述的方法，另包含：
进行平坦化制作工艺去除该金属栅极以形成第一金属栅极于该鳍状结构一侧以及第二金属栅极于该鳍状结构另一侧。
10.一种半导体元件，其特征在于，包含：
鳍状结构，设于基底上；
栅极结构，设于该鳍状结构上；以及
聚合物停止层，设于该栅极结构旁的该鳍状结构顶部及侧壁。
11.如权利要求10所述的半导体元件，另包含：
第一间隙壁，设于该栅极结构侧壁；
第二间隙壁，设于该第一间隙壁侧壁，其中该聚合物停止层是设于该第一间隙壁以及该第二间隙壁之间；以及
源极/漏极区域，设于该第二间隙壁两侧。
12.如权利要求10所述的半导体元件，其中该第一间隙壁以及该聚合物停止层包含不同材料。
13.如权利要求10所述的半导体元件，其中该第二间隙壁以及该聚合物停止层包含不同材料。
14.如权利要求10所述的半导体元件，其中该聚合物停止层包含碳、氧、氮、氢以及氟。
15.一种半导体元件，其特征在于，包含：
鳍状结构，依据上视角度沿着第一方向延伸于基底上；
第一栅极结构，沿着第二方向延伸于该鳍状结构一侧，其中该第一栅极结构紧邻该鳍状结构的第一角落包含第一聚合物停止层；以及
第二栅极结构，沿着第二方向延伸于该鳍状结构另一侧。
16.如权利要求15所述的半导体元件，其中该第一栅极结构紧邻该鳍状结构的第二角落包含第二聚合物停止层。
17.如权利要求15所述的半导体元件，其中该第二栅极结构紧邻该鳍状结构的第三角落包含第三聚合物停止层。
18.如权利要求15所述的半导体元件，其中该第二栅极结构紧邻该鳍状结构的第四角落包含第四聚合物停止层。
19.如权利要求15所述的半导体元件，其中该第一聚合物停止层包含碳、氧、氮、氢以及氟。
20.如权利要求15所述的半导体元件，另包含介质层，设于该第一栅极结构以及该鳍状结构之间。
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