CN113161366A - 具有使用内插器的堆叠器件芯片的三维存储器件 - Google Patents

具有使用内插器的堆叠器件芯片的三维存储器件 Download PDF

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CN113161366A
CN113161366A CN202110040294.0A CN202110040294A CN113161366A CN 113161366 A CN113161366 A CN 113161366A CN 202110040294 A CN202110040294 A CN 202110040294A CN 113161366 A CN113161366 A CN 113161366A
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CN113161366B (zh
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刘峻
肖莉红
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Abstract

公开了具有使用内插器的堆叠器件芯片的三维(3D)存储器件及其制造方法的实施例。在示例中，3D存储器件包括第一和第二器件芯片以及其间的内插器。第一器件芯片包括外围器件以及处于所述第一器件芯片的表面上并且电连接至所述外围器件的第一芯片触点。第二器件芯片包括交替导体/电介质堆叠层、竖直延伸通过所述交替导体/电介质堆叠层的存储器串、以及处于所述第二器件芯片的表面上并且电连接至所述存储器串的第二芯片触点。所述内插器包括内插器衬底以及处于所述内插器的相对表面上并且通过所述内插器衬底相互电连接的第一和第二内插器触点。第一和第二内插器触点分别附接至所述第一和第二芯片触点。

Description

具有使用内插器的堆叠器件芯片的三维存储器件
本申请是申请日为2018年06月29日，发明名称为“具有使用内插器的堆叠器件芯片的三维存储器件”，申请号为201880000984.X的专利申请的分案申请。
背景技术
本公开的实施例涉及三维(3D)存储器件及其制造方法。
通过改进工艺技术、电路设计、程序设计算法和制造工艺使平面存储单元缩小到更小的尺寸。然而，随着存储单元的特征尺寸接近下限，平面工艺和制造技术变得有挑战性，而且成本高。结果，平面存储单元的存储密度接近上限。
3D存储器架构能够解决平面存储单元的密度限制。3D存储器架构包括存储器阵列以及用于控制到和来自存储器阵列的信号的外围器件。
发明内容
文中公开了具有使用内插器的堆叠器件芯片的3D存储器件及其制造方法的实施例。
在一个示例中，3D存储器件包括第一器件芯片、第二器件芯片、以及竖直设置在第一器件芯片和第二器件芯片之间的内插器。所述第一器件芯片包括外围器件以及设置在所述第一器件芯片的表面上并且电连接至所述外围器件的第一芯片触点。第二器件芯片包括交替导体/电介质堆叠层、竖直延伸通过所述交替导体/电介质堆叠层的存储器串、以及设置在所述第二器件芯片的表面上并且电连接至所述存储器串的第二芯片触点。所述内插器包括内插器衬底、设置在所述内插器的第一表面上的第一内插器触点、以及设置在所述内插器的与所述第一表面相对的第二表面上并且通过所述内插器衬底电连接至所述第一内插器触点的第二内插器触点。所述第一内插器触点附接至所述第一芯片触点，并且所述第二内插器触点附接至所述第二芯片触点。
在另一个示例中，3D存储器件包括第一器件芯片、第二器件芯片、以及竖直设置在第一器件芯片和第二器件芯片之间的内插器。所述第一器件芯片包括第一交替导体/电介质堆叠层、竖直延伸通过所述第一交替导体/ 电介质堆叠层的第一存储器串、以及设置在所述第一器件芯片的表面上并且电连接至所述第一存储器串的第一芯片触点。所述第二器件芯片包括第二交替导体/电介质堆叠层、竖直延伸通过所述第二交替导体/电介质堆叠层的第二存储器串、以及设置在所述第二器件芯片的表面上并且电连接至所述第二存储器串的第二芯片触点。所述内插器包括内插器衬底、设置在所述内插器的第一表面上的第一内插器触点、以及设置在所述内插器的与所述第一表面相对的第二表面上并且通过所述内插器衬底电连接至所述第一内插器触点的第二内插器触点。所述第一内插器触点附接至所述第一芯片触点，并且所述第二内插器触点附接至所述第二芯片触点。
在不同的示例中，公开了用于形成3D存储器件的方法。交替导体/电介质堆叠层形成在芯片衬底的第一侧。形成竖直延伸通过所述交替导体/电介质堆叠层的存储器串。芯片触点形成在所述芯片衬底的与所述第一侧相对的第二侧并且电连接至所述存储器串。第一内插器触点形成在内插器衬底的第一侧。第二内插器触点形成在内插器衬底的与第一侧相对的第二侧并且通过内插器衬底电连接至第一内插器触点。所述第一内插器触点附接至所述芯片触点。
在另一个示例中，公开了用于形成3D存储器件的方法。交替导体/电介质堆叠层形成在芯片衬底的第一侧。形成竖直延伸通过所述交替导体/电介质堆叠层的存储器串。芯片触点形成在所述芯片衬底的第一侧并且电连接至所述存储器串。第一内插器触点形成在内插器衬底的第一侧。第二内插器触点形成在内插器衬底的与第一侧相对的第二侧并且通过内插器衬底电连接至第一内插器触点。所述第一内插器触点附接至芯片触点。
附图说明
被并入本文并形成说明书的一部分的附图例示了本公开的实施例并与说明书一起进一步用以解释本公开的原理，并使相关领域的技术人员能够做出和使用本公开。
图1示出了根据一些实施例的具有使用内插器的堆叠器件芯片的示例性3D存储器件的截面图。
图2A-图2H示出了根据各种实施例的具有使用内插器的堆叠的外围器件芯片和存储器阵列器件芯片的示例性3D存储器件的示意图。
图3A-图3D示出了根据各种实施例的具有使用内插器的堆叠存储器阵列器件芯片的示例性3D存储器件的示意图。
图4A-图4D示出了根据一些实施例的用于形成外围器件芯片的示例性制造过程。
图5A-图5G示出了根据一些实施例的用于形成存储器阵列器件芯片的示例性制造过程。
图6A-图6F示出了根据一些实施例的用于形成内插器的示例性制造过程。
图7A-图7B示出了根据一些实施例的用于将外围器件芯片和存储器件阵列器件芯片附接至内插器的示例性制造过程。
图8是根据一些实施例的用于形成外围器件芯片的示例性方法的流程图。
图9是根据一些实施例的用于形成存储器阵列器件芯片的示例性方法的流程图。
图10是根据一些实施例的用于形成内插器的示例性方法的流程图。
将参考附图描述本公开的实施例。
具体实施方式
尽管对具体配置和布置进行了讨论，但应当理解，这只是出于示例性目的而进行的。相关领域中的技术人员将认识到，可以使用其它配置和布置而不脱离本公开的精神和范围。对相关领域的技术人员显而易见的是，本公开还可以用于多种其它应用中。
要指出的是，在说明书中提到“一个实施例”、“实施例”、“示例性实施例”、“一些实施例”等指示所述的实施例可以包括特定特征、结构或特性，但未必每个实施例都包括该特定特征、结构或特性。此外，这种短语未必是指同一个实施例。另外，在结合实施例描述特定特征、结构或特性时，结合其它实施例(无论是否明确描述)实现这种特征、结构或特性应在相关领域技术人员的知识范围内。
通常，可以至少部分从上下文中的使用来理解术语。例如，至少部分取决于上下文，本文中使用的术语“一个或多个”可以用于描述单数意义的任何特征、结构或特性，或者可以用于描述复数意义的特征、结构或特性的组合。类似地，至少部分取决于上下文，诸如“一”或“所述”的术语同样可以被理解为传达单数使用或传达复数使用。此外，可以将术语“基于”理解为未必旨在传达排他性的一组因素，并且相反可以允许存在未必明确描述的额外因素，其同样至少部分地取决于上下文上下文。
应当容易理解，本公开中的“在…上”、“在…上方”和“在…之上”的含义应当以最宽方式被解读，以使得“在…上”不仅表示“直接在”某物“上”而且还包括在某物“上”且其间有居间特征或层的含义，并且“在…上方”或“在…之上”不仅表示“在”某物“上方”或“之上”的含义，而且还可以包括其“在”某物“上方”或“之上”且其间没有居间特征或层(即，直接在某物上)的含义。
此外，诸如“在…之下”、“在…下方”、“下部”、“在…上方”、“上部”等空间相关术语在本文中为了描述方便可以用于描述一个元件或特征与另一个或多个元件或特征的关系，如在附图中示出的。空间相关术语旨在涵盖除了在附图所描绘的取向之外的在设备使用或操作中的不同取向。设备可以以另外的方式被定向(旋转90度或在其它取向)，并且本文中使用的空间相关描述词可以类似地被相应解释。
如本文中使用的，术语“衬底”是指向其上增加后续材料层的材料。衬底自身可以被图案化。增加在衬底顶部的材料可以被图案化或者可以保持不被图案化。此外，衬底可以包括宽范围的半导体材料，例如硅、锗、砷化镓、磷化铟等。替代地，衬底可以由诸如玻璃、塑料或蓝宝石晶圆的非导电材料制成。
如本文中使用的，术语“层”是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构的厚度的均质或非均质连续结构的区域。例如，层可以位于在连续结构的顶表面和底表面之间或在顶表面和底表面处的任何水平面对之间。层可以水平、竖直和/或沿倾斜表面延伸。衬底可以是层，其中可以包括一个或多个层，和/或可以在其上、其上方和/或其下方具有一个或多个层。层可以包括多个层。例如，互连层可以包括一个或多个导体和接触层(其中形成互连线和/或通孔触点) 和一个或多个电介质层。
如本文使用的，术语“标称/标称地”是指在产品或过程的设计阶段期间设置的用于部件或过程操作的特性或参数的期望或目标值，以及高于和/ 或低于期望值的值的范围。值的范围可能是由于制造过程或容限中的轻微变化导致的。如本文使用的，术语“大约”指示可以基于与主题半导体器件相关联的特定技术节点而变化的给定量的值。基于特定技术节点，术语“大约”可以指示给定量的值，其例如在值的10％-30％(例如，值的±10％、±20％或±30％)内变化。
如本文使用的，术语“3D存储器件”是指一种半导体器件，其在横向取向的衬底上具有竖直取向的存储单元晶体管串(在本文中被称为“存储器串”，例如NAND存储器串)，以使得所述存储器串相对于衬底在竖直方向上延伸。如本文使用的，术语“竖直/竖直地”是指标称地垂直于衬底的横向表面。
随着3D NAND存储器件持续在竖直方向上按比增大(例如，具有96 层或更多层)，由于干法刻蚀所面临的困难，对具有高深宽比的结构(例如，沟道孔和栅缝隙(GLS))实施一步刻蚀可能是不切实际的。尤其是对于如沟道孔的小尺寸图案而言，关键尺寸(CD)控制和进一步减小将有利于单元密度提高。
已经提出了通过将处于不同衬底上的外围器件和存储器阵列接合起来而制造一些3D NAND存储器件(例如，具有96层或更多层)的直接键合技术。然而，直接键合工艺可能引起成品率损失和额外成本，尤其是对于要键合三个以上的器件的情况而言。而且，针对光刻对准和叠覆、刻蚀停止能力和均匀性控制、湿法清洁等方面，直接键合工艺可能具有小的工艺容差。
在一些3D NAND存储器件(例如，128层或更多层)中，提出了一种使用半导体堆栈间插塞将存储器堆叠层的两个堆栈集成在同一衬底上的双堆栈结构。与使用直接键合技术类似，使用双堆栈结构的3D NAND存储器件面临着一些问题，例如，由于复杂的工艺集成而导致的小工艺容差、高成本和低成品率。此外，堆栈间插塞使用的半导体材料可能引入额外的电阻，其可能降低器件性能。
与上文描述的其它3D NAND存储器件相比，根据本公开的各种实施例提供的3DNAND存储器件具有更高的单元密度、更好的性能以及提高的成品率。通过将外围器件芯片和一个或多个存储器阵列器件芯片竖直堆叠，并使用内插器将它们连接起来，能够提高3DNAND存储器件的单元密度，而不引入显著的工艺困难。
例如，通过使用内插器而非直接键合将多个器件芯片接合起来，文中公开的3DNAND存储器件能够在制造期间实现更好的CD控制以及更加宽松的光刻对准/叠覆规范，由此降低成本并提高生产成品率和吞吐量。而且，与双堆栈结构中的半导体堆栈间插塞的电阻相比，使用内插器形成于不同器件芯片之间的电连接可以具有较低的电阻。此外，对于具有竖直集成的三个或更多器件芯片的器件(甚至具有更高的单元密度)而言，文中公开的使用内插器的3D NAND存储器件及其制造方法具有高工艺可扩展性。
图1示出了根据本公开的一些实施例的具有使用内插器的堆叠器件芯片的示例性3D存储器件100的截面图。如图1所示，3D存储器件100可以是包括竖直堆叠并且使用两个内插器而电气和机械地连接的一个外围器件芯片和两个存储器阵列器件芯片的三级存储器件。应当理解，内插器能够提供以任何竖直布置连接任何数量的器件芯片的灵活性，以提高3D存储器件100的单元密度和生产成品率。例如，3D存储器件100可以具有两个以上的存储器阵列器件芯片，以进一步提高单元密度，并且外围器件芯片可以设置在3D存储器件100的底部、顶部或者中间。
在一些实施例中，3D存储器件100包括外围器件芯片102、第一存储器阵列器件芯片142、以及竖直设置在外围器件芯片102和第一存储器阵列器件芯片142之间的第一内插器124，它们一起形成了如图1所示的两级存储器件170。为了电气和机械地耦合到一起，外围器件芯片102可以包括位于其顶表面上的一组芯片触点110，第一内插器124可以包括位于其顶表面上的第一组内插器触点130和位于其底表面上的第二组内插器触点120，并且第一存储器阵列器件芯片142可以包括位于其底表面上的一组芯片触点 140。根据一些实施例，应用焊料凸块来附接每一对内插器触点和芯片触点。
如图1所示，外围器件芯片102可以包括芯片衬底104、外围器件106、互连层108和芯片触点110。芯片衬底104可以包括硅(例如，单晶硅)、硅锗(SiGe)、砷化镓(GaAs)、锗(Ge)、绝缘体上硅(SOI)或者任何其它适当材料。外围器件106可以形成在芯片衬底104“上”，其中，外围器件106的全部或部分形成在芯片衬底104中(例如，低于芯片衬底104的顶表面)和/或直接形成在芯片衬底104上。外围器件106可以包括形成在芯片衬底104上的多个晶体管107。外围器件106还可以进一步包括隔离区 (例如，浅沟槽隔离(STI))和掺杂区(例如，晶体管107的源极区和漏极区)。在一些实施例中，外围器件芯片102被上下翻转，并且因而外围器件106设置在芯片衬底104下方。
在一些实施例中，外围器件106可以包括用于促进3D存储器件100的操作的任何适当数字、模拟和/或混合信号电路。例如，外围器件106可以包括页缓冲器、解码器(例如，行解码器和列解码器)、感测放大器、驱动器、电荷泵、电流或电压参考或者电路的任何有源或无源部件(例如，晶体管、二极管、电阻器或电容器)中的一者或多者。在一些实施例中，外围器件106使用互补金属氧化物半导体(CMOS)技术(又称为“CMOS 芯片”)形成在芯片衬底104上。
如图1所示，互连层108可以形成在外围器件106上方(文中称为“外围互连层”)，以向和从外围器件106传递电信号。外围互连层108可以包括多个互连，所述多个互连包括横向互连线和竖直互连接入(通孔)触点。如文中使用的，术语“互连”可以广泛地包括任何适当类型的互连，例如中间工序(MEOL)互连和后段工序(BEOL)互连。外围互连层108可以进一步包括一个或多个层间电介质(ILD)层(又称为“金属间电介质(IMD) 层”)，可以在ILD层中形成互连线和通孔触点。外围互连层108中的互连可以包括导电材料，所述导电材料包括但不限于钨(W)、钴(Co)、铜(Cu)、铝(Al)、硅化物或其任何组合。外围互连层108中的ILD层可以包括电介质材料，所述电介质材料包括但不限于氧化硅、氮化硅、氮氧化硅、低介电常数(低k)电介质或其任何组合。
应当指出，x和y轴被添加至图1，以进一步示出3D存储器件100中的部件的空间关系。芯片衬底104包括沿x方向(横向或者宽度方向)横向延伸的两个横向表面(例如，顶表面和底表面)。如文中所使用，半导体器件(例如，外围器件芯片102)的一个部件(例如，层或器件)是处于另一部件(例如，层或器件)“上”、“上方”还是“下方”是当衬底在y 方向(竖直方向或厚度方向)上被定位在半导体器件的最低平面中时，沿y 方向相对于半导体器件的衬底(例如，芯片衬底104)确定的。在本公开中将通篇采用相同的概念来描述空间关系。
如图1所示，芯片触点110可以形成在外围器件芯片102的顶表面上并且通过(例如)外围互连层108中的互连而电连接至外围器件106。芯片触点110可以向和从外围器件芯片102传递电信号。芯片触点110还可以充当用于促进外围器件芯片102和第一内插器124之间的粘附的接口。在一些实施例中，芯片触点110是包括一个或多个薄膜层的导电焊盘，所述薄膜层对(例如)焊料材料(又称为“焊料焊盘”)具有高亲合性。薄膜层可以包括诸如Al、Au、Cu、Cr、Ni、TiW或其任何组合的导体。在一些实施例中，导电焊盘具有处于大约100nm和大约1μm之间的范围内的尺寸，例如，处于100nm和1μm之间(例如，100nm、200nm、300nm、400nm、 500nm、600nm、700nm、800nm、900nm、1μm、由所述下端和这些值中的任何值所界定的任何范围、或者由这些值中的任何两个值所限定的任何范围中)的尺寸。在一些实施例中，芯片触点110是导电凸块，例如焊料焊盘上的焊料凸块(未示出)。焊料凸块材料可以包括但不限于诸如63Sn/Pb、 Cu/Sb/Ag/Sn和95.5Sn/3.8Ag/0.7Cu的合金。在一些实施例中，导电凸块具有处于大约1μm和大约100μm之间的范围内的尺寸，例如，处于1μm和 100μm之间(例如，1μm、5μm、10μm、20μm、30μm、40μm、50μm、60μm、 70μm、80μm、90μm、100μm、由所述下端和这些值中的任何值所界定的任何范围、或者由这些值中的任何两个值所限定的任何范围中)的尺寸。
内插器可以充当接口接合器件，其在形成3D存储器件的过程中带来额外的好处。例如，内插器可以具有非常光滑的表面，以使得对另一配对器件芯片的表面平滑度的要求不是那么严苛。内插器还可以充当热扩散器，以使得在接合过程期间可以均匀地施加热量。内插器还可以在3D存储器件的操作期间充当良好的热沉，由此避免器件过热。
如图1所示，3D存储器件100的第一内插器124可以包括内插器衬底 121、多个贯穿衬底通孔触点126、第一组内插器触点130以及第二组内插器触点120。第一组内插器触点130和第二组内插器触点120可以分别形成在第一内插器124的相对表面(例如，顶表面和底表面)上。在一些实施例中，第一内插器124还可以包括设置在内插器衬底121的相对表面(例如，顶表面和底表面)上的两个重新分布层122和128。在一些实施例中，第一重新分布层128形成在内插器衬底121的顶表面上，并且处于第一组内插器触点130和内插器衬底121之间。第一重新分布层128可以与第一组内插器触点130接触。在一些实施例中，第二重新分布层122形成在内插器衬底121的底表面上并且处于第二组内插器触点120和内插器衬底121之间。第二重新分布层122可以与第二组内插器触点120接触。应当理解，在一些实施例中，第一内插器124仅包括形成于内插器衬底121的顶表面或者底表面上的一个重新分布层，例如第一重新分布层128或者第二重新分布层122。应当进一步理解，在一些实施例中，第一内插器124不包括任何重新分布层。
通过使用贯穿衬底通孔触点126，电信号能够通过内插器衬底121在第一组内插器触点130和第二组内插器触点120之间竖直(沿y方向)传递。如果内插器衬底121由硅构成，那么贯穿衬底通孔触点126又被称为“贯穿硅通孔”(TSV)。每个贯穿衬底通孔触点126可以延伸通过内插器衬底 121，并且电连接至第一和第二重新分布层128和122以及第一和第二组内插器触点130和120。包括第一重新分布层128和/或第二重新分布层122 可以进一步使得电信号能够横向(例如，沿x方向)传递，并且因而从器件芯片上的不同位置键合。重新分布层122和128可以包括形成于一个或多个ILD层中的互连，以用于互连布线。
在一些实施例中，内插器衬底121包括诸如单晶硅、陶瓷、玻璃或者任何其它适当材料的材料。贯穿衬底通孔触点126可以包括填充在穿过内插器衬底121的整个厚度的通孔开口中的导电材料，例如Al、Cu、W或者任何其它适当材料。在一些实施例中，内插器触点120和130是导电焊盘，例如焊料焊盘。导电焊盘可以包括导体，包括Al、Au、Cu、Cr、Ni、TiW 或其任何组合。在一些实施例中，导电焊盘具有处于大约100nm和大约1μm 之间的范围内的尺寸，例如，处于100nm和1μm之间(例如，100nm、200nm、 300nm、400nm、500nm、600nm、700nm、800nm、900nm、1μm、由所述下端和这些值中的任何值所界定的任何范围、或者由这些值中的任何两个值所限定的任何范围中)的尺寸。在一些实施例中，内插器触点120和130 是导电凸块，例如焊料焊盘上的焊料凸块(未示出)。焊料凸块材料可以包括但不限于诸如63Sn/Pb、Cu/Sb/Ag/Sn和95.5Sn/3.8Ag/0.7Cu的合金。在一些实施例中，导电凸块具有处于大约1μm和大约100μm之间的范围内的尺寸，例如，处于1μm和100μm之间(例如，1μm、5μm、10μm、20μm、 30μm、40μm、50μm、60μm、70μm、80μm、90μm、100μm、由所述下端和这些值中的任何值所界定的任何范围、或者由这些值中的任何两个值所限定的任何范围中)的尺寸。
内插器触点120和130在图1中被示为球形形状。这用于例示，在一些实施例中，由于导电凸块的扩大的尺寸的原因，内插器触点120或130 的外观受到导电凸块的支配，即使内插器触点120或130实际上是由导电焊盘上的导电凸块形成的。除非另行指出，否则文中将导电焊盘和导电凸块的组合称为“导电凸块”。
如图1所示，一旦完成了接合过程，每个内插器触点120(例如，导电凸块)可以附接至外围器件芯片102的对应芯片触点110(例如，导电焊盘) (例如，与之牢固地熔合)。应当理解，芯片触点110是导电凸块并且内插器触点120是导电焊盘的相反方案也是可行的。由于内插器触点120和芯片触点110可以包括导体，因而内插器触点120和芯片触点110的接合能够在外围器件芯片102和第一内插器124之间形成低电阻电触点(例如，金属-金属触点)。内插器触点120和芯片触点110的接合还可以在外围器件芯片102和第一内插器124之间提供具有适当机械强度的粘合。
如图1所示，3D存储器件100的第一存储器阵列器件芯片142可以包括芯片衬底144、交替导体/电介质堆叠层152、互连层154(文中称为“阵列互连层”)、处于第一存储器阵列器件芯片142的底表面上的多个底部芯片触点140、以及处于第一存储器阵列器件芯片142的顶表面上的多个顶部芯片触点156。顶部芯片触点156和交替导体/电介质堆叠层152设置在芯片衬底144的同一侧上，并且底部芯片触点140和交替导体/电介质堆叠层 152设置在芯片衬底144的不同侧上。芯片衬底144可以包括硅(例如，单晶硅)、SiGe、GaAs、Ge、SOI或者任何其它适当材料。
在一些实施例中，交替导体/电介质堆叠层152包括多个对，每一对包括导体层和电介质层。交替导体/电介质堆叠层152可以形成在芯片衬底144 上。在一些实施例中，将第一存储器阵列器件芯片142上下翻转，并且因此交替导体/电介质堆叠层152设置在芯片衬底144下方。交替导体/电介质堆叠层152中的导体层和电介质层可以在竖直方向上交替。导体层可以包括导电材料，所述导电材料包括但不限于W、Co、Cu、Al、掺杂硅、硅化物或其任何组合。电介质层可以包括电介质材料，所述电介质材料包括但不限于氧化硅、氮化硅、氮氧化硅或其组合。如图1所示，第一存储器阵列器件芯片142还可以包括提供通往NAND存储器串150的控制栅的电连接的字线通孔触点153。每个字线通孔触点153可以使其下端与交替导体/ 电介质堆叠层152中的导体层接触，从而对第一存储器阵列器件芯片142 的字线进行单独寻址。
在一些实施例中，第一存储器阵列器件芯片142是NAND闪存存储器芯片，其中提供具有形成于芯片衬底144上的NAND存储器串150的阵列的形式的存储单元。每个NAND存储器串150可以竖直延伸通过交替导体/ 电介质堆叠层152，并且可以包括竖直串联连接的多个存储单元。竖直地 (即，沿y方向)形成存储单元的能力有效地提高了单位芯片面积的存储密度。在一些实施例中，每个NAND存储器串150包括半导体沟道和电介质层(被称为“存储器膜”)。半导体沟道可以竖直延伸通过交替导体/电介质堆叠层152，并且可以包括硅，例如非晶硅、多晶硅或者单晶硅。电介质层可以是包括隧穿层、存储层(又称为“电荷捕获/存储层”)和阻挡层的复合层。每个NAND存储器串150可以具有圆柱形状(例如，柱形形状)。根据一些实施例，半导体沟道、隧穿层、存储层和阻挡层按此顺序沿从柱的中心向外表面的方向布置。例如，隧穿层设置在交替导体/电介质堆叠层和半导体沟道之间，并且存储层设置在隧穿层和交替导体/电介质堆叠层152 之间。隧穿层可以包括氧化硅、氮化硅或其任何组合。存储层可以包括氮化硅、氮氧化硅、硅或其任何组合。阻挡层可以包括氧化硅、氮化硅、高介电常数(高k)电介质或其任何组合。
如图1所示，阵列互连层154可以设置在交替导体/电介质堆叠层152 和其中的NAND存储器串150上方。阵列互连层154可以包括形成于一个或多个ILD层中的包括互连线和通孔触点的多个互连。在一些实施例中，阵列互连层154中的互连包括本地互连(例如，位线通孔触点)，每个本地互连使其下端与对应NAND存储器串150的上端接触。在一些实施例中，阵列互连层154中的互连包括后段工序(BEOL)互连，所述后段工序互连中的至少一些使其上端与顶部芯片触点156接触。因而，BEOL互连能够提供在交替导体/电介质堆叠层152中的部件(例如，NAND存储器串150) 与顶部芯片触点156之间的电连接。
在一些实施例中，第一存储器阵列器件芯片142包括竖直延伸通过交替导体/电介质堆叠层152的一个或多个贯穿阵列触点(TAC)146。TAC 146 可以延伸通过交替导体/电介质堆叠层152的全部和芯片衬底144的至少部分。TAC 146可以使得源自于交替导体/电介质堆叠层152中的部件(例如， NAND存储器串150)的电信号被布线至底部芯片触点140和/或顶部芯片触点156。TAC 146还可以在底部芯片触点140和顶部芯片触点156之间提供电连接。例如，TAC 146的下端与底部芯片触点140接触，并且TAC 146 的上端与阵列互连层154中的互连接触。如图1所示，第一存储器阵列器件芯片142还可以包括竖直延伸通过芯片衬底144的整个厚度的贯穿衬底通孔触点147(例如，TSV)，其可以提供在交替导体/电介质堆叠层152中的部件(例如，NAND存储器串150)和底部芯片触点140之间的电连接。
顶部和底部芯片触点156和140可以通过阵列互连层154中的互连、 TAC 146和/或通过贯穿衬底通孔触点147电连接至NAND存储器串150。在一些实施例中，芯片触点140和156是导电焊盘，例如焊料焊盘。导电焊盘可以包括导体，包括Al、Au、Cu、Cr、Ni、TiW或其任何组合。在一些实施例中，导电焊盘具有处于大约100nm和大约1μm之间的范围内的尺寸，例如，处于100nm和1μm之间(例如，100nm、200nm、300nm、400nm、 500nm、600nm、700nm、800nm、900nm、1μm、由所述下端和这些值中的任何值所界定的任何范围、或者由这些值中的任何两个值所限定的任何范围中)的尺寸。在一些实施例中，芯片触点140和156是导电凸块，例如焊料焊盘上的焊料凸块(未示出)。焊料凸块材料可以包括但不限于诸如 63Sn/Pb、Cu/Sb/Ag/Sn和95.5Sn/3.8Ag/0.7Cu的合金。在一些实施例中，导电凸块具有处于大约1μm和大约100μm之间的范围内的尺寸，例如，处于 1μm和100μm之间(例如，1μm、5μm、10μm、20μm、30μm、40μm、50μm、 60μm、70μm、80μm、90μm、100μm、由所述下端和这些值中的任何值所界定的任何范围、或者由这些值中的任何两个值所限定的任何范围中)的尺寸。
如图1所示，一旦完成了接合过程，每个内插器触点130(例如，导电凸块)就可以附接至第一存储器阵列器件芯片142的对应底部芯片触点140 (例如，导电焊盘)(例如，与之牢固地熔合)。应当理解，底部芯片触点 140是导电凸块并且内插器触点130是导电焊盘的相反方案也是可行的。由于内插器触点130和底部芯片触点140可以包括导体，因而内插器触点130 和底部芯片触点140的接合能够在第一存储器阵列器件芯片142和第一内插器124之间形成低电阻电触点(例如，金属-金属触点)。内插器触点130 和底部芯片触点140的接合还可以为第一存储器阵列器件芯片142和第一内插器124之间的粘附提供适当机械强度。应当理解，在一些实施例中，首先使第一存储器阵列器件芯片142上下翻转(其中，使顶部芯片触点156 面向下朝向内插器触点130)，并且之后通过使顶部芯片触点156附接至内插器触点130而使第一存储器阵列器件芯片142与第一内插器124接合。
因此，由于外围器件芯片102和第一存储器阵列器件芯片142两者能够在第一内插器124的相对两侧上附接至第一内插器124，因而外围器件芯片102和第一存储器阵列器件芯片142能够通过第一内插器124进行电气和机械耦合，由此形成两级存储器件170。例如，源自于外围器件芯片102 中的晶体管107的电信号可以通过外围互连层108中的互连、芯片触点110、内插器触点120、重新分布层122、贯穿衬底通孔触点126、重新分布层128、内插器触点130、底部芯片触点140、TAC 146和阵列互连层154中的互连利用低电阻电触点而布线至第一存储器阵列器件芯片142中的顶部芯片触点156。此外，通过调整芯片触点110和140以及内插器触点120和130的尺寸和/或布置重新分布层122和128中的互连布线，能够显著降低集成外围器件芯片102和第一存储器阵列器件芯片142的工艺难度，例如，同时具有更好的CD控制以及放松的光刻对准和叠覆规范。
如图1所示，3D存储器件100可以是竖直集成了一个外围器件芯片(例如，外围器件芯片102)和多个存储器阵列器件芯片(例如，竖直堆叠的多个存储器阵列器件芯片)的多级存储器件。在一些实施例中，3D存储器件 100是具有堆叠在两级存储器件170的顶部的第二存储器阵列器件芯片172 的三级存储器件。第二存储器阵列器件芯片172能够通过竖直设置在第一和第二存储器阵列器件芯片142和172之间的第二内插器164而电气和机械耦合至两级存储器件170。
与第一存储器阵列器件芯片142类似，第二存储器阵列器件芯片172 可以包括芯片衬底184、交替导体/电介质堆叠层192、均竖直延伸通过交替导体/电介质堆叠层192的NAND存储器串190的阵列、多个字线通孔触点 193、多个TAC 186、多个贯穿衬底通孔触点187和阵列互连层194。为了附接至第二内插器164，第二存储器阵列器件芯片172还可以包括处于底表面上的一组底部芯片触点196。此外或者任选地，第二存储器阵列器件芯片 172可以包括处于顶表面上的一组顶部芯片触点196，其将被附接至另一内插器(未示出)，以进一步增加3D存储器件100的存储器阵列级。在一些实施例中，第二存储器阵列芯片172是第一存储器阵列器件芯片142的复制，以提高单元密度。因而，将容易地认识到第一和第二存储器阵列器件芯片142和172两者中的类似结构的细节(例如，材料、制造工艺、功能等)，并且将不再对其重复描述。
与第一内插器124类似，第二内插器164可以包括内插器衬底171、形成于内插器衬底171的相对表面上的两个重新分布层162和168、以及多个贯穿衬底通孔触点176。为了附接至第一和第二存储器阵列器件芯片142和 172，第二内插器164还可以包括设置在第二内插器162的相对表面(例如，顶表面和底表面)上的两组内插器触点160和180。内插器触点160和180 可以分别附接至第一存储器阵列器件芯片142的顶部芯片触点156和第二存储器阵列器件芯片172的底部芯片触点196。在一些实施例中，第二内插器164是第一内插器124的复制，以提高竖直集成能力。因而，将容易地认识到第一和第二内插器124和164两者中的类似结构的细节(例如，材料、制造工艺、功能等)，并且将不再对其做出重复描述。
应当理解，使用内插器的器件芯片接合过程是可重复过程。通过更多循环，能够形成三级以上的3D存储器件100。还应当理解，每一级的相对竖直位置不限于图1所示的示例。例如，外围器件芯片102可以是多级存储器件的底部级(如图1所示)、顶部级或者任何中间级。还应当理解，每一级的取向不限于图1所示的示例。例如，在多级存储器件中可以使外围器件芯片102、第一存储器阵列器件芯片142和/或第二存储器阵列器件芯片172上下翻转。也就是说，在多级存储器件中可以使器件芯片的有源侧 (例如，形成外围器件或者存储器阵列器件的侧)面向上或者面向下。在外围器件芯片102处于多级存储器件中的中间级和/或使外围器件芯片102 上下翻转时，能够在芯片衬底104的附有贯穿衬底通孔触点的背面上形成额外的芯片触点(未示出)，以用于背面互连布线。
例如，图2A-图2H示出了根据各种实施例的具有使用内插器的堆叠的外围器件芯片和存储器阵列器件芯片的示例性3D存储器件200的示意图。如图2所示，能够从两级3D存储器件200得到八种不同器件芯片布置。3D 存储器件200可以包括外围器件芯片202、内插器208和存储器阵列器件芯片212。在一些实施例中，外围器件芯片202进一步包括在上面形成外围器件(例如，晶体管)的有源侧206以及具有芯片衬底的无源侧204。类似地，根据一些实施例，存储器阵列器件芯片212进一步包括在上面形成存储器阵列器件(例如，NAND存储器串)的有源侧216和具有芯片衬底的无源侧214。内插器208可以在两侧包含相同的图案，因而其翻转将不带来新的变化。外围器件芯片202和存储器阵列器件芯片212可以分别附接至内插器208的相对两侧，并由此通过内插器208进行电气和机械耦合，以形成 3D存储器件200，上文联系图1对此给出了详细描述。
在图2A中，接合的外围器件芯片202和存储器阵列器件芯片212均使其有源侧216和206面向上，并使其无源侧214和204面向下。外围器件芯片202设置在存储器阵列器件芯片212下方。利用图2A作为基础布置，通过使存储器阵列器件芯片212上下翻转形成图2B中的3D存储器件200；通过使外围器件芯片202上下翻转形成图2C中的3D存储器件200；通过使外围器件芯片202和存储器阵列器件芯片212两者都上下翻转形成图2D 中的3D存储器件200。此外，图2E-图2H中的3D存储器件200分别是通过从图2A-图2D中的3D存储器件200调换存储器阵列器件芯片212和外围器件芯片202的竖直位置而形成的。
在图2A-图2H的每者中，3D存储器件200的每个触点210包括形成于外围器件芯片202或存储器阵列器件芯片212的外表面上的芯片触点以及形成于内插器208的任一侧的外表面上的内插器触点。芯片触点和内插器触点可以被附接(例如，熔合)，以形成触点210。应当理解，触点210 要么具有两个附接的导电凸块的形式，要么具有一个导电焊盘附接至一个导电凸块的形式。图2A-图2H中的触点210的球形形状是出于简洁的缘故，并且不限制所附接的芯片触点和内插器触点的可行类型。
在一些实施例中，内插器可以用于沿竖直方向仅附接存储器阵列器件芯片。例如，图3A-图3D示出了根据各种实施例的具有使用内插器的堆叠存储器阵列器件芯片的示例性3D存储器件300的示意图。如图3所示，可以从两级3D存储器件300(省略外围器件)得到四种器件芯片布置。应当理解，可以通过任何其它适当方案，例如通过直接键合、形成在存储器阵列器件芯片的同一芯片衬底上、或者横向芯片集成来将外围器件电气和机械耦合至堆叠的存储器阵列器件芯片。
3D存储器件300可以包括第一存储器阵列器件芯片302、内插器308 和第二存储器阵列器件芯片312。在一些实施例中，第一存储器阵列器件芯片302进一步包括在上面形成存储器阵列器件(例如，NAND存储器串) 的有源侧306以及具有芯片衬底的无源侧304。类似地，根据一些实施例，第二存储器阵列器件芯片312进一步包括在上面形成存储器阵列器件(例如，NAND存储器串)的有源侧316和具有芯片衬底的无源侧314。内插器 308可以在两侧包含相同的图案，因而其翻转将不带来新的变化。第一存储器阵列器件芯片302和第二存储器阵列器件芯片312可以分别附接至内插器308的相对两侧，并由此通过内插器308进行电气和机械耦合，以形成 3D存储器件300，上文联系图1对此给出了详细描述。
在图3A中，接合的第一和第二存储器阵列器件芯片302和312均使其有源侧316和306面向上，并且使其无源侧314和304面向下。使用图3A 作为基础布置，通过使第二存储器阵列器件芯片312上下翻转形成图3B中的3D存储器件300；通过使第一存储器阵列器件芯片302上下翻转形成图 3C中的3D存储器件300；通过使第一和第二存储器阵列器件芯片302和312两者上下翻转形成图3D中的3D存储器件300。
在图3A-图3D中的每者中，3D存储器件300的每个触点310包括形成于第一或第二存储器阵列器件芯片302或312的外表面上的芯片触点以及形成于内插器308的任一侧的外表面上的内插器触点。芯片触点和内插器触点可以被附接(例如，熔合)，以形成触点310。应当理解，触点310 要么具有两个附接的导电凸块的形式，要么具有一个导电焊盘附接至一个导电凸块的形式。图3A-图3D中的触点310的球形形状是出于简洁的缘故，并且不限制附接的芯片触点和内插器触点的可行类型。
图4A-图4D示出了根据本公开的一些实施例的用于形成外围器件芯片的示例性制造过程。图8是根据一些实施例的用于形成外围器件芯片的示例性方法800的流程图。图4A-图4D和图8中描绘的外围器件芯片的示例包括图1所描绘的外围器件芯片102。将一起描述图4A-图4D以及图8。应当理解，方法800中所示的操作不是穷举的，并且也可以在所示操作中的任何操作之前、之后或者之间执行其它操作。此外，所述操作中的一些可以是同时执行的，或者可以是按照与图8所示不同的顺序执行的。
参考图8，方法800开始于操作802，其中，在芯片衬底上形成外围器件。芯片衬底可以是硅衬底。如图4A中所示，在硅衬底402上形成外围器件。外围器件可以包括形成于硅衬底402上的多个晶体管404。晶体管404 可以是通过多个工艺步骤形成的，所述工艺步骤包括但不限于光刻、干法/ 湿法刻蚀、薄膜沉积、热生长、注入、化学机械抛光(CMP)或其任何组合。在一些实施例中，通过离子注入和/或热扩散在硅衬底402中形成掺杂区406，其起着(例如)晶体管404的源极区和/或漏极区的作用。在一些实施例中，还通过湿法/干法刻蚀和薄膜沉积在硅衬底402中形成隔离区408 (例如，STI)。
方法800进行至操作804，如图8所示，其中，在外围器件上方形成互连层(例如，外围互连层)。外围互连层可以包括形成于一个或多个ILD层中的多个互连。如图4B所示，外围互连层416可以形成在硅衬底402上以及晶体管404上方。外围互连层416可以包括处于多个ILD层中的互连，所述互连包括中间工序和/或后段工序的互连线412和通孔触点414，以与外围器件(例如，晶体管404)进行电连接。
在一些实施例中，外围互连层416包括通过多种工艺形成的多个ILD 层以及位于其中的互连。例如，互连线412和通孔触点414可以包括通过一种或多种薄膜沉积工艺沉积的导电材料，所述工艺包括但不限于CVD、 PVD、ALD、电镀、无电镀或其任何组合。形成互连线412和通孔触点414 的制造工艺还可以包括光刻、CMP、湿法/干法刻蚀或者任何其它适当工艺。 ILD层可以包括通过一种或多种薄膜沉积工艺沉积的电介质材料，所述工艺包括但不限于CVD、PVD、ALD或其任何组合。图4B中所示的ILD层和互连可以被统称为“互连层”(例如，外围互连层416)。
方法800进行至操作806，如图8所示，其中，在外围器件芯片的外表面(例如，顶表面)上形成芯片触点(例如，顶部芯片触点)。如图4C所示，在外围互连层416的顶表面上形成一组顶部芯片触点420A。顶部芯片触点420A可以通过外围互连层416中的互连(例如，通孔触点414)与外围器件(例如，晶体管404)电连接。在一些实施例中，每个顶部芯片触点 420A包括具有一个或多个导体膜的导电焊盘，例如，焊料焊盘。导体膜可以包括但不限于Al、Au、Cu、Cr、Ni、TiW或其任何组合。导电焊盘可以是通过一种或多种薄膜沉积工艺沉积的，所述工艺包括但不限于CVD、 PVD、ALD、电镀、无电镀或其任何组合。形成导电焊盘的制造工艺还可以包括光刻、湿法/干法刻蚀等。
在一些实施例中，如图4D所示，在外围互连层416的顶表面上形成一组顶部芯片触点420B。每个顶部芯片触点420B可以包括导电凸块，例如，沉积在焊料焊盘上的焊料导体(统称为“焊料凸块”)。焊料凸块材料可以包括但不限于诸如63Sn/Pb、Cu/Sb/Ag/Sn和95.5Sn/3.8Ag/0.7Cu的合金。焊料导体可以是通过大块膜沉积工艺沉积的，所述工艺包括但不限于CVD、 PVD、电镀、无电镀或其任何组合。然后可以实施热回流工艺，以帮助形成圆化形状的焊料凸块。形成导电凸块的制造工艺还可以包括光刻、湿法/ 干法刻蚀等。
图5A-图5G示出了根据本公开的一些实施例的用于形成存储器阵列器件芯片的示例性制造过程。图9是根据一些实施例的用于形成存储器阵列器件芯片的示例性方法900的流程图。图5A-图5G和图9中描绘的存储器阵列器件芯片的示例包括图1中描绘的第一和第二存储器阵列器件芯片142 和172。将一起描述图5A-图5G以及图9。应当理解，方法900中所示的操作不是穷举的，并且也可以在所示操作中的任何操作之前、之后或者之间执行其它操作。此外，所述操作中的一些可以是同时执行的，或者可以是按照与图9所示不同的顺序执行的。
参考图9，方法开始于操作902，其中，在芯片衬底上形成交替导体/ 电介质堆叠层。如图5A所示，在硅衬底502上形成第一电介质层504和第二电介质层506的对(文中称为“电介质层对”)。堆叠的电介质层对可以形成交替电介质堆叠层508。交替电介质堆叠层508可以包括第一电介质层 504和不同于第一电介质层504的第二电介质层506的交替堆叠层。在一些实施例中，每个电介质层对包括一层氮化硅和一层氧化硅。在一些实施例中，第一电介质层504可以均具有相同厚度或者可以具有不同厚度。类似地，第二电介质层506可以均具有相同厚度或者可以具有不同厚度。交替电介质堆叠层508可以是通过一种或多种薄膜沉积工艺形成的，所述工艺包括但不限于CVD、PVD、ALD或其任何组合。
在一些实施例中，交替电介质堆叠层508可以被替换为多个导体/电介质层对，即，导体层(例如，多晶硅)和电介质层(例如，氧化硅)的交替堆叠层。如图5B所示，交替电介质堆叠层508的每个第一电介质层504 可以被替换为导体层510，由此形成交替导体/电介质堆叠层518中的多个导体/电介质层对。利用导体层510替换第一电介质层504可以是通过相对于第二电介质层506有选择地对第一电介质层504进行湿法/干法刻蚀并利用导体层510填充所述结构而执行的。导体层510可以包括导电材料，所述导电材料包括但不限于W、Co、Cu、Al、掺杂硅、多晶硅、硅化物或其任何组合。可以通过诸如CVD、ALD、任何其它适当工艺或其任何组合的薄膜沉积工艺填充导体层510。
方法900进行至操作904，如图9所示，其中，在芯片衬底上形成多个 NAND存储器串。每个NAND存储器串可以竖直延伸通过交替导体/电介质堆叠层。如图5B所示，在硅衬底502上形成多个NAND存储器串512。在一些实施例中，形成NAND存储器串512的制造过程包括形成竖直延伸通过交替导体/电介质堆叠层518的半导体沟道。在一些实施例中，形成NAND存储器串512的制造过程还包括在半导体沟道和交替导体/电介质堆叠层 518之间形成电介质层。电介质层可以是复合电介质层，例如，包括但不限于隧穿层、存储层和阻挡层的多个电介质层的组合。隧穿层可以包括电介质材料，所述电介质材料包括但不限于氧化硅、氮化硅、氮氧化硅或其任何组合。存储层可以包括用于存储电荷以用于存储器操作的材料。存储层材料可以包括但不限于氮化硅、氮氧化硅、氧化硅和氮化硅的组合、或其任何组合。半导体沟道和电介质层(包括其中的隧穿层和存储层)可以是通过诸如ALD、CVD、PVD、任何其它适当工艺或其任何组合的工艺形成的。
在一些实施例中，操作904进一步包括形成一个或多个TAC，每个TAC 竖直延伸通过交替导体/电介质堆叠层。如图5B所示，TAC 514被形成为竖直延伸通过交替导体/电介质堆叠层518以及硅衬底502的至少部分。在一些实施例中，形成TAC 514的制造过程包括通过干法/湿法刻蚀工艺形成穿过交替导体/电介质堆叠层518的竖直开口，随后利用导电材料和用于隔离目的的其它材料填充所述开口。TAC 514可以包括导电材料，所述导电材料包括但不限于W、Co、Cu、Al、掺杂硅、硅化物或其任何组合。可以通过ALD、CVD、PVD、电镀、任何其它适当工艺、或其任何组合利用导电材料和其它材料填充TAC 514的开口。
在一些实施例中，操作904进一步包括形成一个或多个贯穿衬底通孔触点，每个贯穿衬底通孔触点竖直延伸通过芯片衬底。贯穿衬底通孔触点可以与交替导体/电介质堆叠层中的部件(例如，NAND存储器串)接触。如图5B所示，形成穿过硅衬底502并且与NAND存储器串512接触的TSV 522。在一些实施例中，形成TSV 522的制造过程包括通过干法/湿法刻蚀工艺形成穿过硅衬底502的竖直开口，随后利用导电材料和用于隔离目的的其它材料填充所述开口。TSV 522可以包括导电材料，所述导电材料包括但不限于W、Co、Cu、Al、掺杂硅、硅化物或其任何组合。可以通过ALD、 CVD、PVD、电镀、任何其它适当工艺、或其任何组合利用导电材料和其它材料填充TSV 522的开口。
方法900进行至操作906，如图9所示，其中，在NAND存储器串上方形成互连层(例如，阵列互连层)。如图5C所示，在交替导体/电介质堆叠层518和其中的NAND存储器串512上方形成阵列互连层528。阵列互连层528可以包括处于一个或多个ILD层中的包括互连线和通孔触点的互连526，以用于向和从NAND存储器串512传递电信号。
在一些实施例中，阵列互连层528包括通过多种工艺形成的多个ILD 层和其中的互连526。例如，互连526可以包括通过一种或多种薄膜沉积工艺沉积的导电材料，所述工艺包括但不限于CVD、PVD、ALD、电镀、无电镀或其任何组合。形成互连526的制造工艺还可以包括光刻、CMP、湿法/干法刻蚀、或者任何其它适当工艺。ILD层可以包括通过一种或多种薄膜沉积工艺沉积的电介质材料，所述工艺包括但不限于CVD、PVD、ALD 或其任何组合。图5C中所示的ILD层和互连526可以被统称为“互连层” (例如，阵列互连层528)。
方法900进行至操作908，如图9所示，其中，在存储器阵列器件芯片的一个或两个外表面(例如，顶表面和/或底表面)上形成芯片触点。可以在芯片衬底的正面形成第一组芯片触点，并且可以在芯片衬底的背面形成第二组芯片触点。每个芯片触点可以是导电焊盘(例如，焊料焊盘)或者导电凸块(例如，焊料凸块)。如图5D所示，底部导电焊盘532A可以形成在存储器阵列器件芯片的底表面上，例如，形成在硅衬底502的背面。在一些实施例中，底部导电焊盘532A分别与TAC 514和TSV 522接触。如图5E所示，顶部导电焊盘534A可以形成在存储器阵列器件芯片的顶表面上，例如，形成在芯片衬底502的正面并且处于阵列互连层528上。在一些实施例中，顶部导电焊盘534A分别与阵列互连层528中的互连526接触。在一些实施例中，形成导电焊盘532A和534A的制造过程包括形成一个或多个导体膜，所述导体膜可以包括导电材料，所述导电材料包括但不限于Al、Au、Cu、Cr、Ni、TiW或其任何组合。导体膜可以通过PVD、 CVD、ALD、电镀、无电镀、任何其它适当工艺、或其任何组合来形成。
替代地，如图5F所示，底部导电凸块532B可以形成在存储器阵列器件芯片的底表面上，例如，形成在硅衬底502的背面。在一些实施例中，底部导电凸块532B分别与TAC 514和TSV 522接触。如图5G所示，顶部导电凸块534B可以形成在存储器阵列器件芯片的顶表面上，例如，形成在芯片衬底502的正面以及阵列互连层528上。在一些实施例中，顶部导电凸块534B分别与阵列互连层528中的互连526接触。在一些实施例中，形成导电凸块532B和534B的制造过程包括形成焊料焊盘，并且之后形成焊料凸块。焊料凸块可以包括焊料材料，所述焊料材料包括但不限于63Sn/Pb、 Cu/Sb/Ag/Sn和95.5Sn/3.8Ag/0.7Cu。焊料凸块可以通过PVD、CVD、电镀、无电镀、任何其它适当工艺或其任何组合形成。在一些实施例中，在沉积焊料材料之后实施热回流。
图6A-图6F示出了根据本公开的一些实施例的用于形成内插器的示例性制造过程。图10是根据一些实施例的用于形成内插器的示例性方法1000 的流程图。图6A-图6F和图10中描绘的内插器的示例包括图1中描绘的第一和第二内插器124和164。将一起描述图6A-图6F以及图10。应当理解，方法1000中所示的操作不是穷举的，并且也可以在所示操作中的任何操作之前、之后或者之间执行其它操作。此外，所述操作中的一些可以是同时执行的，或者可以是按照与图10所示不同的顺序执行的。
参考图10，方法1000开始于操作1002，其中，在内插器衬底的一侧 (例如，顶侧)形成第一重新分布层和第一组内插器触点。第一组内插器触点可以是导电焊盘或者导电凸块。如图6A所示，内插器衬底602可以由包括但不限于硅(例如，单晶硅)、玻璃和陶瓷的材料制成。第一重新分布层604可以形成在内插器衬底602的顶表面上，并且可以包括形成在一个或多个ILD层中的诸如互连线和通孔触点的互连，以使得电信号能够横向传递而不互相短路。互连可以包括导电材料，所述导电材料包括但不限于 W、Co、Cu、Al、硅化物或其任何组合。ILD层可以包括通过一种或多种薄膜沉积工艺沉积的电介质材料，所述工艺包括但不限于CVD、PVD、ALD 或其任何组合。ILD层和互连可以被统称为“重新分布层”(例如，第一重新分布层604)。
第一组导电焊盘606可以在内插器衬底602的顶侧形成在第一重新分布层604上。导电焊盘606可以与第一重新分布层604中的互连接触。在一些实施例中，导电焊盘606是包括多个导体膜的焊料焊盘，所述导体膜由包括但不限于Al、Au、Cu、Cr、Ni、TiW或其任何组合的导电材料制成。导体膜可以通过PVD、CVD、ALD、电镀、无电镀、任何其它适当工艺或其任何组合形成。
方法1000进行至操作1004，其中，形成均延伸通过内插器衬底的通孔触点(例如，TSV，如果内插器衬底是硅衬底的话)。如图6B所示，形成通过内插器衬底602的整个厚度并且与第一重新分布层604中的互连接触的多个通孔触点610(被称为“贯穿衬底通孔触点”)。在一些实施例中，如果不用第一重新分布层604，那么贯穿衬底通孔触点610与导电焊盘606直接电接触。贯穿衬底通孔触点610可以包括导电材料，所述导电材料包括但不限于Al、Cu和W。在一些实施例中，形成贯穿衬底通孔触点610的工艺包括光刻、干法/湿法刻蚀、沉积等。
方法1000进行至操作1006，其中，在内插器衬底的另一侧(例如，底侧)形成第二重新分布层和第二组内插器触点。第二组内插器触点可以是导电焊盘或者导电凸块。第二重新分布层可以通过贯穿衬底通孔触点电连接至第一重新分布层。如图6C所示，第二重新分布层620可以形成在内插器衬底602的底表面上，并且可以包括形成于一个或多个ILD层中的诸如互连线和通孔触点的互连，以使得电信号能够横向传递而不相互短路。第二重新分布层620中的互连可以与贯穿衬底通孔触点610接触。互连可以包括导电材料，所述导电材料包括但不限于W、Co、Cu、Al、硅化物或其任何组合。ILD层可以包括通过一种或多种薄膜沉积工艺沉积的电介质材料，所述工艺包括但不限于CVD、PVD、ALD或其任何组合。ILD层和互连可以被统称为“重新分布层”(例如，第二重新分布层620)。
第二组导电焊盘622可以在内插器衬底602的底侧形成在第二重新分布层620上。导电焊盘622可以与第二重新分布层620中的互连接触。因而，处于内插器衬底602的相对侧上的第一组导电焊盘606和第二组导电焊盘622可以通过第一重新分布层604和第二重新分布层620以及贯穿衬底通孔触点610电连接。在一些实施例中，导电焊盘622是包括多个导体膜的焊料焊盘，所述导体膜由包括但不限于Al、Au、Cu、Cr、Ni、TiW或其任何组合的导电材料制成。导体膜可以通过PVD、CVD、ALD、电镀、无电镀、任何其它适当工艺、或其任何组合来形成。
如上文所述，处于内插器的任一侧上的内插器触点可以是导电焊盘或导电凸块。在一些实施例中，处于内插器衬底602的顶侧的每个导电焊盘606进一步包括导电凸块(例如，焊料凸块)，从而将其自身转化成导电凸块630，如图6D所示。在一些实施例中，处于内插器衬底602的底侧的每个导电焊盘622进一步包括导电凸块(例如，焊料凸块)，从而将其自身转化成导电凸块640，如图6E所示。在一些实施例中，处于内插器衬底602 的顶侧和底侧两者上的导电焊盘606和622均进一步包括导电凸块(例如，焊料凸块)，从而分别将其自身转化成导电凸块630和640，如图6F所示。焊料凸块可以包括焊料材料，所述焊料材料包括但不限于63Sn/Pb、 Cu/Sb/Ag/Sn和95.5Sn/3.8Ag/0.7Cu。焊料凸块可以通过PVD、CVD、电镀、无电镀、任何其它适当工艺、或其任何组合形成。在一些实施例中，在沉积焊料材料之后实施热回流。
在形成器件芯片(例如，外围器件芯片和存储器阵列器件芯片)和内插器之后，可以使用内插器通过接合工艺使器件芯片竖直接合。在一些实施例中，第一器件芯片的外表面(例如，顶表面或底表面)上的芯片触点附接至内插器的一侧上的内插器触点，并且第二器件芯片的外表面(例如，顶表面或底表面)上的芯片触点附接至内插器另一侧上的内插器触点。结果，第一器件芯片和第二器件芯片使用内插器在竖直方向上电气和机械耦合。图7A-图7B示出了根据一些实施例的用于将外围器件芯片和存储器件阵列器件芯片附接至内插器的示例性制造过程。
如图7A所示，内插器704被定位为略高于外围器件芯片702的位置，以使得内插器704的底表面上的内插器触点708中的每者与外围器件芯片 702的顶表面上的对应芯片触点706对准。之后，使内插器704下降，直到大部分内插器触点708与芯片触点706物理接触为止。在一些实施例中，实施诸如热压的热工艺，以通过形成于内插器触点708和芯片触点706之间的焊料接合将内插器704接合至外围器件芯片702。第一接合过程形成了图7B所示的复合器件714。可以重复相同的接合过程，以将存储器阵列器件芯片710的底部芯片触点712附接至内插器704的顶表面上的内插器触点709。因此，存储器阵列器件芯片710通过形成于内插器触点709和底部芯片触点712之间的焊料接合而接合至复合器件714。在执行了两个接合过程之后形成了两级存储器件716。在一些实施例中，如果配对触点(例如，内插器触点或者芯片触点)之一包括导电焊盘(例如，焊料焊盘)，那么另一个配对触点包括导电凸块(例如，焊料凸块)，以便于接合过程。
对特定实施例的上述说明因此将完全揭示本公开的一般性质，使得他人能够通过运用本领域技术范围内的知识容易地对这种特定实施例进行修改和/或调整以用于各种应用，而不需要过度实验，并且不脱离本公开的一般概念。因此，基于本文呈现的教导和指导，这种调整和修改旨在处于所公开的实施例的等同物的含义和范围内。应当理解，本文中的措辞或术语是用于说明的目的，而不是为了进行限制，从而本说明书的术语或措辞将由技术人员按照所述教导和指导进行解释。
上文已经借助于功能构建块描述了本公开的实施例，功能构建块例示了指定功能及其关系的实施方式。在本文中出于方便描述的目的任意地限定了这些功能构建块的边界。可以限定替代的边界，只要适当执行指定的功能及其关系即可。
发明内容和摘要部分可以阐述发明人所设想的本公开的一个或多个示例性实施例，但未必是所有示例性实施例，并且因此，并非旨在通过任何方式限制本公开和所附权利要求。
本公开的广度和范围不应受任何上述示例性实施例的限制，并且应当仅根据以下权利要求书及其等同物来进行限定。

Claims (36)

1.一种三维(3D)存储器件，包括：
第一器件芯片，其包括：
外围器件；以及
第一芯片触点，其设置在所述第一器件芯片的表面上并且电连接至所述外围器件；
第二器件芯片，包括：
交替导体/电介质堆叠层以及竖直延伸通过所述交替导体/电介质堆叠层的存储器串；以及
第二芯片触点，其设置在所述第二器件芯片的表面上并且电连接至所述存储器串；以及
竖直设置在所述第一器件芯片和所述第二器件芯片之间的内插器，
并且其中，所述第一器件芯片的所述外围器件和所述第二器件芯片是竖直堆叠并使用所述内插器而电气和机械地连接的。
2.根据权利要求1所述的3D存储器件，其中，所述内插器包括：
内插器衬底；
设置在所述内插器的第一表面上的第一内插器触点；以及
第二内插器触点，其设置在所述内插器的与所述第一表面相对的第二表面上并且通过所述内插器衬底电连接至所述第一内插器触点，
其中，所述第一内插器触点附接至所述第一芯片触点，并且所述第二内插器触点附接至所述第二芯片触点。
3.根据权利要求2所述的3D存储器件，其中，所述第一芯片触点和所述第二芯片触点的至少其中之一或者所述第一内插器触点和所述第二内插器触点的至少其中之一包括导电凸块。
4.根据权利要求3所述的3D存储器件，其中，所述导电凸块的尺寸处于大约1μm和大约100μm之间。
5.根据权利要求2所述的3D存储器件，其中，所述第一芯片触点和所述第二芯片触点的至少其中之一或者所述第一内插器触点和所述第二内插器触点的至少其中之一包括导电焊盘。
6.根据权利要求5所述的3D存储器件，其中，所述导电焊盘的尺寸处于大约100nm和大约1μm之间。
7.根据权利要求2-6中的任何一项所述的3D存储器件，其中，所述第一芯片触点和所述第二芯片触点以及所述第一内插器触点和所述第二内插器触点中的每者包括导体。
8.根据权利要求2-7中的任何一项所述的3D存储器件，其中，所述内插器进一步包括：
重新分布层，其设置在所述内插器衬底上并且与所述第一内插器触点和所述第二内插器触点之一接触；以及
第一通孔触点，其延伸通过所述内插器衬底并且电连接至所述重新分布层以及所述第一内插器触点和所述第二内插器触点中的另一个，以使所述第一内插器触点和所述第二内插器触点通过所述重新分布层和所述第一通孔触点电连接。
9.根据权利要求2-8中的任何一项所述的3D存储器件，其中，所述第二器件芯片进一步包括竖直延伸通过所述交替导体/电介质堆叠层的第二通孔触点，所述第二通孔触点包括与所述第二芯片触点接触的第一端。
10.根据权利要求9所述的3D存储器件，其中，所述第二器件芯片进一步包括与所述第二通孔触点的第二端接触的互连层。
11.根据权利要求1-10中的任何一项所述的3D存储器件，其中，所述第二芯片触点和所述存储器串设置在上面形成了所述交替导体/电介质堆叠层的芯片衬底的不同侧上。
12.根据权利要求1-10中的任何一项所述的3D存储器件，其中，所述第二芯片触点和所述存储器串设置在上面形成了所述交替导体/电介质堆叠层的芯片衬底的同一侧上。
13.根据权利要求1-12中的任何一项所述的3D存储器件，其中，所述第一芯片触点和所述外围器件设置在上面形成了所述外围器件的芯片衬底的不同侧上。
14.根据权利要求1-12中的任何一项所述的3D存储器件，其中，所述第一芯片触点和所述外围器件设置在上面形成了所述外围器件的芯片衬底的同一侧上。
15.根据权利要求1-14中的任何一项所述的3D存储器件，还包括：
第三器件芯片，其包括：
另一交替导体/电介质堆叠层以及竖直延伸通过所述另一交替导体/电介质堆叠层的另一存储器串；以及
第三芯片触点，其设置在所述第三器件芯片的表面上并且电连接至所述另一存储器串；以及
另一内插器，其竖直设置在所述第三器件芯片与所述第一器件芯片和所述第二器件芯片中的一个之间，所述另一内插器包括：
另一内插器衬底；
第三内插器触点，其设置在所述另一内插器的第一表面上；以及
第四内插器触点，其设置在所述另一内插器的与所述第一表面相对的第二表面上并且通过所述另一内插器衬底电连接至所述第三内插器触点，
其中，所述第一器件芯片和所述第二器件芯片中的所述一个进一步包括设置在所述第一器件芯片和所述第二器件芯片中的所述一个的另一表面上的第四芯片触点；并且
所述第三内插器触点附接至所述第三芯片触点，并且所述第四内插器触点附接至所述第四芯片触点。
16.一种三维(3D)存储器件，包括：
第一器件芯片，其包括：
第一交替导体/电介质堆叠层以及竖直延伸通过所述第一交替导体/电介质堆叠层的第一存储器串；以及
第一芯片触点，其设置在所述第一器件芯片的表面上并且电连接至所述第一存储器串；
第二器件芯片，包括：
第二交替导体/电介质堆叠层以及竖直延伸通过所述第二交替导体/电介质堆叠层的第二存储器串；以及
第二芯片触点，其设置在所述第二器件芯片的表面上并且电连接至所述第二存储器串；以及
竖直设置在所述第一器件芯片和所述第二器件芯片之间的内插器，
并且其中，所述第一器件芯片和所述第二器件芯片是竖直堆叠并使用所述内插器而电气和机械地连接的。
17.根据权利要求16所述的3D存储器件，其中，所述内插器包括：
内插器衬底；
设置在所述内插器的第一表面上的第一内插器触点；以及
第二内插器触点，其设置在所述内插器的与所述第一表面相对的第二表面上并且通过所述内插器衬底电连接至所述第一内插器触点，
其中，所述第一内插器触点附接至所述第一芯片触点，并且所述第二内插器触点附接至所述第二芯片触点。
18.根据权利要求17所述的3D存储器件，其中，所述第一芯片触点和所述第二芯片触点的至少其中之一或者所述第一内插器触点和所述第二内插器触点的至少其中之一包括导电凸块。
19.根据权利要求18所述的3D存储器件，其中，所述导电凸块的尺寸处于大约1μm和大约100μm之间。
20.根据权利要求17所述的3D存储器件，其中，所述第一芯片触点和所述第二芯片触点的至少其中之一或者所述第一内插器触点和所述第二内插器触点的至少其中之一包括导电焊盘。
21.根据权利要求20所述的3D存储器件，其中，所述导电焊盘的尺寸处于大约100nm和大约1μm之间。
22.根据权利要求17-21中的任何一项所述的3D存储器件，其中，所述第一芯片触点和所述第二芯片触点以及所述第一内插器触点和所述第二内插器触点中的每者包括导体。
23.根据权利要求17-22中的任何一项所述的3D存储器件，其中，所述内插器进一步包括：
重新分布层，其设置在所述内插器衬底上并且与所述第一内插器触点和所述第二内插器触点之一接触；以及
第一通孔触点，其延伸通过所述内插器衬底并且电连接至所述重新分布层以及所述第一内插器和所述第二内插器中的另一个，以使所述第一内插器触点和所述第二内插器触点通过所述重新分布层和所述第一通孔触点电连接。
24.根据权利要求16-23中的任何一项所述的3D存储器件，其中，所述第一器件芯片和所述第二器件芯片的至少其中之一进一步包括竖直延伸通过对应的第一交替导体/电介质堆叠层或第二交替导体/电介质堆叠层的第二通孔触点，所述第二通孔触点包括与对应的第一芯片触点或第二芯片触点接触的第一端。
25.根据权利要求24所述的3D存储器件，其中，所述第一器件芯片和所述第二器件芯片的至少其中之一进一步包括与所述第二通孔触点的第二端接触的互连层。
26.根据权利要求16-25中的任何一项所述的3D存储器件，其中，所述第二芯片触点和所述第二存储器串设置在上面形成了所述第二交替导体/电介质堆叠层的芯片衬底的不同侧上。
27.根据权利要求16-25中的任何一项所述的3D存储器件，其中，所述第二芯片触点和所述第二存储器串设置在上面形成了所述第二交替导体/电介质堆叠层的芯片衬底的同一侧上。
28.根据权利要求16-25中的任何一项所述的3D存储器件，其中，所述第一芯片触点和所述第一存储器串设置在上面形成了所述第一交替导体/电介质堆叠层的芯片衬底的不同侧上。
29.根据权利要求16-25中的任何一项所述的3D存储器件，其中，所述第一芯片触点和所述第一存储器串设置在上面形成了所述第一交替导体/电介质堆叠层的芯片衬底的同一侧上。
30.根据权利要求16-29中的任何一项所述的3D存储器件，还包括：
第三器件芯片，包括：
外围器件；以及
第三芯片触点，其设置在所述第三器件芯片的表面上并且电连接至所述外围器件；以及
另一内插器，其竖直设置在所述第三器件芯片与所述第一器件芯片和所述第二器件芯片中的一个之间，所述另一内插器包括：
另一内插器衬底；
设置在所述另一内插器的第一表面上的第三内插器触点；以及
第四内插器触点，其设置在所述另一内插器的与所述第一表面相对的第二表面上并且通过所述另一内插器衬底电连接至所述第三内插器触点，
其中，所述第一器件芯片和所述第二器件芯片中的所述一个进一步包括设置在所述第一器件芯片和所述第二器件芯片中的所述一个的另一表面上的第四芯片触点；并且
所述第三内插器触点附接至所述第三芯片触点，并且所述第四内插器触点附接至所述第四芯片触点。
31.一种用于形成根据权利要求16所述的三维(3D)存储器件的方法，包括：
在芯片衬底的第一侧形成交替导体/电介质堆叠层；
形成竖直延伸通过所述交替导体/电介质堆叠层的存储器串；
在所述芯片衬底的与所述第一侧相对的第二侧形成芯片触点，所述芯片触点电连接至所述存储器串；
在内插器衬底的第一侧形成第一内插器触点；
在所述内插器衬底的与所述第一侧相对的第二侧形成第二内插器触点，所述第二内插器触点通过所述内插器衬底电连接至所述第一内插器触点；以及
将所述第一内插器触点附接至所述芯片触点。
32.根据权利要求31所述的方法，还包括：
在形成所述第一内插器触点之前，在所述内插器衬底上形成重新分布层；以及
形成第一通孔触点，所述第一通孔触点延伸通过所述内插器衬底并且与所述重新分布层接触，以使得所述第一内插器触点和所述第二内插器触点通过所述重新分布层和所述第一通孔触点电连接。
33.根据权利要求31或32所述的方法，还包括：
形成竖直延伸通过所述交替导体/电介质堆叠层的第二通孔触点；以及
形成处于所述芯片衬底的第一侧并与所述第二通孔触点接触的互连层。
34.一种用于形成根据权利要求16所述的三维(3D)存储器件的方法，包括：
在芯片衬底的第一侧形成交替导体/电介质堆叠层；
形成竖直延伸通过所述交替导体/电介质堆叠层的存储器串；
在所述芯片衬底的第一侧形成芯片触点，所述芯片触点电连接至所述存储器串；
在内插器衬底的第一侧形成第一内插器触点；
在所述内插器衬底的与所述第一侧相对的第二侧形成第二内插器触点，所述第二内插器触点通过所述内插器衬底电连接至所述第一内插器触点；以及
将所述第一内插器触点附接至所述芯片触点。
35.根据权利要求34所述的方法，还包括：
在形成所述第一内插器触点之前，在所述内插器衬底上形成重新分布层；以及
形成第一通孔触点，所述第一通孔触点延伸通过所述内插器衬底并且与所述重新分布层接触，以使得所述第一内插器触点和所述第二内插器触点通过所述重新分布层和所述第一通孔触点电连接。
36.根据权利要求34或35所述的方法，还包括：
形成竖直延伸通过所述交替导体/电介质堆叠层的第二通孔触点；以及
形成处于所述芯片衬底的第一侧并与所述第二通孔触点和所述芯片触点接触的互连层。
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