CN112020763A - 用于简化的手柄晶片的dbi到si的键合 - Google Patents

用于简化的手柄晶片的dbi到si的键合 Download PDF

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Publication number
CN112020763A
CN112020763A CN201980026853.3A CN201980026853A CN112020763A CN 112020763 A CN112020763 A CN 112020763A CN 201980026853 A CN201980026853 A CN 201980026853A CN 112020763 A CN112020763 A CN 112020763A
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substrate
bonding
bonding surface
forming
handle
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CN112020763B (zh
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C·曼达拉普
G·G·小方丹
G·高
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Evanss Adhesive Technologies
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Evanss Adhesive Technologies
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Abstract

器件和技术包括制备各种微电子部件的工艺步骤，该各种微电子部件用于键合，诸如用于没有粘合剂的直接键合。工艺包括在微电子部件的第一表面上提供第一键合表面，将手柄键合到制备的第一键合表面，以及在微电子部件被夹持在手柄处的情况下，处理微电子部件的第二表面。在一些实施例中，工艺包括将手柄从第一键合表面移除，以及在第一键合表面处将微电子部件直接键合到其他微电子部件。

Description

用于简化的手柄晶片的DBI到SI的键合
相关申请的交叉引用
本申请要求于2019年4月17日提交的美国非临时申请第16/386,261号，以及于2018年4月20日提交的美国临时申请第62/660,509号的权益，这些申请通过整体引用并入本文。
技术领域
以下描述涉及集成电路(“IC”)。更具体地，以下描述涉及制造IC裸片和晶片。
背景技术
微电子元件通常包括半导体材料(诸如硅和砷化镓)的薄板，该薄板通常被称为半导体晶片。晶片可以形成为包括位于晶片的表面上和/或部分被嵌入晶片中的多个集成芯片或裸片。与晶片分离的裸片通常被作为单独的预封装单元提供。在一些封装设计中，裸片安装到衬底或芯片载体上，转而该衬底或该芯片载体安装在电路面板(诸如印刷电路板(PCB))上。例如，许多裸片设置在适合于表面安装的封装中。
封装的半导体裸片也可以设置成“堆叠”布置，其中设置一个封装，例如，在电路板或其他载体上，并且在第一封装的顶部安装另一封装。这些布置可以允许许多不同的裸片或器件设置在电路板上的单个足迹中，并且可以通过在封装之间提供短的互连来进一步促进高速操作。通常，这种互连距离只能稍微大于裸片本身的厚度。为了在裸片封装的堆叠中实现互连，可以将用于机械和电气连接的互连结构设置在每个裸片封装(除了最上面的封装)的两侧(例如面)上。
附加地，作为部分的各种微电子封装方案，裸片或晶片可以以三维布置堆叠。这可以包括在基底裸片、器件、晶片，衬底等上，堆叠一个或多个裸片、器件和/或晶片的层，以在竖直或水平布置上堆叠多个裸片或晶片以及两者的各种组合。
裸片或晶片可以使用各种键合技术以堆叠布置键合，各种键合技术包括直接电介质键合的、无粘合剂技术，诸如
Figure BDA0002731352180000021
或混合的键合技术，诸如
Figure BDA0002731352180000022
两者都可从英帆萨斯邦德科技有限公司(以前的Ziptronix公司)、Xperi公司(例如参见美国专利第6,864,585号和第7,485,968号，这些专利整体并入本文)获得。键合的裸片或晶片的相应配合表面。通常包括嵌入的导电互连结构等。在一些示例中，键合表面被布置并被对齐，使得在键合工艺中导电互连结构从相应的表面接合。接合的互连结构在堆叠的裸片或晶片之间形成连续的导电互连(用于信号、功率等)。
实现堆叠的裸片和晶片布置，可能会面临各种各样的挑战。当使用直接键合或混合键合技术来键合堆叠的裸片时，通常期望待被键合的裸片表面非常平整、光滑和干净。例如，一般而言，在表面拓扑方面，表面应当具有非常低的方差(即纳米级方差)，使得表面可以紧密配合，以形成持久的键合。
可以形成和制备用于堆叠和键合的双面裸片，其中裸片的两个侧面将被键合到其他衬底或裸片，诸如利用多个裸片到裸片应用或裸片到晶片的应用。制备裸片的两个侧面包括对两个表面进行抛光，以满足电介质粗糙度规范和金属化层(例如铜等)凹陷规范。例如，键合表面处的导电互连结构可能仅在键合表面的绝缘材料下方会稍微凹陷。键合表面下方的凹陷量可以由器件或应用的尺寸容差、规范或物理极限决定。可以使用化学机械抛光(CMP)工艺等来制备用于与另一裸片、晶片或其他衬底键合的混合表面。
手柄晶片在工艺步骤中可以被用于保持裸片，该手柄晶片在处理工艺中可以被临时地粘到裸片的一个侧面，并且之后被移除。然而，粘合剂键合通常不会提供使晶片精确地减薄至1μm至10μm的硅厚度所需的均匀度，通常也不会允许在高于250℃的温度下进行处理。另外，粘合层通常过于可压缩，以致于通过化学机械抛光(CMP)来支撑充分的平坦化。
附图说明
详细的描述是参照附图进行说明的。在图中，参考数字的(多个)最左边的数位标识参考数字首次出现的图。在不同的图中使用相同的参考数字来表示相似的或相同的项。
出于该讨论，图中所示的器件和系统被示出为具有多种部件。如本文所描述的，器件和/或系统的各种实施方式可以包括较少的部件并且处于本公开的范围内。备选地，器件和/或系统的其他实施方式可以包括附加部件或所描述的部件的各种组合，并且处于本公开的范围内。
图1至图3示出了根据实施例的示例图形流程图，图示了使用手柄晶片制备用于键合的裸片的示例工艺。
图4至图6示出了根据实施例的示例图形流程图，图示了使用手柄晶片制备用于键合的裸片的另一示例工艺。
图7至图9示出了根据实施例的示例图形流程图，图示了使用手柄晶片制备用于键合的裸片的附加示例工艺。
图10至图12示出了根据实施例的示例图形流程图，图示了使用手柄晶片制备用于键合的裸片的又一示例工艺。
图13图示了根据实施例的由多个堆叠且键合的微电子元件组成的示例微电子组件。
发明内容
公开了代表技术和器件，包括用于制备各种微电子部件的工艺步骤，各种微电子部件用于键合，诸如用于没有粘合剂的直接键合。该工艺包括在微电子部件的第一表面上提供第一键合表面，将手柄键合到制备的第一键合表面，以及在微电子部件被夹持在手柄处的情况下，处理微电子部件的第二表面。在一些实施例中，工艺包括从第一键合表面移除手柄，并且将微电子部件在第一键合表面处直接键合到其他微电子部件。
在各种实施方式中，微电子组件包括：第一衬底，包括具有平坦化形貌的第一键合表面，该第一键合表面具有第一预定最大表面公差；以及第二衬底，该第二衬底具有带有平坦化形貌的键合表面。第二衬底使用直接电介质到电介质的、无粘合剂技术而被键合到第一衬底的第一键合表面，以形成手柄。在第一衬底的与第一表面相对的第二表面被处理的情况下，第二衬底被布置为支撑第一衬底。在一个示例中，在第一衬底被夹持在手柄处的情况下，使第二表面平坦化，以形成第一衬底的第二键合表面(该第二键合表面具有第二预定最大表面公差)。
在实施方式中，第一衬底的第一键合表面包括电介质并且包括一个或多个导电互连。在另一种实施方式中，第二衬底包括硅。
在各种实施方式中，形成微电子组件的方法包括：制备第一衬底的第一键合表面，该制备包括使第一键合表面平坦化以具有第一预定最大表面公差以及将第二衬底沉积到第一键合表面上，以形成手柄；以及在第一衬底被夹持在手柄处的情况下，处理第一衬底的与第一表面相对的第二表面。
在实施例中，方法包括：使第二表面平坦化，以形成具有第二预定最大表面公差的第二键合表面。在另一实施例中，方法包括：使用直接电介质到电介质的、无粘合剂接合技术，将第二衬底直接键合到第一键合表面。在又一实施例中，方法包括：移除手柄以及将第一衬底单片化成多个微电子裸片。
各种实施方式和布置参考电气和电子部件以及不同的载体进行讨论。虽然提到了具体部件(即裸片、晶片、集成电路(IC)芯片裸片、衬底等)，但是这并不旨在限制，而是为了便于讨论和说明。参考晶片、裸片、衬底等进行讨论的技术和器件，适用于任何类型或数目的电气部件、电路(例如集成电路(IC)、混合电路、ASIC、存储器器件、处理器等)、部件组、封装部件、结构(例如晶片、面板、板、PCB等)等，它们可以利用外部电路、系统、载体等被耦合以与彼此进行接口。这些不同的部件、电路、组、封装、结构等中的每一个通常都可以被称为“微电子部件”。为了简单起见，除非另有规定，否则被键合到另一部件的部件将在本文中被称为“裸片”。
该发明内容并不旨在给出完整的描述。下面将使用多个示例更详细地说明实施方式。虽然在此处和在下面讨论了各种实施方式和示例，但是进一步的实施方式和示例，通过组合单独的实施方式和示例的特征和要素，可能也是可以的。
具体实施方式
图案化的金属和氧化物层经常设置在裸片、晶片或其他衬底(下文称为“裸片”)上，作为混合键合或
Figure BDA0002731352180000051
表面层。在双面裸片的情况下，具有制备的键合表面的图案化的金属和氧化物层可以设置在裸片的两个侧面上。氧化物在氧化物表面处与金属化层(例如嵌入的导电特征)通常是高度平坦的(通常到纳米级粗糙度)、或仅在氧化物表面下方是凹陷的。氧化物下方的凹陷量通常由尺寸容差、规范或物理极限决定。通常使用化学机械抛光(CMP)步骤和/或其他制备步骤，来制备用于与另一裸片、晶片或其他衬底直接键合的键合表面。
当处理厚度低于200μm的薄晶片时，为了在没有破损的情况下处理晶片，某种规范的手柄晶片通常被附接到器件晶片。当为了晶片堆叠和键合的目的需要处理晶片的背面时，这尤其如此。对于许多应用来说，期望在厚度只有几微米硅厚度且多次在高于25摄氏度的温度下处理晶片。
然而，使用粘合剂将手柄晶片键合到器件晶片，通常不会提供将器件晶片精确减薄到1μm至10μm的硅厚度所需的均匀度，通常也不会允许在高于250℃的温度下进行处理。粘合层通常过于可压缩，以致于通过化学机械抛光(CMP)来支撑充分的平坦化。
本文所公开的器件和技术描述了使用直接键合技术将手柄晶片键合到器件晶片，以允许在对裸片的键合表面进行处理、在高于250℃的温度下进行处理，以及在为CMP平坦化提供充分的支撑等时的均匀度。手柄晶片便于在工艺步骤中处理裸片，并且在不再需要时，可以被选择性地移除。在各种实施方式中，手柄晶片直接键合到制备的键合表面中的一个。使用除粘合剂之外的直接键合技术将手柄附接到器件晶片意味着，选择性移除工艺使制备的键合表面留在器件晶片上。
图1至图13图示了用于制备各种微电子部件(诸如裸片302)的代表器件和工艺，各种微电子部件用于键合，诸如用于没有粘合剂的直接键合。该工艺包括：在微电子部件的第一表面(其可以是器件晶片102或其他衬底的部分)上提供第一键合表面(诸如第一键合表面108)，提供第一键合表面包括提供被嵌入在第一键合表面中的第一导电互连特征110或衬底；将手柄(诸如手柄晶片114)键合到制备的第一键合表面；在微电子部件的第二表面上提供第二键合表面(诸如第二键合表面202)，提供第二键合表面包括提供被嵌入在第二键合表面中的第二导电互连特征110’或结构；从第一键合表面移除手柄；以及通过在键合表面直接键合微电子部件来形成微电子组件，等等。
工艺被描述的顺序并不旨在被说明为限制，并且工艺中的任意数目的所描述工艺框可以按照任何顺序被组合以实现工艺或备选工艺。附加地，可以从任何工艺中删除单个的框，而不脱离本文所描述主题的精神和范围。此外，工艺可以在任何合适的硬件、软件、固件或其组合中实现，而不脱离本文所描述的主题范围。在备选实施方式中，其他技术可以以各种组合形式被包括在工艺中并且处于本公开的范围内。
参照图1至图3，在工艺100中，可以使用各种技术形成代表器件晶片102(例如晶片、衬底、裸片等)，以包括基底衬底104和绝缘层或电介质层106。基底衬底104可以由硅、锗、玻璃、石英、电介质表面、直接或间接带隙半导体材料或半导体层或其他合适的材料组成。绝缘层106沉积或形成在衬底104之上，并且可以由无机电介质材料层组成，诸如氧化物、氮化物、氮氧化物、碳氧化物、碳化物、碳氮化物、金刚石、类金刚石材料、玻璃、陶瓷、玻璃陶瓷等以及它们的组合。
如框A所示，器件晶片102的键合表面108可以包括导电特征110，诸如迹线、衬垫和互连结构，例如，需要时，被嵌入至绝缘层106中并且设置为使得导电特征110可以在键合工艺中从相对器件的相应键合表面108被配合并结合。结合的导电特征110可以在堆叠的器件之间形成连续的导电互连(用于信号、功率等)。
镶嵌工艺(或类似的工艺)可以被用于在绝缘层106中形成嵌入的导电特征110。导电特征110可以由金属(例如铜等)或其他导电材料或材料的组合组成，并且包括结构、迹线、衬垫、图案等。在一些示例中，在沉积导电特征110的材料之前，可以在用于导电特征110的空腔中沉积阻挡层112，以便阻挡层112被沉积在导电特征110与绝缘层106之间。例如，阻挡层112可以由钽或其他导电材料组成，以防止或减少导电特征110的材料扩散到绝缘层106中。
通过使用附加的衬底或所谓的虚拟衬垫、迹线、图案等，导电特征110可以被嵌入到绝缘层106中，以提供电气和/或热路径，或相反可以被配置为平衡键合表面108的金属化。在形成导电特征110之后，可以使器件晶片102的暴露表面(包括绝缘层106和导电特征110)平坦化(例如经由CMP)，以形成平的键合表面108。
形成键合表面108包括对表面108进行抛光，以满足电介质粗糙度规范和金属化层(例如铜等)凹陷规范，以制备用于直接键合的表面108。换言之，键合表面108形成为尽可能平坦且光滑，具有非常小的表面拓扑公差。各种传统工艺(诸如化学机械抛光(CMP)、干法或湿法蚀刻等)都可以被用于实现低表面粗糙度。这种工艺提供了导致可靠键合的平整的、光滑的表面108。
在一些情况下，如图1所示，导电特征110的暴露表面可以相对于键合表面108有意地凹陷，以允许材料膨胀，特别是在加热退火期间(如果要进行的话)。在其他情况下，导电特征110的暴露表面可以形成为超过凹陷规范，并且可以从键合表面108上方突出，以允许导电特征110在之后的处理中氧化。例如，这可以通过对电介质层106进行选择性蚀刻来完成。
在抛光或其他工艺步骤中，导电特征110的在键合层108处的表面可能被氧化(等等)，这可能导致其超出期望的规范。导电特征110可以被选择性地蚀刻、接触抛光等，以消除氧化并改善后续的键合和电气连接，包括恢复相对于键合表面108的期望的凹陷。
在制备之后，器件晶片102的第一键合表面108可以被键合到另一支撑晶片114(例如“硅晶片”、“手柄晶片”等)，以制造第二(即背面)键合表面202。例如，添加手柄晶片114有助于在第二侧面处理期间，处理器件晶片102，特别是在器件晶片102较薄或在处理期间被减薄时。手柄晶片114可以包括硅衬底，类似于基底层104等。具有与基底层104相似的热膨胀系数(CTE)的手柄晶片114，可以有助于在处理期间控制翘曲，特别是在处理期间加热器件时。在文中尽管参考了手柄晶片，手柄并不限于诸如硅晶片的晶片形式。备选地，手柄可以被提供为面板、裸片或其他形式和/或材料，用以容纳各种大小的衬底104。
如框A所示，可以通过在手柄晶片114上沉积绝缘层118，来制备手柄晶片114的键合表面116。绝缘层118可以由无机电介质材料层组成，诸如氧化物、氮化物、氮氧化物、碳氧化物、碳化物、碳氮化物、金刚石、类金刚石材料、玻璃、陶瓷、玻璃陶瓷等以及它们的组合(例如，绝缘层118可以部分或全部由与绝缘层106相同的(多种)材料组成，但不必如此)。使键合表面116平坦化(使用CMP等)，以实现高度平坦的表面，以便与器件晶片102进行可靠的直接键合。在实施例中，可以对键合表面108和键合表面116(例如绝缘层118，如果存在的话)中的一个或两个进行等离子体激活，为键合做准备。
如框B所示，工艺100包括：通过将手柄114的键合表面116(在绝缘层118上，如果存在的话)直接键合到器件晶片102的键合表面108，手柄晶片114在不使用粘合剂的情况下，被键合到器件晶片102。在一些示例中，键合在环境或“室温”(例如小于90℃)条件下进行。在其他示例中，可以对键合的组件进行热退火，以加强键合。增加的牺牲手柄114为非常薄的有源裸片(例如，<<50μm)提供机械支撑。手柄114还可以在高温处理中保留DBI金属化层(例如铜)，例如在约300摄氏度下保留2小时等。
如框C所示，在形成第二键合表面202并且对其进行抛光之前，基底层104可以被减薄，并且任何一个硅通孔(TSV)被暴露和平坦化。通过使用直接键合将手柄晶片114附接到器件晶片102，可以实现使器件晶片102非常精确的减薄，并且可以在高于250℃的温度下处理键合后的对。在实施例中，基底层104被减薄，以具有小于20微米的厚度和小于3微米的总厚度变化(TTV)。在其他实施例中，基底层104的厚度和TTV可能具有更大的尺寸。
参照图2，如框D所示，利用在适当位置的手柄晶片114，然后器件晶片102的背面上的第二键合表面202可以被沉积、形成并且被抛光，以在具有最小表面拓扑公差的情况下满足最大电介质粗糙度规范和金属化层(例如铜等)凹陷规范。例如，可以将绝缘层106’沉积到器件晶片102的背面上，并且如果需要，在其中嵌入导电特征110’。包括绝缘层106’(和导电特征110’)的第二键合表面202被平坦化，为直接键合做准备。
在框E中，可以将临时地载体204附接到第二键合表面202，例如利用临时地粘合剂206等。
如框F所示，随后，可以使用各种技术(包括但不限于背面研磨、化学机械抛光(CMP)、干法蚀刻和湿法化学腐蚀或其组合)使手柄晶片114减薄并且将其选择性地移除。在一些情况下，可以使用与基底层114(例如其可以由硅组成)不同的技术(例如不同的化学和/或机械工艺或技术)来移除手柄晶片114的绝缘(例如氧化物)层118。当手柄晶片114被移除时，包括绝缘层106和任何导电层(诸如导电特征110)的第一键合表面108显露出来。在各个示例中，第一键合表面108可以在无需进行进一步处理的情况下准备就绪用于直接键合。在其他示例中，在键合之前可以执行一些制备步骤(例如抛光、清洗、漂洗等)。
在一些情况下，可以将保护涂层208涂到经过抛光的第一键合表面108或第二键合表面202上，以在加工工艺中进行保护。在一个示例中，如框F所示，在手柄晶片114被移除之后，可以将保护涂层208涂到暴露的第一键合表面108上。保护涂层208可以保护第一键合表面108，包括绝缘层106和任何导电特征110，用于在手柄晶片114已被蚀刻、溶解、研磨或以其他方式从第一键合表面108移除之后的、未来的直接或混合键合步骤。在一些实施例中，保护涂层208可以包括光致抗蚀剂、聚合物涂层等。
如框G所示，在完成器件晶片102的两个侧面之后，可以移除临时地载体204和临时地键合材料206。在框H中(参见图3)，完成的双面器件晶片102然后可以被安装到保持在切割框架中的切割带304上，并且被单片化以形成一定量的双面裸片302。器件晶片102可以通过等离子体切割、锯齿切割、隐形切割或其他技术被单片化成裸片302。可选地，裸片302可以被转移到夹持环，为键合做准备。在实施方式中，裸片302在被安装到切割框架或夹持环上的情况下，可以被清洗(或经历其他处理)。
在一些实施例中，在单片化之前或之后，可以将不只一种类型的保护层涂到(多个)键合表面108和/或202上。例如(如框H所示)，第一保护层208可以包括疏水保护层，并且覆盖疏水层208的可以是亲水保护层306。在下面的疏水层208允许在清洗裸片302的侧表面时使用腐蚀性蚀刻化学品(在单片化之后)，而且也增加了制备的键合表面108和/或202的保存期限。
在上面的亲水层接收切割工艺中所产生的颗粒、碎片、切割带、粘合剂等或可能被它们浸渍。亲水层306连同颗粒和碎片一起被移除。换言之，颗粒和碎片随亲水层306的移除而被带走。在一些情况下，疏水层208可以暂时地保留在裸片302上，以在后续的处理或存储工艺中保护(多个)表面108和/或202。然而，疏水层208(或任何剩余的保护涂层)可以在键合之前被移除，如框I所示。
在框J中，工艺100包括使用拾取和放置器件等，将单片化的裸片302堆叠和键合到制备的主裸片、晶片、衬底308等。制备主衬底308可以包括在衬底308的表面上沉积和形成键合表面310，沉积和形成键合表面310包括提供导电特征312等，以及形成高度平坦的表面拓扑，包括如上所述的在基底层104”上方的绝缘层106”。
在一些情况下，可以对键合表面108和/或键合表面310进行等离子体处理，以加强直接键合。可以将附加裸片302堆叠和键合到衬底308或先前被键合的裸片302，如框K所示。进一步地，一旦根据需要堆叠和键合(多个)裸片302，便可以对组件300进行热退火，以进一步键合导电特征110和312。当然，将了解，裸片302可以在被键合到衬底308之前被堆叠。此外，热退火可以在每个键合步骤之后或在所有裸片和衬底都被堆叠之后实现。
例如，参照图4至图6，示出了工艺400，其中在没有绝缘层118的情况下，可以将裸硅的牺牲性手柄晶片114键合到器件晶片102。如图4所示，在框A中，工艺400包括提供器件晶片102(例如晶片、衬底、裸片等)，其可以如上所述形成为包括基底衬底104和绝缘层或电介质层106。
如框A所示，器件晶片102的键合表面108可以包括导电特征110。镶嵌工艺(等等)可以被用于在绝缘层106中形成嵌入的导电特征110。导电特征110可以由金属(例如铜等)或其他导电材料或材料的组合组成，并且包括结构、迹线、衬垫、图案等。在一些示例中，如上所述，在沉积导电特征110的材料之前，可以在用于导电特征110的空腔中沉积阻挡层112(未示出)，以便阻挡层112被沉积在导电特征110和绝缘层106之间。
在形成导电特征110之后，可以使器件晶片102的暴露表面(包括绝缘层106和导电特征110)平坦化(例如经由CMP)，以形成平的键合表面108。形成键合表面108包括：对表面108进行抛光，以满足电介质粗糙度规范和金属化层(例如铜等)凹陷规范，从而制备用于直接键合的表面108。
在制备之后，可以将器件晶片102的第一键合表面108键合到手柄晶片114，以制造第二(即背面)键合表面202。在实施方式中，手柄晶片114包括硅衬底等。如框A所示，使手柄晶片114的键合表面116平坦化(使用CMP等)，以实现高度平坦表面，用于与器件晶片102形成可靠的直接键合。在实施例中，可以用食人鱼(piranha)腐蚀剂(例如硫酸和过氧化氢)来制备手柄晶片114的键合表面116。附加地或备选地，手柄晶片114的键合表面116可以具有薄的氧化物层，诸如可以通过热氧化工艺提供，而不是通过上述氧化物沉积工艺提供。这种薄的氧化物层可以小于10nm。在实施例中，可以对键合表面108进行等离子体激活，为键合做准备。
如框B所示，工艺400包括：在不使用粘合剂的情况下，通过将手柄114的键合表面116直接键合到器件晶片102的键合表面108，将手柄晶片114键合到器件晶片102。在一些示例中，键合是在周围环境或“室温”(例如小于90℃)条件下进行的。在其他示例中，可以对键合的组件进行热退火，以加强键合。增加的牺牲手柄114为非常薄的有源裸片(例如，<<50μm)提供机械支撑。手柄114还可以在高温处理期间保护DBI金属化层(例如铜)，例如在约300摄氏度下达2小时等。
如框C所示，在形成第二键合表面202并且对其进行抛光之前，基底层104可以被减薄，并且任何一个硅通孔(TSV)被暴露。通过使用直接键合将手柄晶片114附接到器件晶片102，可以实现使器件晶片102非常精确的减薄，并且可以在高于250℃的温度下处理键合后的对。
参照图5，如框D所示，利用在适当位置的手柄晶片114，然后器件晶片102的背面上的第二键合表面202可以被沉积、形成且被抛光，以在具有最小表面拓扑公差的情况下满足最大电介质粗糙度规范和金属化层(例如铜等)凹陷规范。例如，可以将绝缘层106’沉积到器件晶片102的背面上，并且导电特征110’(如果需要)被嵌入其中。使包括绝缘层106’(和导电特征110’)的第二键合表面202平坦化，为直接键合做准备。
在框E中，可以将临时地载体204附接到第二键合表面202，例如利用临时地粘合剂206等。
如框F所示，随后，可以使用各种技术(包括但不限于背面研磨、触摸CMP、干法蚀刻和湿法化学腐蚀或其组合)使手柄晶片114减薄并且将其选择性地移除。在一些示例中，非常薄的氧化物层可以与手柄晶片114一起被移除。例如，在薄的氧化物层被键合到第一键合表面时，其可以是手柄晶片114的部分，如上所述。当手柄晶片114被移除时，包括绝缘层106和任何导电层(诸如导电特征110)的第一键合表面108显露出来。例如，在各个示例中，第一键合表面108可以在无需进行进一步处理(诸如CMP)的情况下准备就绪直接键合。在其他示例中，在键合之前可以执行一些制备步骤(例如抛光、清洗、漂洗等)。
在一些情况下，可以将一个或多个保护涂层208和/或306涂到经过抛光的第一键合表面108或第二键合表面202上，以在加工工艺中进行保护，如上所述。在一个示例中，如框F所示，在手柄晶片114被移除之后，可以将保护涂层208和/或306涂到暴露的第一键合表面108上。
如框G所示，在完成器件晶片102的两个侧面之后，可以移除临时地载体204和临时地键合材料206。在框H中(参见图6)，使用等离子体切割、锯齿切割、隐形切割或其他技术，完成的双面器件晶片102可以被安装到框架上的切割带304上并且被单片化以形成一定量的双面裸片302。可选地，裸片302可以被转移到夹持环，为键合做准备。在实施方式中，裸片302在被安装到保持在切割框架或夹持环中的带304上的情况下，可以被清洗(或经历其他处理)。
在一些情况下，手柄晶片114可能在之前的工艺步骤中未被移除，并且可能与薄晶片一起被切割并且被用于在该工艺步骤中处理裸片302。在那些情况下，在批量处理工艺等中，可以从多个裸片302移除被切割的手柄114。例如，湿法蚀刻可以被用于移除手柄114，如果需要的话，还可以增加键合表面108的轻触抛光。在备用实施例中，如果需要，或被用于其他工艺目的，被切割的手柄114可以保持键合到裸片302中的一些裸片，以增加裸片302的高度。
如上所述，在单片化之前或之后，不只一种类型的保护层(例如208和/或306)可以被涂到(多个)键合表面108和/或202上。例如，可以将第一疏水保护涂层208和上面的亲水保护涂层306以及一个或多个其他保护涂层涂到(多个)键合表面108和/202上。如上所述，单片化所产生的颗粒和碎片可以随一个或多个保护涂层(例如亲水层306)的移除而被带走。在一些情况下，疏水层208可以临时地留在裸片302上，以在后续处理或存储工艺中保护(多个)表面108和/或202。然而，疏水层208(或任何剩余的保护涂层)可以在键合之前被移除，如框I所示。
在框J中，工艺100包括：使用拾取和放置器件等，将单片化的裸片302堆叠和键合到制备的主裸片、晶片、衬底308等。制备主衬底308可以包括：在衬底308的表面上沉积和形成键合表面310，包括提供导电特征312等，以及形成高度平面的表面拓扑，包括基底层104”上的绝缘层106”，如上所述。
在一些情况下，可以对键合表面108和/或键合表面310进行等离子体处理，以加强直接键合。附加的裸片302可以被堆叠并被键合到衬底308或之前键合的裸片308，如框K所示。进一步地，一旦(多个)裸片302根据需要被堆叠并被键合，便可以对组件300进行热退火，以进一步键合导电特征110和312。
对于本领域技术人员而言，使用裸硅晶片作为手柄114的优点是显而易见的。例如，手柄晶片114可以直接键合到为直接键合制备的表面(诸如氧化物表面或
Figure BDA0002731352180000141
(例如混合)表面)。当利用以下处理组合移除手柄晶片114时：诸如但不限于背面研磨、CMP、干法蚀刻和湿法化学腐蚀或其组合，可以在高选择度的情况下通过各种技术完全移除手柄晶片114，因为只涉及一种材料(例如硅)。
如上所述，裸硅手柄晶片114特别地用于制备和处理用于键合工艺的薄裸片302。例如，为
Figure BDA0002731352180000142
(例如混合)键合制备的器件晶片102可以直接被键合到裸硅手柄晶片114，并且随后被减薄到低于例如10μm的活性硅厚度。该键合的晶片对可以在器件晶片102的背面上进行处理，以制备用于键合的第二
Figure BDA0002731352180000151
(例如混合)表面。
如果需要，则器件晶片102的切割街区可以被图案化并被蚀刻至手柄晶片114或被蚀刻进手柄晶片114，以实现用于键合的均匀光滑的裸片302边缘。然后手柄晶片114可以被减薄到裸片302的键合所需的用于切割和处理的期望厚度。在裸片302已被键合到第二器件晶片308(等等)之后，可以通过例如湿法化学腐蚀选择性地移除手柄114。可以选择湿法蚀刻，例如TMAH，该方法在硅、氧化物、铜和阻挡金属之间具有非常高的选择度，使得能够在不损坏键合表面108或202的情况下，移除硅手柄114。如果有必要，则可以在蚀刻之后采用轻CMP处理，使裸片302的表面108和/或202光滑，以便键合第二裸片302。可以重复该处理，以在器件晶片308(等等)上实现器件裸片302的堆叠。
使用没有粘合剂的直接键合技术，将具有氧化物层118或裸硅手柄晶片114的手柄晶片114键合到器件晶片102的一些优点包括：手柄114适应器件晶片102的准确减薄；手柄114适应器件晶片102的高温处理；与粘合剂键合的手柄晶片相比，手柄114在手柄114和器件晶片102之间提供更好的热传导；手柄适应晶片的正常操作(与可能需要特殊操作的透明手柄晶片相反)用于处理；以及手柄114提供了清洁的且没有移动的包含粒子的材料或其他污染物(诸如利用玻璃晶片)的手柄技术。
例如，参照图7至图9，示出了处理700，其中在没有绝缘层118的情况下，可以将裸硅牺牲手柄晶片114键合到器件晶片102。在实施方式中，器件晶片102可以安装到工艺卡盘上，以执行一些工艺步骤。如图7所示，在框A中，处理700包括提供器件晶片102(例如晶片、衬底、裸片等)，其可以如上述形成为包括基底衬底104和绝缘层或电介质层106。
如框A所示，器件晶片102的键合表面108可以包括导电特征110，如上所述，该器件晶片还可以包括导电特征110与绝缘层106之间的阻挡层112(未示出)。
在键合表面108制备之后，可以将器件晶片102的第一键合表面108键合到用于制造第二(即背面)键合表面202的手柄晶片114(例如裸硅晶片、具有通过等离子体或湿法化学处理形成的薄的热氧化物或薄的氧化物的硅等)。在实施方式中，手柄晶片114被平坦化(使用CMP等)，以实现高度平面的表面，并且可以利食人鱼蚀刻剂(例如硫酸和过氧化氢)来制备。在实施例中，可以对键合表面108进行等离子体激活，为键合做准备。
如框B所示，处理700包括：通过将手柄114的键合表面116直接键合到器件晶片102的键合表面108，手柄晶片114在不使用粘合剂的情况下，被键合到器件晶片102。在一些示例中，键合是在周围环境或“室温”(例如小于90℃)条件下进行的。在其他示例中，可以对键合的组件进行热退火，以加强键合。
如框C所示，在形成第二键合表面202并且对其进行抛光之前，基底层104可以被减薄，并且任何一个硅通孔(TSV)被暴露且被平坦化。通过使用直接键合来将手柄晶片114附接到器件晶片102，可以实现使器件晶片102非常精确的减薄，并且可以在高于250℃的温度下处理键合后的对。
参照图8，如框D所示，利用在适当位置的手柄晶片114，可以沉积、形成在器件晶片102的背面上的第二键合表面202并且对其进行抛光以在具有最小表面拓扑公差的情况下满足最大电介质粗糙度规范和金属化层(例如铜等)凹陷规范。例如，可以将绝缘层106’沉积到器件晶片102的背面上，并且如果需要，导电特征110’被嵌入其中。使包括绝缘层106’(和导电特征110’)的第二键合表面202平坦化，为直接键合做准备。
在框E中，可以将器件晶片102安装到诸如真空卡盘或静电卡盘等工艺卡盘802(等等)上
如框F所示，随后，可以使用各种技术(包括但不限于背面研磨、触摸CMP、干法蚀刻和湿法化学腐蚀或其组合)使手柄晶片114减薄并且将其选择性地移除。当手柄晶片114被移除时，包括绝缘层106和任何导电层(诸如导电特征110)的第一键合表面108显露出来。在各个示例中，第一键合表面108可以在无需进行进一步处理的情况下准备就绪直接键合，因为残留的少量氧化物可能在所需的粗糙度规范内。在其他示例中，在键合之前可以执行一些制备步骤(例如抛光、清洗、漂洗等)。
在一些情况下，如上所述，可以将一个或多个保护涂层208和/或306涂到经过抛光的第一键合表面108或第二键合表面202上，以在处理中进行保护。在一个示例中，参照框F，在手柄晶片114被移除之后，可以将保护涂层208和/或306(未示出)涂到暴露的第一键合表面108上。
如框G所示，当器件晶片102的两个侧面完成时，以及(在框H中，参照图9)当完成的双面器件晶片102安装到保持在切割框架中的切割带304上时，将器件晶片102从工艺卡盘802中释放。然后使用等离子体切割、锯齿切割、隐形切割或其他技术将晶片单片化，以形成一定量的双面裸片302。可选地，裸片302可以被转移到保持在夹持环中的切割带，为键合做准备。在实施方式中，裸片302在被安装到保持在切割框架或夹持环中的带304上的情况下，可以被清洗(或经历其他处理)。
在一些情况下，手柄晶片114可能在先前的工艺步骤中未被移除，并且可以在该工艺步骤中被用于处理裸片302。在那些情况下，在批量处理工艺等中，可以将手柄114从多个裸片302移除。例如，湿法蚀刻可以被用于移除手柄114，如果需要的话，还可以增加键合表面108的轻触抛光。
如上所述，在单片化之前或之后，不只一种类型的保护层(例如208和/或306)可以被涂到(多个)键合表面108和/或202上。例如，可以将第一疏水保护涂层208和在上面的亲水保护涂层306以及一个或多个其他保护涂层涂到(多个)键合表面108和/202上。如上所述，单片化所产生的颗粒和碎片可以随一个或多个保护涂层(例如亲水层306)的移除而被带走。在一些情况下，疏水层208可以暂时的留在裸片302上，以在后续处理或储存中保护(多个)表面108和/或202。然而，疏水层208(或任何剩余的保护涂层)可以在键合之前被移除，如框I所示。
在框J中，工艺100包括：使用拾取和放置器件等，将单片化的裸片302堆叠和键合到制备的主裸片、晶片、衬底308等。制备主衬底308可以包括：在衬底308的表面上沉积和形成键合表面310，包括提供导电特征312等，以及形成高度平坦的表面拓扑，包括基底层104”上的绝缘层106”，如上所述。
在一些情况下，可以对键合表面108和/或键合表面310进行等离子体处理，以加强直接键合。附加的裸片302可以被堆叠并被键合到衬底308或先前键合的裸片308，如框K所示。进一步地，一旦(多个)裸片302根据需要被堆叠和键合，便可以对组件300进行热退火，以进一步键合导电特征110和312。
例如，参照图10至图12，示出了简化工艺1000，其中裸硅牺牲手柄晶片114可以在没有绝缘层118的情况下，被键合到器件晶片102。在实施方式中，没有附加的临时地手柄或载体与器件晶片102一起使用。如图10所示，在框A中，工艺1000包括提供器件晶片102(例如晶片、衬底、裸片等)，其可以如上所述形成为包括基底衬底104和绝缘层或电介质层106。
如框A所示，器件晶片102的键合表面108可以包括导电特征110，如上所述，该器件晶片还可以包括在导电特征110与绝缘层106之间的阻挡层112(未示出)。
在键合表面108的制备之后，可以将器件晶片102的第一键合表面108键合到用于制造第二(即背面)键合表面202的手柄晶片114(例如裸硅等)。在实施方式中，手柄晶片114被平坦化(使用CMP等)，以实现高度平坦的表面，并且可以利用食人鱼蚀刻(例如硫酸和过氧化氢)来制备。附加地或备选地，手柄晶片114的键合表面116可以具有薄的氧化物层，诸如可以通过热氧化工艺提供，而不是通过上述氧化物沉积工艺提供。在实施例中，可以对键合表面108进行等离子体激活，为键合做准备。
如框B所示，工艺1000包括：通过将手柄114的键合表面116直接键合到器件晶片102的键合表面108，手柄晶片114在不使用粘合剂的情况下被键合到器件晶片102。在一些示例中，键合是在周围环境或“室温”(例如小于90℃)条件下进行的。在其他示例中，可以对键合的组件进行热退火，以加强键合。
如框C所示，在形成第二键合表面202并且对其进行抛光之前，基底层104可以被减薄，并且任何一个硅通孔(TSV)被暴露且被平坦化。通过使用直接键合将手柄晶片114附接到器件晶片102，可以实现使器件晶片102非常精确的减薄，并且可以在高于250℃的温度下处理键合对。
参照图11，如框D所示，利用在适当位置的手柄晶片114，可以沉积、形成在器件晶片102的背面上的第二键合表面202并且对其进行抛光，以在具有最小表面拓扑公差的情况下满足最大电介质粗糙度规范和金属化层(例如铜等)凹陷规范。例如，可以将绝缘层106’沉积到器件晶片102的背面上，并且如果需要，导电特征110’被嵌入其中。使包括绝缘层106’(和导电特征110’)的第二键合表面202平坦化，为直接键合做准备。
在框E中，如果需要，可以使硅手柄晶片114减薄。例如，如果手柄114旨在保持被键合到单片化的裸片302，则在这个步骤中或在工艺1000中的其他步骤中，可以使手柄晶片114减薄。在一些情况下，可以将一个或多个保护涂层208和/或306涂到经过抛光的第二键合表面202上，以在处理工艺中进行保护，如上所述。
如框F所示，器件晶片102与手柄晶片114一起向下翻转，并且被附接到保持在切割框架中的切割带304，以进行单片化，并且裸片302可以被转移到保持在夹持环中的切割带，为键合做准备。在实施方式中，裸片302在被安装到保持在切割框架或夹持环中的带304上的情况下，可以被清洗(或经历其他处理)。
如上所述，在单片化之前或之后，不只一种类型的保护层(例如208和/或306)可以被涂到(多个)键合表面108和/或202上。例如，可以将第一疏水保护涂层208和在上面的亲水保护涂层306以及一个或多个其他保护涂层涂到(多个)键合表面108和/202上。如上所述，单片化所产生的颗粒和碎片可以随一个或多个保护涂层(例如亲水层306)的移除而被带走。在一些情况下，疏水层208可以暂时的保留在裸片302上，以在后续处理或储存中保护(多个)表面108和/或202。然而，疏水层208(或任何剩余的保护涂层)可以在键合之前被移除，如框G所示。
在框H中，工艺1000包括：使用拾取和放置器件等，将单片化的裸片302堆叠和键合到制备的主裸片、晶片、衬底308等。制备主衬底308可以包括：在衬底308的表面上沉积和形成键合表面310，包括提供导电特征312等，以及形成高度平坦的表面拓扑，包括基底层104”上的绝缘层106”，如上所述。在一些情况下，可以对键合表面108和/或键合表面310进行等离子体处理，以加强直接键合。
如框H所示，例如，可以使用湿法蚀刻，在批处理中将手柄114从堆叠的和键合的裸片302中移除。在一些示例中，非常薄的氧化物层可以与手柄114一起被移除。例如，薄的氧化物层(<10nm)在被键合到第一键合表面时是手柄晶片114的部分，如上所述。如果需要，则可以执行键合表面108的轻触抛光(例如CMP)。可以将附加的裸片302堆叠和键合到衬底308或先前键合的裸片302，如框I所示。在键合之后(如果需要，则在批处理中)，可以将手柄114从附加的堆叠裸片302中的每个堆叠裸片中移除。备选地，例如，如果需要，则一些手柄114可以保持被键合到一些裸片302(例如，未从一些裸片302移除)，以增加裸片302的高度。进一步地，一旦(多个)裸片302根据需要被堆叠且被键合，便可以对组件300进行热退火，以进一步键合导电特征110和312。
参照图13，示出了示例微电子组件300，该微电子组件可以使用上述工艺100、400、700、1000中的一个或多个或另一工艺来形成。在实施例中，将多个裸片302(例如裸片302A至302N)堆叠和键合，如工艺1000的框H所描述。在每个裸片302都被键合到先前的裸片302(或衬底308)之后，在键合后续裸片302之前，可以将手柄114从键合的裸片302中移除。在各个实施例中，如果适用，则除了其他移除技术，还可以使用选择性湿法化学腐蚀来移除手柄114。
在实施方式中，使用(多种)选择性湿法蚀刻化学品来移除手柄114，也可以将组件300的其他部分暴露于化学品。例如，在手柄114移除步骤中，可以将一个或多个裸片302的基底层104和绝缘层106暴露于蚀刻化学品。当这些层(104和106)暴露于化学腐蚀时，选择性湿法蚀刻化学品对基底层104(例如硅)材料的蚀刻程度比绝缘层106(如果它完全蚀刻绝缘层106)大得多。这可以导致裸片302(包括先前已被堆叠和键合到组件300的裸片302)的基底层104的凹陷1302。因此，由于更多的暴露于化学腐蚀剂，堆叠中较低的裸片302可能有更大的凹陷1302。
例如，如图13所示，首先将裸片302A键合到主衬底308，并且在键合之后，使用化学腐蚀剂来移除裸片302A的手柄114。在移除步骤中，裸片302A的基底层104可以暴露于选择性化学腐蚀，从而导致基底层104的一些凹陷1302。裸片302A的绝缘层106也可以暴露于选择性化学腐蚀，但是由于化学腐蚀的选择性，可以经历非常少的凹陷或不经历凹陷。这可以使基底层104的凹陷1302在视觉上更可察觉。
一旦手柄114从裸片302A移除并且顶部键合表面108被暴露并制备以进行键合，便将裸片302B键合到裸片302A。一旦在裸片302B的手柄114的移除工艺中堆叠再次暴露于选择性化学腐蚀，便会导致裸片302B的基底层104的一些凹陷1302和裸片302A的基层104的更多凹陷1302。由于化学腐蚀的选择性，裸片302A和302B的绝缘层106经历非常少的凹陷或不经历凹陷。
当每个后续裸片302C至302N都被添加到堆叠时，移除每个裸片的手柄114，并且将堆叠暴露于(多种)选择性蚀刻化学品中。组件300上产生的不均匀轮廓特征可能看起来如图13所示，其中许多或全部基底层104已经历了一些凹陷1302(例如，基底层104的至少一部分具有比绝缘层106窄的宽度)，而绝缘层106已经历了非常少的凹陷或没有经历凹陷。同样，与组件300的上部裸片302(诸如裸片302N)相比，下部裸片302(诸如裸片302A)可以显示出更多的凹陷1302。
这会导致锯齿状并且不是恒定的或均匀的轮廓边缘，但是其中与裸片302(诸如裸片302A)的基底层104在裸片堆叠的相对端的最窄宽度(a)相比，裸片302(诸如裸片302N)的基底层104的在裸片堆叠302的第一端的最窄宽度(n)具有更大的尺寸。例如，键合的裸片堆叠302的每个裸片302的基底层104的最窄宽度具有从堆叠(宽度＝n)的第一端到堆叠(宽度＝a)的相对端逐渐减小的尺寸(n、c、b、a)。虽然每个裸片302的绝缘层106的尺寸(w)都是大体上恒定的，但是大于具有最大的最窄宽度尺寸的基底层104的最窄宽度(n)。
在各个实施例中，与本文所描述的工艺步骤相比，一些工艺步骤可能被修改或消除。
本文所描述的技术、部件和器件并不限于图1至图13的图示，并且在不脱离本公开的范围的情况下，可以应用于包括其他电器部件的其他设计、类型、布置和构造。在一些情况下，可以使用附加的或备选的部件、技术、序列或工艺来实现本文所描述的技术。进一步地，在产生相似或近似相同的结果的情况下，部件和/或技术可以在以各种组合来设置和/或组合。
虽然已经用特定于结构特征和/或方法动作的语言描述了本公开的实施方式，但是应当理解，实施方式并不一定受限于所描述的特定特征或动作。更确切地说，特定特征和动作被作为实施示例器件和技术的代表形式而公开。

Claims (32)

1.一种形成微电子组件的方法，包括：
制备第一衬底的第一键合表面，包括使所述第一键合表面平坦化，以具有第一预定最大表面公差；
将第二衬底直接键合到所述第一键合表面上，以将所述第二衬底用作手柄；以及
在所述第一衬底被键合到所述手柄的情况下，处理所述第一衬底的与所述第一表面相对的第二表面。
2.根据权利要求1所述的形成微电子组件的方法，所述方法进一步包括：使所述第二表面平坦化，以形成具有第二预定最大表面公差的第二键合表面。
3.根据权利要求1所述的形成微电子组件的方法，所述方法进一步包括：使用直接电介质到电介质的、无粘合剂键合技术，将所述第二衬底直接键合到所述第一键合表面。
4.根据权利要求1所述的形成微电子组件的方法，所述方法进一步包括：经由以下项来移除所述手柄：背面研磨、选择性湿法蚀刻、选择性干法蚀刻、化学机械平坦化、或背面研磨、选择性湿法蚀刻、选择性干法蚀刻和化学机械平坦化的组合。
5.根据权利要求1所述的形成微电子组件的方法，所述方法进一步包括：在所述第一衬底被键合到所述手柄的情况下，将所述第一衬底减薄至小于20微米。
6.根据权利要求1所述的形成微电子组件的方法，所述方法进一步包括：将所述第一衬底单片化成多个微电子裸片。
7.根据权利要求1所述的形成微电子组件的方法，其中所述第二衬底包括氧化物。
8.根据权利要求1所述的形成微电子组件的方法，其中所述第二衬底包括硅。
9.根据权利要求8所述的形成微电子组件的方法，其中所述第二衬底包括被形成在所述硅上的、小于10nm的氧化物层。
10.根据权利要求8所述的形成微电子组件的方法，其中所述第二衬底包括通过热氧化而被形成在所述硅上的氧化物层。
11.一种形成微电子组件的方法，包括：
制备第一衬底的第一键合表面，包括使所述第一键合表面平坦化，以具有第一预定最大表面公差，所述第一键合表面包括电介质、并且包括一个或多个导电互连；
使用直接电介质到电介质的、无粘合剂接合技术，将第二衬底直接键合到所述第一键合表面，以将所述第二衬底用作手柄；以及
在所述第一衬底被键合到所述手柄的情况下，使所述第一衬底的与所述第一表面相对的第二表面平坦化，以形成所述第一衬底的、具有第二预定最大表面公差的第二键合表面。
12.根据权利要求11所述的形成微电子组件的方法，所述方法进一步包括：在将所述第二衬底的键合表面键合到所述第一衬底的所述第一键合表面之前，使所述第二衬底的键合表面平坦化，并且利用包括硫酸和过氧化氢的腐蚀剂来制备所述第二衬底的所述键合表面。
13.根据权利要求11所述的形成微电子组件的方法，所述方法进一步包括：在将所述第二衬底的所述键合表面键合到所述第一衬底的所述第一键合表面之前，使所述第二衬底的键合表面平坦化，并且经由热氧化工艺在所述第二衬底的所述键合表面上形成薄的氧化物层。
14.根据权利要求11所述的形成微电子组件的方法，所述方法进一步包括：在所述第一衬底被键合到所述手柄的情况下，并且在形成所述第二键合表面之前，将所述第一衬底减薄。
15.根据权利要求14所述的形成微电子组件的方法，其中所述第一衬底被减薄，以具有小于20微米的厚度和小于3微米的总厚度变化(TTV)。
16.根据权利要求11所述的形成微电子组件的方法，所述方法进一步包括：在所述第二表面处沉积绝缘层，以形成所述第二键合表面。
17.根据权利要求11所述的形成微电子组件的方法，所述方法进一步包括：
移除所述手柄；以及
将所述第一衬底单片化成多个微电子裸片。
18.根据权利要求17所述的形成微电子组件的方法，所述方法进一步包括：经由以下项来移除所述手柄：选择性湿法蚀刻、选择性干法蚀刻、化学机械平坦化、背面研磨、或选择性湿法蚀刻、选择性干法蚀刻、化学机械平坦化和背面研磨的组合。
19.根据权利要求11所述的形成微电子组件的方法，所述方法进一步包括：等离子体激活所述第一衬底的所述第一键合表面。
20.根据权利要求11所述的形成微电子组件的方法，所述方法进一步包括：在将所述第二衬底键合到所述第一衬底之后，对所述第一衬底和所述第二衬底进行热退火。
21.根据权利要求11所述的形成微电子组件的方法，所述方法进一步包括：通过背面研磨、蚀刻和化学机械平坦化来移除所述手柄。
22.根据权利要求11所述的形成微电子组件的方法，所述方法进一步包括：在所述第一衬底的所述第一键合表面上沉积保护涂层，并且将所述第一衬底单片化成多个微电子裸片。
23.根据权利要求11所述的形成微电子组件的方法，所述方法进一步包括：在所述第一衬底被键合到所述手柄的情况下，使用没有粘合剂的直接键合技术，将所述微电子裸片堆叠并键合到制备的主裸片、晶片或衬底。
24.根据权利要求11所述的形成微电子组件的方法，所述方法进一步包括：
临时地将载体键合到所述第一衬底的所述第二键合表面；以及
在所述第一衬底被夹持在所述载体处的情况下，移除所述手柄。
25.根据权利要求11所述的形成微电子组件的方法，其中所述第二衬底包括氧化物。
26.根据权利要求11所述的形成微电子组件的方法，其中所述第二衬底包括硅，以及其中所述手柄经由选择性蚀刻剂而被移除。
27.根据权利要求11所述的形成微电子组件的方法，其中所述第二衬底包括硅，并且其中在移除所述硅之后，所述第一键合表面准备就绪进行进一步的键合，而无需对所述第一键合表面进行进一步的CMP。
28.一种微电子组件，包括：
多个键合的微电子元件的堆叠，所述微电子元件使用直接电介质到电介质的、无粘合剂技术而被键合在一起，所述微电子元件中的每个微电子元件包括：
第一层，包括具有平坦化形貌的第一键合表面，所述第一键合表面具有预定最大表面公差，所述第一键合表面包括绝缘材料、并且包括一个或多个导电互连；
第二层，在没有粘合剂的情况下被键合到与所述第一键合表面相对的所述第一层，所述第二层包括半导体材料；以及
第三层，包括具有平坦化形貌的第二键合表面，所述第二键合表面具有所述预定最大表面公差，所述第二键合表面包括绝缘材料、并且包括一个或多个导电互连，所述第三层的与所述第二键合表面相对的表面在没有粘合剂的情况下被键合到所述第二层，
其中所述微电子元件中的每个微电子元件的所述第二层的至少一部分具有凹陷的周界、以及比所述第一层或所述第三层的宽度更窄的宽度。
29.根据权利要求28所述的微电子组件，其中所述第一层的所述第一键合表面和所述第三层的所述第二键合表面包括氧化物。
30.根据权利要求28所述的微电子组件，其中所述第二层包括硅。
31.根据权利要求28所述的微电子组件，其中微电子元件的所述第二层的、在多个键合的微电子元件的所述堆叠的第一端处的最窄宽度，与微电子元件的所述第二层的、在多个键合的微电子元件的所述堆叠的相对端处的最窄宽度相比，具有更大的尺寸。
32.根据权利要求31所述的微电子组件，其中多个键合的微电子元件的所述堆叠的每个微电子元件的所述第二层的最窄宽度，具有从所述堆叠的所述第一端到所述堆叠的所述相对端逐渐减小的尺寸。
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