TW202343661A - 用於簡化的輔具晶圓的dbi至矽接合 - Google Patents

用於簡化的輔具晶圓的dbi至矽接合 Download PDF

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Publication number
TW202343661A
TW202343661A TW112124035A TW112124035A TW202343661A TW 202343661 A TW202343661 A TW 202343661A TW 112124035 A TW112124035 A TW 112124035A TW 112124035 A TW112124035 A TW 112124035A TW 202343661 A TW202343661 A TW 202343661A
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Taiwan
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bonding
wafer
die
bonding surface
layer
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TW112124035A
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English (en)
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肯卓瑟卡 曼達拉普
蓋烏斯 吉爾曼 方騰二世
桂蓮 高
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美商艾德亞半導體接合科技有限公司
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Publication of TW202343661A publication Critical patent/TW202343661A/zh

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Abstract

本發明提供裝置及技術，其包括用於製備各種微電子組件之製程步驟，該些微電子組件用於接合，諸如用於在無黏著劑之情況下之直接接合。該些製程包括：將第一接合表面設置於該些微電子組件之第一表面上；將輔具接合至所製備之第一接合表面；及當在該輔具處夾持該些微電子組件時，加工該些微電子組件之第二表面。在一些具體實例中，該些製程包括自該第一接合表面移除該輔具，及將該第一接合表面處的該些微電子組件直接接合至其他微電子組件。

Description

用於簡化的輔具晶圓的DBI至矽接合
以下描述係關於積體電路（「IC」）。更特定而言，以下描述係關於製造IC晶粒及晶圓。 優先權主張及相關申請案之交叉參考
本申請案主張2019年4月17日申請的美國非臨時申請案第16/386,261號及2018年4月20日申請的美國臨時申請案第62/660,509號之權益，該些申請案因而以全文引用之方式併入。
微電子元件通常包含半導體材料（諸如矽或砷化鎵）之較薄厚塊，其通常稱為半導體晶圓。晶圓可經形成為包括晶圓表面上及/或部分嵌入晶圓內之多個積體晶片或晶粒。與晶圓分隔開之晶粒通常經設置為單獨的經預封裝單元。在一些封裝設計中，晶粒經安裝至基板或晶片載體，該基板或晶片載體繼而經安裝在諸如印刷電路板（printed circuit board；PCB）之電路面板上。舉例而言，許多晶粒經設置於適合表面安裝之封裝中。
亦可以「堆疊」配置來設置經封裝半導體晶粒，其中一個封裝經設置於例如電路板或其他載體上，而另一封裝經安裝於第一封裝之頂部上。該些配置可允許將若干不同晶粒或裝置安裝於電路板上之單個佔據面積內，且可藉由在封裝之間設置較短互連件來進一步促成高速操作。通常，此互連距離可僅略大於晶粒自身之厚度。對於待在晶粒封裝之堆疊內達成的互連，用於機械及電連接之互連結構可設置於每一晶粒封裝（除了最頂部封裝以外）之兩側（例如，面）上。
此外，晶粒或晶圓可以三維配置堆疊作為各種微電子封裝方案之部分。此可包括在基底晶粒、裝置、晶圓、基板或類似者上堆疊一或多個晶粒、裝置及/或晶圓之層，以豎直或水平配置堆疊多個晶粒或晶圓，以及兩者之各種組合。
可使用各種接合技術以堆疊配置來接合晶粒或晶圓，該些接合技術包括直接介電質接合、無黏著劑技術（諸如ZiBond®）或混合接合技術（諸如DBI®），兩種技術均可自Invensas接合技術公司（先前係Ziptronix公司）、Xperi公司購得（例如參看美國專利第6,864,585號及第7,485,968號，該專利以其全文併入本文中)。經接合晶粒或晶圓之各別配合表面通常包括嵌入式導電互連結構或類似者。在一些實例中，接合表面經配置且對準使得來自各別表面之導電互連結構在接合期間結合。結合的互連結構在堆疊晶粒或晶圓之間形成連續導電互連件（用於信號、功率等）。
實施經堆疊晶粒及晶圓配置可存在多種挑戰。當使用直接接合或混合接合技術來接合經堆疊晶粒時，通常需要待接合之晶粒的表面極平坦、光滑且潔淨。舉例而言，該些表面一般應具有極低的表面拓樸差異（亦即，奈米尺度差異）使得該些表面可緊密配合以形成持續接合。
可形成雙側晶粒並準備進行堆疊及接合，其中晶粒之兩側將諸如利用多個晶粒對晶粒或晶粒對晶圓應用來接合至其他基板或晶粒。製備晶粒之兩側包括：修整兩個表面以符合介電質粗糙度規格（dielectric roughness specifications）及金屬層（例如銅等）凹進規格（metallic layer recess specifications）。舉例而言，接合表面處之導電互連結構可輕微凹進，略低於接合表面之絕緣材料。可藉由裝置或應用之尺寸公差、規格或實體限制來判定低於接合表面之凹進量。混合表面可使用化學機械研磨（chemical mechanical polishing；CMP）製程或類似者來準備與另一晶粒、晶圓或其他基板進行接合。
在加工步驟期間可使用輔具晶圓來保持晶粒，該輔具晶圓在加工期間可暫時膠合至晶粒之一側，且隨後移除該輔具晶圓。然而，黏著劑接合通常不提供使晶圓精確薄化為1至10 um之矽厚度所必需的均一性，通常亦不考慮在高於250C之溫度下進行加工。此外，黏著劑層通常過於具有壓縮性以致於無法藉由化學機械研磨（CMP）來支援充分平坦化。
揭示代表性技術及裝置，該代表性技術及裝置包括用於製備各種微電子組件的製程步驟，該些微電子組件用於接合，諸如用於在無黏著劑之情況下之直接接合。該些製程包括：將第一接合表面設置於微電子組件之第一表面上；將輔具接合至所製備之第一接合表面；及當在輔具處夾持微電子組件時，加工微電子組件之第二表面。在一些具體實例中，該些製程包括自第一接合表面移除輔具，及將第一接合表面處的微電子組件直接接合至其他微電子組件。
在各種實施方案中，微電子組裝件包含：第一基板，其包括含具有第一預定最大表面差異之平坦化表面形貌的第一接合表面；及第二基板，其具有含平坦化表面形貌之接合表面。使用直接介電質對介電質無黏著劑技術將第二基板接合至第一基板之第一接合表面以形成輔具。在加工與第一表面相對之第一基板之第二表面時，第二基板經配置以支撐第一基板。在一個實例中，當在輔具處夾持第一基板時，使第二表面平坦化以形成第一基板之具有第二預定最大表面差異之第二接合表面。
在一實施方案中，第一基板之第一接合表面包含介電質且包括一或多個導電互連件。在另一實施方案中，第二基板包含矽。
在各種實施方案中，形成微電子組裝件之方法包含：製備第一基板之第一接合表面，其包括使該第一接合表面平坦化以具有第一預定最大表面差異；及將第二基板沉積至第一接合表面上以形成輔具；及當在輔具處夾持第一基板時，加工與第一表面相對之第一基板之第二表面。在一具體實例中，該方法包括使第二表面平坦化以形成具有第二預定最大表面差異之第二接合表面。在另一具體實例中，該方法包括：使用直接介電質對介電質無黏著劑接合技術將第二基板直接接合至第一接合表面。在另一具體實例中，該方法包括移除輔具及將第一基板單體化（singulate）為複數個微電子晶粒。
參考電組件及電子組件及變化之載體來論述各種實施方案及配置。儘管提及具體組件（亦即，晶粒、晶圓、積體電路（integrated circuit；IC）晶片晶粒、基板等），但此並不意欲為限制性的，而是為了易於論述及方便說明。參考晶圓、晶粒、基板或類似者所論述之技術及裝置適用於任何類型或數目之電組件、電路（例如積體電路（IC）、混合電路、ASICS、記憶體裝置、處理器等）、組件群組、封裝式組件、結構（例如晶圓、面板、板、PCB等）及類似者，其可經耦接以彼此介接，以與外部電路、系統、載體及類似者介接。這些不同組件、電路、群組、封裝、結構及類似者中之每一者可通常稱作「微電子組件」。為簡單起見，除非另外指定，否則接合至另一組件之組件將在本文中稱作「晶粒」。
此概述並不意欲給出完整描述。在下文使用複數個實例更詳細地解釋實施方案。儘管在此處且在下文論述各種實施方案及實例，但其他實施方案及實例可藉由組合個別實施方案及實例之特徵及元件來成為可能。
概述
經圖案化金屬及氧化層常常設置於晶粒、晶圓或其他基板（在下文中稱為「晶粒」）上作為混合接合表面層或DBI®表面層。就雙側晶粒而言，具有所製備之接合表面之經圖案化金屬及氧化層可設置於晶粒之兩側上。氧化物通常與氧化物表面處或凹進為略低於該氧化物表面的金屬層（例如嵌入式導電特徵）高度平坦（通常針對奈米級粗糙度）。通常藉由尺寸公差、規格或實體限制來判定低於氧化物之凹進量。接合表面通常使用化學機械研磨（CMP）步驟及/或其他製備步驟來準備與另一晶粒、晶圓或其他基板進行直接接合
當加工厚度低於200 um之薄晶圓時，出於在不破裂之情況下處置晶圓之目的，通常將一些描述之輔具晶圓附接至裝置晶圓。當出於晶圓堆疊及接合之目的來加工晶圓之背側時尤其如此。對於許多應用，需要加工厚度只有幾微米之矽厚度的晶圓，且在高於250C之較高溫度下多次進行加工。
然而，使用黏著劑將輔具晶圓接合至裝置晶圓通常不提供使裝置晶圓精確薄化為1至10 um之矽厚度所必需的均一性，通常亦不考慮在高於250C之溫度下進行加工。黏著劑層通常過於具有壓縮性以致於無法藉由化學機械研磨（CMP）來支援充分平坦化。
本文所揭示之裝置及技術描述使用直接接合技術將輔具晶圓接合至裝置晶圓以允許在加工晶粒之接合表面時、在高於250C之溫度下加工晶粒時、為CMP平坦化提供充分支援時以及諸如此類操作之時的均一性。輔具晶圓便於在加工步驟期間處置晶粒，且在不再需要該輔具晶圓時可將其選擇性地移除。在各種實施方案中，輔具晶圓直接接合至所製備之接合表面中之一者。使用直接接合技術而非黏著劑將輔具附接至裝置晶圓意謂選擇性移除製程使所製備之接合表面保留在裝置晶圓上。
圖1至13說明用於製備各種微電子組件（諸如晶粒302）的代表性裝置及製程，該些微電子組件用於接合，諸如用於在無黏著劑之情況下之直接接合。該些製程包括：將第一接合表面（諸如第一接合表面108）設置於微電子組件（其可為裝置晶圓102或其他基板之部分）之第一表面上，其包括設置嵌入於第一接合表面中之第一導電互連特徵110或結構；將輔具（諸如輔具晶圓114）接合至所製備之第一接合表面；將第二接合表面（諸如第二接合表面202）設置於微電子組件之第二表面上，其包括設置嵌入於第二接合表面中之第二導電互連特徵110'或結構；自第一接合表面移除輔具；及藉由在接合表面處直接接合微電子組件來形成微電子組裝件，等等。
所描述製程之次序並不意欲解釋成限制，且可按任何次序組合製程中之任何數目個所描述製程區塊以實施製程或替代製程。此外，可在不脫離本文中所描述之主題之精神及範疇的情況下自製程中之任一者刪除個別區塊。此外，在不脫離本文中所描述之主題之範疇的情況下，製程可以任何合適之硬體、軟體、韌體或其組合實施。在替代實施方案中，其他技術可以各種組合包括於製程中，且仍然在本發明之範疇內。 例示性具體實例
參考圖1至3，在製程100中，代表性裝置晶圓102（例如晶圓、基板、晶粒等）可使用各種技術而形成為包括基底基板104及絕緣或介電層106。基底基板104可包含矽、鍺、玻璃、石英、介電性表面、直接或間接能隙半導體材料或層或另一合適材料。絕緣層106沉積或形成於基板104上方，且可包含無機介電材料層，諸如氧化物、氮化物、氮氧化物、碳氧化物、碳化物、碳氮化物、金剛石、金剛石類材料、玻璃、陶瓷、玻璃-陶瓷及類似者以及其組合。
如在區塊A處所展示，裝置晶圓102之接合表面108可包括導電特徵110（諸如跡線、襯墊及互連結構），其嵌入於絕緣層106中且經佈置以使得來自相對裝置之各別接合表面108之導電特徵110可視需要在接合期間配對並結合。經結合導電特徵110可形成堆疊裝置之間的連續導電互連件（用於信號、功率等）。
鑲嵌製程（或類似者）可在絕緣層106中用於形成嵌入式導電特徵110。導電特徵110可包含金屬（例如銅等）或其他導電材料或這些材料之組合，且包括結構、跡線、襯墊、圖案等等。在一些實例中，障壁層112可在沉積導電特徵110之材料之前沉積於導電特徵110之凹穴中，使得障壁層112安置於導電特徵110與絕緣層106之間。障壁層112可包含（例如）鉭或另一導電材料，以防止或減少將導電特徵110之材料擴散至絕緣層106中。
導電特徵110可嵌入於絕緣層106中以設置電及/或熱路徑，或替代地可經組態以經由使用額外襯墊或所謂虛設襯墊、跡線、圖案或類似者來平衡接合表面108之金屬化。在形成導電特徵110之後，可（例如經由CMP）使裝置晶圓102之曝露表面（其包括絕緣層106及導電特徵110）平坦化以形成平坦接合表面108。
形成接合表面108包括修整表面108以符合介電質粗糙度規格及金屬層（例如銅等）凹進規格，以製備用於直接接合之表面108。換言之，接合表面108經形成為儘可能平坦及光滑的，且具有極小表面拓樸差異。各種習知製程（諸如化學機械研磨（CMP）、乾式蝕刻或濕式蝕刻等等）可用於實現低表面粗糙度。此製程提供產生可靠接合的平坦及光滑之表面108。
在一些情況下，如圖1中所展示，導電特徵110之曝露表面可相對於接合表面108有意凹進，以允許材料膨脹，尤其係在加熱退火期間，在要對其執行加熱退火之情況下。在其他情況下，導電特徵110之曝露表面可經形成為超出凹進規格，且可突起至接合表面108之上，以允許導電特徵110在稍後加工期間之氧化。舉例而言，此可藉由選擇性蝕刻介電層106而實現。
在研磨或其他製程步驟期間，接合層108處之導電特徵110之表面可變為氧化的（或類似者），此可導致其變成不合所需規格。導電特徵110可選擇性地經蝕刻、經接觸研磨或類似者，以移除氧化物並改善後續接合及電連接，包括相對於接合表面108恢復所需凹部。
在製備之後，裝置晶圓102之第一接合表面108可接合至另一支撐晶圓114（例如「矽載體」、「輔具晶圓」或類似者）以用於製造第二（亦即，背側）接合表面202。舉例而言，添加輔具晶圓114輔助在第二側加工期間（尤其在裝置晶圓102較薄或在加工期間薄化時）處置裝置晶圓102。輔具晶圓114可包含類似於基底層104之矽基板，或類似者。具有與基底層104類似之熱膨脹係數（coefficient of thermal expansion；CTE）之輔具晶圓114可幫助控制在加工期間（尤其在加工期間對裝置進行加熱時）之翹曲。雖然在本文中對輔具晶圓進行了參考，但輔具不限於晶圓形式，諸如矽晶圓。輔具可替代地經設置為面板、晶粒或其他形式及/或材料以容納不同大小之基板104。
如在區塊A處所展示，可藉由將絕緣層118沉積於輔具晶圓114上來製備輔具晶圓114之接合表面116。絕緣層118可包含無機介電材料層，諸如氧化物、氮化物、氮氧化物、碳氧化物、碳化物、碳氮化物、金剛石、金剛石類材料、玻璃、陶瓷、玻璃-陶瓷及類似者以及其組合（例如絕緣層118可部分或完全地包含與絕緣層106相同之材料，但並非必須的）。（使用CMP或類似者）使接合表面116平坦化以獲得高度平坦之表面，以供與裝置晶圓102可靠地直接接合。在一具體實例中，接合表面108及接合表面116（例如絕緣層118（若存在））中之一者或兩者可在製備以用於接合時經電漿活化。
如在區塊B處所展示，製程100包括：在不使用黏著劑之情況下藉由將輔具114之接合表面116（若存在，位於絕緣層118上）直接接合至裝置晶圓102之接合表面108來將輔具晶圓114接合至裝置晶圓102。在一些實例中，在環境或「室溫」（例如小於90℃）條件下執行接合。在其他實例中，可對經接合組裝件進行熱退火以增強接合。所添加之犧牲輔具114為極薄主動晶粒（例如＜＜50 um）提供機械支撐。輔具114亦可在高溫加工（例如大約300℃持續2小時，或類似者）期間保護DBI金屬層（例如銅）。
如在區塊C處所展示，在形成並研磨第二接合表面202之前，可使基底層104薄化，且使任何矽穿孔（through silicon via；TSV）曝露並平坦化。藉由使用直接接合將輔具晶圓114附接至裝置晶圓102，可實現裝置晶圓102之極精確薄化，且可在高於250C之溫度下加工接合對。在一具體實例中，使基底層104薄化為具有小於20微米之厚度及小於3微米之總厚度差異（total thickness variation；TTV）。在其他具體實例中，基底層104之厚度及TTV可具有略微較大之大小。
參考圖2，如在區塊D處所展示，在使輔具晶圓114處於適當位置之情況下，裝置晶圓102之背側上之第二接合表面202隨後可經沉積、形成且修整以在如上文所描述之最小表面拓樸差異之情況下符合最大介電質粗糙度規格及金屬層（例如銅等）凹進規格。舉例而言，絕緣層106'可沉積於裝置晶圓102之背側上，且導電特徵110'視需要嵌入於該絕緣層中。包括絕緣層106'（及導電特徵110'）之第二接合表面202在製備以用於直接接合時經平坦化。
在區塊E處，暫時載體204可例如利用暫時黏著劑206或類似者附接至第二接合表面202。
如在區塊F處所展示，隨後可使輔具晶圓114薄化並使用多種技術（包括但不限於背面研磨、化學機械研磨（CMP）、乾式蝕刻及濕式化學蝕刻或其組合）選擇性地移除該輔具晶圓。在一些情況下，可利用與基底層114（其可包含例如矽）不同之技術（例如不同化學及/或機械製程或技術）移除輔具晶圓114之絕緣（例如氧化）層118。在移除輔具晶圓114時露出第一接合表面108，其包括絕緣層106及任何導電層（諸如導電特徵110）。在各種實例中，第一接合表面108可在無進一步加工之情況下準備進行直接接合。在其他實例中，可在接合之前執行一些製備步驟（例如研磨、清洗、沖洗、活化等）。
在一些情況下，可將保護塗層208塗覆至經研磨第一接合表面108或第二接合表面202以在加工期間提供保護。在一個實例中，如在區塊F處所展示，在移除輔具晶圓114之後，可將保護塗層208塗覆至經曝露第一接合表面108。在輔具晶圓114已經蝕刻、溶解、磨掉或以其他方式自第一接合表面108移除之後，保護塗層208可保護第一接合表面108，其包括用於未來直接或混合接合步驟之絕緣層106及任何導電特徵110。在一些具體實例中，保護塗層208可包含光阻、聚合物塗層或類似者。
如在區塊G處所展示，在完成裝置晶圓102之兩側之後，可移除暫時載體204及暫時接合材料206。在區塊H處（參看圖3），經修整之雙側裝置晶圓102隨後可安裝至在切割構架中保持之切割帶304且經單體化以形成一定量的雙側晶粒302。可藉由電漿切割、鋸切切割、隱形切割或其他技術使裝置晶圓102單體化為晶粒302。視情況，在製備以用於接合時可將晶粒302轉移至夾環。在一實施方案中，晶粒302在安裝至切割構架或夾環時可經清洗（或進行其他加工）。
在一些具體實例中，在單體化之前或之後可將超過一種類型之保護層塗覆至接合表面108及/或202。舉例而言（在區塊H處所展示），第一保護層208可包含疏水性保護層，且上覆疏水層208的可為親水性保護層306。下伏疏水層208可允許在清洗晶粒302之側表面（在單體化之後）期間使用侵蝕性蝕刻化學品，且亦延長所製備之接合表面108及/或202之存放期。
上覆親水層306容納或可浸漬有在切割製程期間產生的粒子、殘渣、切割帶、黏著劑等。親水層306以及粒子及殘渣經移除。換言之，該些粒子及殘渣隨著移除親水層306而移走。在一些情況下，疏水層208可暫時保留在晶粒302上以在後續加工或儲存期間保護表面108及/或202。然而，如在區塊I處所展示，可在接合之前移除疏水層208（或任何剩餘的保護塗層）。
在區塊J處，製程100包括使用取放式裝置或類似者將單體化晶粒302堆疊並接合至所製備之主體晶粒、晶圓、基板308或類似者。製備主體基板308可包括：在基板308之表面上沉積並形成接合表面310，其包括設置導電特徵312或類似者；及形成高度平坦表面拓樸，其包含基底層104"上方之絕緣層106"，如上文所描述。
在一些情況下，接合表面108及/或接合表面310可經電漿處理以增強直接接合。如在區塊K處所展示，額外晶粒302可經堆疊且接合至基板308或經堆疊且接合至先前接合之晶粒302。另外，一旦視需要堆疊且接合晶粒302，即可對組裝件300進行熱退火以進一步接合導電特徵110及312。當然，應瞭解，晶粒302可在接合至基板308之前經堆疊。此外，可在每一接合步驟之後實施熱退火，或一旦堆疊了所有晶粒及基板即可實施熱退火。
參考圖4至6，展示製程400，其中例如，裸矽犧牲輔具晶圓114可在無絕緣層118之情況下接合至裝置晶圓102。如圖4中所展示，在區塊A處，製程400包括設置裝置晶圓102（例如晶圓、基板、晶粒等），該裝置晶圓可如上文所論述一樣形成為包括基底基板104及絕緣或介電層106。
如在區塊A處所展示，裝置晶圓102之接合表面108可包括導電特徵110。鑲嵌製程（或類似者）可用於在絕緣層106中形成嵌入式導電特徵110。導電特徵110可包含金屬（例如銅等）或其他導電材料或該些材料之組合，且包括結構、跡線、襯墊、圖案等。在一些實例中，如上文所論述，障壁層112（圖中未示）可在沉積導電特徵110之材料之前沉積於導電特徵110之凹穴中，使得障壁層112安置於導電特徵110與絕緣層106之間。
在形成導電特徵110之後，可（例如經由CMP）使裝置晶圓102之曝露表面（其包括絕緣層106及導電特徵110）平坦化以形成平坦接合表面108。形成接合表面108包括修整表面108以符合介電質粗糙度規格及金屬層（例如銅等）凹進規格，以製備用於直接接合之表面108。
在製備之後，裝置晶圓102之第一接合表面108可接合至輔具晶圓114以用於製造第二（亦即，背側）接合表面202。在一實施方案中，輔具晶圓114包含矽基板或類似者。如在區塊A處所展示，（使用CMP或類似者）使輔具晶圓114之接合表面116平坦化以獲得高度平坦表面，以供與裝置晶圓102可靠地直接接合。在一具體實例中，可利用強清潔性蝕刻劑（piranha etch）（例如硫酸及過氧化氫）製備輔具晶圓114之接合表面116。另外或可替代地，輔具晶圓114之接合表面116可具有諸如可藉由熱氧化製程而非上文所描述之氧化沉積製程提供之薄氧化層。此類薄氧化層可小於10 nm。在一具體實例中，接合表面108可在製備以用於接合時經電漿活化。
如在區塊B處所展示，製程400包括在不使用黏著劑之情況下藉由將輔具114之接合表面116直接接合至裝置晶圓102之接合表面108來將輔具晶圓114接合至裝置晶圓102。在一些實例中，在環境或「室溫」（例如小於90℃）條件下執行接合。在其他實例中，可對經接合組裝件進行熱退火以增強接合。所添加之犧牲輔具114為極薄主動晶粒（例如＜＜50 um）提供機械支撐。輔具114亦可在高溫加工（例如大約300℃持續2小時，或類似者）期間保護DBI金屬層（例如銅）。
如在區塊C處所展示，在形成並研磨第二接合表面202之前，可使基底層104薄化，並使任何矽穿孔（TSV）曝露。藉由使用直接接合將輔具晶圓114附接至裝置晶圓102，可實現裝置晶圓102之極精確薄化，且可在高於250C之溫度下加工接合對。
參考圖5，如在區塊D處所展示，在使輔具晶圓114處於適當位置之情況下，裝置晶圓102之背側上之第二接合表面202隨後可經沉積、形成且修整以在如上文所描述之最小表面拓樸差異之情況下符合最大介電質粗糙度規格及金屬層（例如銅等）凹進規格。舉例而言，絕緣層106'可沉積於裝置晶圓102之背側上，且導電特徵110'視需要嵌入於該絕緣層中。包括絕緣層106'（及導電特徵110'）之第二接合表面202在製備以用於直接接合時經平坦化。
在區塊E處，暫時載體204可例如利用暫時黏著劑206或類似者附接至第二接合表面202。
如在區塊F處所展示，隨後可使輔具晶圓114薄化並使用多種技術（包括但不限於背面研磨、接觸CMP、乾式蝕刻及濕式化學蝕刻或其組合）選擇性地移除該輔具晶圓。在一些實例中，可利用輔具晶圓114移除極薄之氧化層。舉例而言，如上文所論述，薄氧化層在其接合至第一接合表面時可為輔具晶圓114之部分。在移除輔具晶圓114時露出第一接合表面108，其包括絕緣層106及任何導電層（諸如導電特徵110）。在各種實例中，第一接合表面108可在無進一步加工（諸如CMP）之情況下準備進行直接接合。在其他實例中，可在接合之前執行一些製備步驟（例如研磨、清洗、沖洗、活化等）。
在一些情況下，如上文所描述，可將一或多個保護塗層208及/或306塗覆至經研磨第一接合表面108或第二接合表面202以在加工期間提供保護。在一個實例中，如在區塊F處所展示，在移除輔具晶圓114之後，可將保護塗層208及/或306塗覆至經曝露第一接合表面108。
如在區塊G處所展示，在完成裝置晶圓102之兩側之後，可移除暫時載體204及暫時接合材料206。在區塊H處（參看圖6），經修整之雙側裝置晶圓102可安裝至構架上之切割帶304且使用電漿切割、鋸切切割、隱形切割或其他技術來進行單體化以形成一定量的雙側晶粒302。視情況，在製備以用於接合時可將晶粒302轉移至夾環。在一實施方案中，晶粒302在安裝於在切割構架或夾環中保持之帶304上時可經清洗（或進行其他加工）。
在一些情況下，輔具晶圓114在前述製程步驟中可能尚未經移除，且其可利用薄晶圓進行分割並在此製程步驟中用於處置晶粒302。在那些情況下，可在分批製程或類似者中自多個晶粒302移除經分割輔具114。舉例而言，可使用濕式蝕刻移除輔具114，視需要可添加接合表面108之輕接觸研磨（light touch polish）。在替代具體實例中，經分割輔具114可與一些晶粒302保持接合以視需要增大晶粒302之高度或用於其他製程目的。
如上文所論述，在單體化之前或之後可將超過一種類型之保護層（例如208及/或306）塗覆至接合表面108及/或202。舉例而言，可將第一疏水性保護塗層208及上覆親水性保護塗層306以及一或多個其他保護塗層塗覆至接合表面108及/或202。如上文所論述，來自單體化之粒子及殘渣可隨著移除一或多個保護塗層（例如親水層306）而移走。在一些情況下，疏水層208可暫時保留在晶粒302上以在後續加工或儲存期間保護表面108及/或202。然而，如在區塊I處所展示，可在接合之前移除疏水層208（或任何剩餘的保護塗層）。
在區塊J處，製程100包括使用取放式裝置或類似者將單體化晶粒302堆疊並接合至所製備之主體晶粒、晶圓、基板308或類似者。製備主體基板308可包括：在基板308之表面上沉積並形成接合表面310，其包括設置導電特徵312或類似者；及形成高度平坦表面拓樸，其包含基底層104"上方之絕緣層106"，如上文所描述。
在一些情況下，接合表面108及/或接合表面310可經電漿處理以增強直接接合。如在區塊K處所展示，額外晶粒302可經堆疊且接合至基板308或經堆疊且接合至先前接合之晶粒302。另外，一旦視需要堆疊且接合晶粒302，即可對組裝件300進行熱退火以進一步接合導電特徵110及312。
將裸矽晶圓用作輔具114之優點對於熟習此項技術者來說將顯而易見。舉例而言，輔具晶圓114可直接接合至準備進行直接接合之表面，諸如氧化表面或DBI®（例如混合）表面。在利用製程（諸如但不限於背面研磨、CMP、乾式蝕刻或濕式化學蝕刻或其組合）之組合移除輔具晶圓114時，可藉由具有高度選擇性之各種技術將輔具晶圓114完全移除，此係由於僅涉及一種材料（例如矽）。
如所論述，裸矽輔具晶圓114可尤其適用於製備及處置用於接合製程之薄晶粒302。舉例而言，準備進行DBI®（例如混合）接合之裝置晶圓102可直接接合至裸矽輔具晶圓114，且隨後經薄化至低於例如10 um之主動矽厚度。可在裝置晶圓102之背側上加工此接合晶圓對以製備用於接合之第二DBI®（例如混合）表面。
視需要，裝置晶圓102之切割道區域可經圖案化並向下蝕刻至輔具晶圓114或蝕刻至該輔具晶圓中以獲得用於接合之均勻光滑之晶粒302邊緣。隨後可使輔具晶圓114薄化至所需厚度以便進行接合晶粒302所需之切割及處置。在晶粒302已接合至第二裝置晶圓308（或類似者）之後，可藉由例如濕式化學蝕刻來選擇性地移除輔具114。可選擇濕式蝕刻，例如TMAH，其在矽、氧化物、銅與障壁金屬之間具有極高之選擇性，使得可在不損壞接合表面108或202之情況下移除矽輔具114。必要時，可在蝕刻以光滑晶粒302之表面108及/或202之後採用輕CMP製程以便接合第二晶粒302。可重複此製程以獲得裝置晶圓308（或類似者）上之裝置晶粒302之堆疊。
在無黏著劑之情況下使用直接接合技術將具有氧化層118之輔具晶圓114或裸矽輔具晶圓114接合至裝置晶圓102的一些優點包括：輔具114適應裝置晶圓102之精準薄化；輔具114適應裝置晶圓102之高溫加工；與經黏著劑接合之輔具晶圓相比，輔具114在輔具114與裝置晶圓102之間提供更佳熱傳導；輔具114適應用於加工之晶圓102之一般處置（相較於可能需要特殊處置之透明輔具晶圓）；及輔具114提供潔淨且沒有含可移動離子之材料或其他污染物（諸如具有玻璃晶圓）之輔具技術。
參考圖7至9，展示製程700，其中例如，裸矽犧牲輔具晶圓114可在無絕緣層118之情況下接合至裝置晶圓102。在一實施方案中，裝置晶圓102可在一些製程步驟中安裝至製程夾盤（process chuck）。如圖7中所展示，在區塊A處，製程700包括設置裝置晶圓102（例如晶圓、基板、晶粒等），其可如上文所論述經形成為包括基底基板104及絕緣或介電層106。
如在區塊A處所展示，裝置晶圓102之接合表面108可包括如上文所論述之導電特徵110，該接合表面亦可包括導電特徵110與絕緣層106之間之障壁層112（圖中未示）。
在製備接合表面108之後，裝置晶圓102之第一接合表面108可接合至輔具晶圓114（例如裸矽晶圓、具有由電漿或濕式化學製程形成之薄熱氧化物或薄氧化物之矽或類似者）以用於製造第二（亦即，背側）接合表面202。在一實施方案中，（使用CMP或類似者）使輔具晶圓114平坦化以獲得高度平坦之表面，且可利用強清潔性蝕刻劑（舉例而言，例如硫酸及過氧化氫）製備該輔具晶圓。在一具體實例中，接合表面108可在製備以用於接合時經電漿活化。
如在區塊B處所展示，製程700包括在不使用黏著劑之情況下藉由將輔具114之接合表面116直接接合至裝置晶圓102之接合表面108來將輔具晶圓114接合至裝置晶圓102。在一些實例中，在環境或「室溫」（例如小於90℃）條件下執行接合。在其他實例中，可對經接合組裝件進行熱退火以增強接合。
如在區塊C處所展示，在形成並研磨第二接合表面202之前，可使基底層104薄化，且使任何矽穿孔（TSV）曝露並平坦化。藉由使用直接接合將輔具晶圓114附接至裝置晶圓102，可實現裝置晶圓102之極精確薄化，且可在高於250C之溫度下加工接合對。
參考圖8，如在區塊D處所展示，在使輔具晶圓114處於適當位置之情況下，裝置晶圓102之背側上之第二接合表面202隨後可經沉積、形成且修整以在如上文所描述之最小表面拓樸差異之情況下符合最大介電質粗糙度規格及金屬層（例如銅等）凹進規格。舉例而言，絕緣層106'可沉積於裝置晶圓102之背側上，且導電特徵110'視需要嵌入於該絕緣層中。包括絕緣層106'（及導電特徵110'）之第二接合表面202在製備以用於直接接合時經平坦化。
在區塊E處，裝置晶圓102可安裝至製程夾盤802（或類似者），諸如真空夾盤或靜電夾盤。
如在區塊F處所展示，隨後可使輔具晶圓114薄化並使用多種技術（包括但不限於背面研磨、接觸CMP、乾式蝕刻及濕式化學蝕刻或其組合）選擇性地移除該輔具晶圓。在移除輔具晶圓114時露出第一接合表面108，其包括絕緣層106及任何導電層（諸如導電特徵110）。在各種實例中，在剩餘之較少量氧化物可在所需粗糙度規格內時，第一接合表面108可在無進一步加工之情況下準備進行直接接合。在其他實例中，可在接合之前執行一些製備步驟（例如研磨、清洗、沖洗、活化等）。
在一些情況下，如上文所描述，可將一或多個保護塗層208及/或306塗覆至經研磨第一接合表面108或第二接合表面202以在加工期間提供保護。在一個實例中，參考區塊F，在移除輔具晶圓114之後，可將保護塗層208及/或306（圖中未示）塗覆至經曝露第一接合表面108。
如在區塊G處所展示，在完成裝置晶圓102之兩側時且（參看圖9，在區塊H處）在經修整之雙側裝置晶圓102安裝至在切割構架中保持之切割帶304時，自製程夾盤802釋放裝置晶圓102。晶圓隨後使用電漿切割、鋸切切割、隱形切割或其他技術來進行單體化以形成一定量的雙側晶粒302。視情況，在製備以用於接合時可將晶粒302轉移至在夾環中保持之切割帶。在一實施方案中，晶粒302在安裝至在切割構架或夾環中保持之切割帶304時可經清洗（或進行其他加工）。
在一些情況下，輔具晶圓114在前述製程步驟中可能尚未經移除，且其可在此製程步驟中用於處置晶粒302。在那些情況下，可在分批製程或類似者中自多個晶粒302移除輔具114。舉例而言，可使用濕式蝕刻移除輔具114，其中視需要可添加接合表面108之輕接觸研磨。
如上文所論述，在單體化之前或之後可將超過一種類型之保護層（例如208及/或306）塗覆至接合表面108及/或202。舉例而言，可將第一疏水性保護塗層208及上覆親水性保護塗層306以及一或多個其他保護塗層塗覆至接合表面108及/或202。如上文所論述，來自單體化之粒子及殘渣可隨著移除一或多個保護塗層（例如親水層306）而移走。在一些情況下，疏水層208可暫時保留在晶粒302上以在後續加工或儲存期間保護表面108及/或202。然而，如在區塊I處所展示，可在接合之前移除疏水層208（或任何剩餘的保護塗層）。
在區塊J處，製程100包括使用取放式裝置或類似者將單體化晶粒302堆疊並接合至所製備之主體晶粒、晶圓、基板308或類似者。製備主體基板308可包括：在基板308之表面上沉積並形成接合表面310，其包括設置導電特徵312或類似者；及形成高度平坦表面拓樸，其包含基底層104"上方之絕緣層106"，如上文所描述。
在一些情況下，接合表面108及/或接合表面310可經電漿處理以增強直接接合。如在區塊K處所展示，額外晶粒302可經堆疊且接合至基板308或經堆疊且接合至先前接合之晶粒302。另外，一旦視需要堆疊且接合晶粒302，即可對組裝件300進行熱退火以進一步接合導電特徵110及312。
參考圖10至12，展示簡化製程1000，其中例如，裸矽犧牲輔具晶圓114在無絕緣層118之情況下接合至裝置晶圓102。在一實施方案中，無額外暫時輔具或載體與裝置晶圓102一起使用。如圖10中所展示，在區塊A處，製程1000包括設置裝置晶圓102（例如晶圓、基板、晶粒等），其可如上文所論述經形成為包括基底基板104及絕緣或介電層106。
如在區塊A處所展示，裝置晶圓102之接合表面108可包括如上文所論述之導電特徵110，該接合表面亦可包括導電特徵110與絕緣層106之間之障壁層112（圖中未示）。
在製備接合表面108之後，裝置晶圓102之第一接合表面108可接合至輔具晶圓114（例如裸矽晶圓或類似者）以用於製造第二（亦即，背側）接合表面202。在一實施方案中，（使用CMP或類似者）使輔具晶圓114平坦化以獲得高度平坦之表面，且可利用強清潔性蝕刻劑（舉例而言，例如硫酸及過氧化氫）製備該輔具晶圓。另外或可替代地，輔具晶圓114之接合表面116可具有諸如可藉由熱氧化製程而非上文所描述之氧化沉積製程提供之薄氧化層。在一具體實例中，接合表面108可在製備以用於接合時被電漿活化。
如在區塊B處所展示，製程1000包括在不使用黏著劑之情況下藉由將輔具114之接合表面116直接接合至裝置晶圓102之接合表面108來將輔具晶圓114接合至裝置晶圓102。在一些實例中，在環境或「室溫」（例如小於90℃）條件下執行接合。在其他實例中，可對經接合組裝件進行熱退火以增強接合。
如在區塊C處所展示，在形成並研磨第二接合表面202之前，可使基底層104薄化，且使任何矽穿孔（TSV）曝露並平坦化。藉由使用直接接合將輔具晶圓114附接至裝置晶圓102，可實現裝置晶圓102之極精確薄化，且可在高於250C之溫度下加工接合對。
參考圖11，如在區塊D處所展示，在使輔具晶圓114處於適當位置之情況下，裝置晶圓102之背側上之第二接合表面202隨後可經沉積、形成且修整以在如上文所描述之最小表面拓樸差異之情況下符合最大介電質粗糙度規格及金屬層（例如銅等）凹進規格。舉例而言，絕緣層106'可沉積於裝置晶圓102之背側上，且導電特徵110'視需要嵌入於該絕緣層中。包括絕緣層106'（及導電特徵110'）之第二接合表面202在製備以用於直接接合時經平坦化。
在區塊E處，可視需要使矽輔具晶圓114薄化。舉例而言，若輔具114意欲與單體化晶粒302保持接合，則在製程1000中之此步驟中或另一步驟中可使輔具晶圓114薄化至所需高度。在一些情況下，如上文所描述，可將一或多個保護塗層208及/或306塗覆至經研磨第二接合表面202以在加工期間提供保護。
如在區塊F處所展示，裝置晶圓102與輔具晶圓114向下倒置且附接至在切割構架中保持之切割帶304以用於單體化，且在製備以用於接合時可將晶粒302轉移至在夾環中保持之切割帶。在一實施方案中，晶粒302在安裝至在切割構架或夾環中保持之切割帶304時可經清洗（或進行其他加工）。
如上文所論述，在單體化之前或之後可將超過一種類型之保護層（例如208及/或306）塗覆至接合表面108及/或202。舉例而言，可將第一疏水性保護塗層208及上覆親水性保護塗層306以及一或多個其他保護塗層塗覆至接合表面108及/或202。如上文所論述，來自單體化之粒子及殘渣可隨著移除一或多個保護塗層（例如親水層306）而移走。在一些情況下，疏水層208可暫時保留在晶粒302上以在後續加工或儲存期間保護表面108及/或202。然而，如在區塊G處所展示，可在接合之前移除疏水層208（或任何剩餘的保護塗層）。
在區塊H處，製程1000包括使用取放式裝置或類似者將單體化晶粒302堆疊並接合至所製備之主體晶粒、晶圓、基板308或類似者。製備主體基板308可包括：在基板308之表面上沉積並形成接合表面310，其包括設置導電特徵312或類似者；及形成高度平坦表面拓樸，其包含基底層104"上方之絕緣層106"，如上文所描述。在一些情況下，接合表面108及/或接合表面310可經電漿處理以增強直接接合。
如在區塊H處所展示，例如在分批製程中可使用濕式蝕刻自經堆疊及接合之晶粒302移除輔具114。在一些實例中，可利用輔具114移除極薄之氧化層。舉例而言，如上文所論述，薄氧化層（＜10 nm）在其接合至第一接合表面時可為輔具晶圓114之部分。可視需要執行接合表面108之輕接觸研磨（例如CMP）。如在區塊I處所展示，額外晶粒302可經堆疊且接合至基板308或經堆疊且接合至先前接合之晶粒302。在接合之後（視需要，在分批製程中），可自額外堆疊晶粒302中之每一者移除輔具114。替代地，一些輔具114可與一些晶粒302保持接合（例如未自一些晶粒302移除）以例如視需要增大晶粒302之高度。另外，一旦視需要堆疊且接合晶粒302，即可對組裝件300進行熱退火以進一步接合導電特徵110及312。
參考圖13，展示實例微電子組裝件300，其可使用上文所描述之製程100、400、700、1000中之一或多者或另一製程來形成。在一具體實例中，如在製程1000之區塊H處所描述，堆疊且接合多個晶粒302（例如晶粒302A至302N）。在各晶粒302接合至前述晶粒302（或接合至基板308）之後，可在接合後續晶粒302之前自接合晶粒302移除輔具114。在各種具體實例中，若適用，除其他移除技術之外，亦可使用選擇性濕式化學蝕刻或類似者來移除輔具114。
在一實施方案中，使用選擇性濕式蝕刻化學物質移除輔具114亦可使組裝件300之其他部分曝露於化學物質。舉例而言，晶粒302中之一或多者之基底層104及絕緣層106可在輔具114移除步驟期間曝露於蝕刻化學物質。當使這些層（104及106）曝露於化學蝕刻時，選擇性濕式蝕刻化學物質可將基底層104之材料（例如矽）蝕刻至比絕緣層106高得多的程度（在其完全蝕刻絕緣層106之情況下）。此可產生晶粒302（其包括先前已堆疊並接合至組裝件300之晶粒302）之基底層104之凹進1302。因此，在堆疊中位於較低層之晶粒302由於更大程度地曝露於化學蝕刻而可具有更大凹進1302。
舉例而言，如圖13中所展示，晶粒302A首先接合至主體基板308，且在接合之後使用化學蝕刻移除晶粒302A之輔具114。晶粒302A之基底層104可在移除步驟期間曝露於選擇性化學蝕刻，從而產生基底層104之一些凹進1302。晶粒302A之絕緣層106亦可曝露於選擇性化學蝕刻，但可因化學蝕刻之選擇性而經受極小凹進或不經受凹進。此可使基底層104之凹進1302在視覺上更易於覺察到。
一旦自晶粒302A移除輔具114且頂部接合表面108經曝露並準備進行接合，晶粒302B即接合至晶粒302A。該堆疊在移除晶粒302B之輔具114期間再次曝露於選擇性化學蝕刻，從而產生晶粒302B之基底層104的一些凹進1302及晶粒302A之基底層104的較大凹進1302。晶粒302A及302B之絕緣層106因化學蝕刻之選擇性而經受極小甚至不凹進。
在將每一後續晶粒302C至302N添加至堆疊時，移除每一晶粒之輔具114，且堆疊曝露於選擇性蝕刻化學物質。組裝件300上之所產生之不均勻輪廓標記可以如圖13中所示出之形式顯現，其中許多或所有基底層104已經受一些凹進1302（例如基底層104之至少一部分具有比絕緣層106窄之寬度），而絕緣層106經受極小甚至不經受凹進。此外，與組裝件300之上部晶粒302（諸如晶粒302N）相比，下部晶粒302（諸如晶粒302A）可展現更大程度之凹進1302。
此產生尖突狀且不持續或均勻之輪廓邊緣，但其中與晶粒之堆疊之相對端處的晶粒302（諸如晶粒302A）之基底層104之最窄寬度（a）相比，晶粒302之堆疊之第一端處的晶粒302（諸如晶粒302N）之基底層104之最窄寬度（n）具有更大尺寸。舉例而言，接合晶粒302之堆疊之每一晶粒302的基底層104之最窄寬度具有自堆疊之第一端（寬度=n）至堆疊之相對端（寬度=a）之愈來愈小之尺寸（n、c、b、a）。而晶粒302中之每一者之絕緣層106的尺寸（w）實質上恆定，且大於具有最窄寬度之最大尺寸的基底層104之最窄寬度（n）。
在各種具體實例中，相較於本文中所描述之製程步驟，可修改或消除一些製程步驟。
本文中所描述之技術、組件及裝置不限於圖1至13之說明，且可在不脫離本發明之範疇的情況下應用於包括其他電組件之其他設計、類型、配置及構造。在一些情況下，額外或替代組件、技術、序列或製程可用於實施本文中所描述之技術。另外，組件及/或技術可以各種組合配置及/或組合，同時產生類似或大致相同之結果。 結論
儘管已以特定於結構特徵及/或方法動作之語言描述本發明之實施方案，但應理解，實施方案不一定限於所描述之具體特徵或動作。確切而言，將具體特徵及動作揭示為實施實例裝置及技術之代表性形式。
100:製程 102:裝置晶圓 104:基底基板 104'':基底層 106:絕緣或介電層 106':絕緣層 106'':絕緣層 108:第一接合表面 110:第一導電互連特徵 110':第二導電互連特徵 112:障壁層 114:輔具晶圓 116:接合表面 118:絕緣層 202:第二接合表面 204:暫時載體 206:暫時黏著劑 208:第一保護層 300:微電子組裝件 302:晶粒 302A至302N:晶粒 304:切割帶 306:上覆親水層 308:主體基板 310:接合表面 312:導電特徵 400:製程 700:製程 802:製程夾盤 1000:簡化製程 1302:凹進 A:區塊 a:最窄寬度 B:區塊 b:尺寸 C:區塊 c:尺寸 D:區塊 E:區塊 F:區塊 J:區塊 H:區塊 I:區塊 J:區塊 K:區塊 n:最窄寬度 w:尺寸
參考隨附圖式闡述詳細描述。在圖式中，元件符號之一或多個最左側數字識別首次出現該元件符號之圖式。在不同圖式中使用相同元件符號指示類似或相同物件。 對於此論述，圖式中所說明之裝置及系統展示為具有大量組件。如本文中所描述，裝置及/或系統之各種實施方案可包括更少組件且仍然在本發明之範疇內。替代地，裝置及/或系統之其他實施方案可包括額外組件或所描述組件之各種組合，且仍然在本發明之範疇內。 [圖1至3]展示說明根據具體實例之在製備用於接合之晶粒時使用輔具晶圓的實例製程的實例圖形流程圖。 [圖4至6]展示說明根據具體實例之在製備用於接合之晶粒時使用輔具晶圓的另一實例製程的實例圖形流程圖。 [圖7至9]展示說明根據具體實例之在製備用於接合之晶粒時使用輔具晶圓的額外實例製程的實例圖形流程圖。 [圖10至12]展示說明根據具體實例之在製備用於接合之晶粒時使用輔具晶圓的又一實例製程的實例圖形流程圖。 [圖13]說明根據具體實例之包含多個經堆疊及接合之微電子元件的實例微電子組裝件。
104:基底基板
104":基底層
106:絕緣或介電層
106":絕緣層
108:第一接合表面
300:微電子組裝件
302A:晶粒
302B至302N:晶粒
308:主體基板
1302:凹進
a:最窄寬度
b:尺寸
c:尺寸
n:最窄寬度
w:尺寸

Claims (1)

  1. 一種形成微電子組裝件之方法，其包含： 製備第一基板之第一接合表面，該第一接合表面包含介電質且包括一或多個導電互連件； 使用直接介電質對介電質無黏著劑技術將第二基板直接接合至該第一接合表面； 當在輔具處支撐該第一基板時，該輔具接合至該第一基板的該第一接合表面，使與該第一接合表面相對之該第一基板之第二表面平坦化； 將該第一基板單體化為複數個微電子晶粒；以及 移除該輔具。
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US10964664B2 (en) 2021-03-30
US11791307B2 (en) 2023-10-17
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