CN111406306A - 半导体装置的制造方法、半导体装置 - Google Patents

半导体装置的制造方法、半导体装置 Download PDF

Info

Publication number
CN111406306A
CN111406306A CN201780097248.6A CN201780097248A CN111406306A CN 111406306 A CN111406306 A CN 111406306A CN 201780097248 A CN201780097248 A CN 201780097248A CN 111406306 A CN111406306 A CN 111406306A
Authority
CN
China
Prior art keywords
layer
semiconductor device
transition
concentration
transition layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201780097248.6A
Other languages
English (en)
Other versions
CN111406306B (zh
Inventor
惠良淳史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN111406306A publication Critical patent/CN111406306A/zh
Application granted granted Critical
Publication of CN111406306B publication Critical patent/CN111406306B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02378Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02579P-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02581Transition metal or rare earth elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Chemical Vapour Deposition (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

特征在于,具有下述工序:在沟道层之上利用InAlN或InAlGaN形成阻挡层;一边提高生长温度一边在该阻挡层之上利用InGaN形成过渡层;以及在该过渡层之上利用GaN形成覆盖层。

Description

半导体装置的制造方法、半导体装置
技术领域
本发明涉及半导体装置的制造方法以及通过该方法制造的半导体装置。
背景技术
由于III-V族氮化物半导体膜,特别是AlxGayInzN(x+y+z=1,y>0)膜具有高的饱和电子速度和高的耐压特性,因此用作电子器件的材料。在这样的电子器件中,特别引起注目的是使用异质构造使界面产生高浓度的2维电子气的高电子迁移率晶体管(HEMT:highelectron mobility transistor)。
将使用了AlxGayInzN(x+y+z=1,y>0)膜的HEMT称为GaN类HEMT。就GaN类HEMT而言,有时在由AlxGayInzN(x+y+z=1,y>0)构成的沟道层之上设置由与沟道层相比带隙大的AlxGayInzN(x>0,x+y+z=1)构成的阻挡层。由此,通过极化效应而产生高浓度的2DEG,能够将薄层电阻降低,得到高的输出。多数是将GaN用于沟道层,将AlGaN用于阻挡层。
为了GaN类HEMT的高输出化,替代AlGaN而使用由InAlN或InAlGaN构成的阻挡层是有效的。通过使混晶中包含InN,从而能够减小与GaN层即沟道层的晶格常数差,使AlN的混晶比增大。由此,能够使二维电子气的浓度提高。在将InAlN用于阻挡层的情况下,为了使与GaN沟道层的晶格失配减小,使用例如In0.17Al0.83N这样的组成。在这样的材料存在于外延晶片的表面的情况下,由于存在In及大量存在Al,因此在晶片工艺中的退火或药品处理时会产生表面粗糙化等损伤。
因此,需要在InAlN阻挡层之上设置GaN覆盖层。但是,InAlN阻挡层的最佳生长温度例如为750℃左右,GaN覆盖层的最佳生长温度例如为1050℃左右,两者有很大差异。在升温至GaN覆盖层的最佳生长温度时有时会对InAlN阻挡层造成损伤。相反,在不升温就使GaN覆盖层生长的情况下存在难以得到高品质的GaN覆盖层这样的问题。在专利文献1中示出以下方法,即,通过将GaN覆盖层分为低温生长层和高温生长层,从而对GaN覆盖层的杂质浓度进行抑制而不会对InAlN阻挡层造成损伤。
专利文献1:日本特开平09-186363号公报
发明内容
在专利文献1所公开的方法中,由于存在低温生长的GaN层,因此特别是在C浓度的降低及平坦性的提高这些点上,GaN覆盖层的品质是不充分的。因此,存在电流崩塌及栅极泄漏大这样的问题。
本发明就是为了解决上述问题而提出的,其目的在于提供品质高的半导体装置的制造方法和半导体装置。
本发明涉及的半导体装置的制造方法的特征在于,具有下述工序:在沟道层之上利用InAlN或InAlGaN形成阻挡层;一边提高生长温度,一边在该阻挡层之上利用InGaN形成过渡层;以及在该过渡层之上利用GaN形成覆盖层。
本发明涉及的半导体装置的特征在于,具有:基板;沟道层,其形成于该基板的上方;InAlN或InAlGaN的阻挡层,其形成于该沟道层之上;InGaN的过渡层,其形成于该阻挡层之上;以及覆盖层,其在该过渡层之上由GaN形成,对于该过渡层的组成,使用大于0而小于1的x以InxGa1-xN进行表示,越是与该覆盖层接近的位置,该x取越小的值。
本发明的其他特征将在以下阐明。
发明的效果
根据本发明,由于一边提高生长温度,一边在阻挡层之上形成过渡层,之后在过渡层之上形成覆盖层,因此能够制造品质高的半导体装置。
附图说明
图1是实施方式1涉及的半导体装置的剖视图。
图2是表示阻挡层、过渡层及覆盖层的生长条件的时序图。
图3是表示原子浓度分布的图。
图4是表示C浓度的分布的例子的图。
图5是表示C浓度的分布的另一例子的图。
图6是表示实施方式2涉及的用于形成各层的时序的时序图。
图7是半导体装置的剖视图。
具体实施方式
参照附图,对本发明的实施方式涉及的半导体装置的制造方法和半导体装置进行说明。有时对相同或对应的结构要素标注相同标号,省略重复说明。
实施方式1.
图1是实施方式1涉及的半导体装置的剖视图。实施方式1涉及的半导体装置为III-V族氮化物半导体外延晶片。该III-V族氮化物半导体外延晶片例如为用于制造高电子迁移率晶体管(HEMT:high electron mobility transistor)的外延晶片。
对该半导体装置的制造方法进行说明。首先,例如在由SiC构成的基板10之上,通过有机金属气相外延(MOCVD:Metal Organic Chemical Vapor Deposition)法利用AlN生长出例如50nm的核形成层12。
接着,在核形成层12之上,通过供给Fe的掺杂剂气体,例如利用以1×1018cm-3掺杂了Fe的GaN生长出高电阻层13。高电阻层13的层厚度例如为300nm。高电阻层13的生长条件例如能够设为温度1050℃、压力200mbar、将氢用作载气。高电阻层13是为了耐压的提高及夹断特性的改善而设置的。
接着,在高电阻层13之上,利用未掺杂的GaN生长出沟道层14。沟道层14的层厚度例如为1μm。生长条件例如能够设为温度1100℃、压力200mbar、V/III比500、将氢用作载气。这样,在基板10的上方形成沟道层14。
接着,在沟道层14之上利用AlN生长出间隔层15。间隔层15的层厚度例如为1nm。生长条件例如能够设为温度1050℃、压力70mbar、V/III比2000、将氢用作载气。
接着,在间隔层15之上,利用InAlN生长出阻挡层16。阻挡层16的材料能够设为InAlN或InAlGaN。阻挡层16作为电子供给层起作用。阻挡层16的层厚度例如为10nm。生长条件例如能够设为温度750℃、压力70mbar、V/III比5000、将氮用作载气。这样,在沟道层14之上隔着间隔层15形成InAlN或InAlGaN的阻挡层16。
接着,在阻挡层16之上,利用InGaN形成过渡层17。然后,在过渡层17之上利用GaN形成覆盖层18。过渡层17的层厚度例如为2nm,覆盖层18的层厚度例如为2nm。覆盖层18的生长条件例如能够设为温度1050℃、压力70mbar、V/III比500、将氢用作载气。在形成了覆盖层18后,在晶片的上表面侧形成电极,对晶片进行切割,由此能够得到多个半导体芯片。
图2是表示阻挡层16、过渡层17及覆盖层18的生长条件的时序图。在图2中示出形成各层时的生长温度、Al原料、In原料、Ga原料的供给的有无等。图中的粗实线表示材料气体的供给,虚线表示供给停止。在阻挡层16、过渡层17及覆盖层18的生长中,始终供给载气和N原料。
在过渡层17的生长中,从阻挡层16的生长温度至覆盖层18的生长温度为止逐渐进行升温。即,一边提高生长温度,一边在阻挡层16之上利用InGaN形成过渡层17。此时,并非必须线性地提高温度。例如,也可以通过在过渡层17的生长中尽可能快地提高温度,从而在到达覆盖层18的生长温度的状态下生长出一些InGaN。或者,也可以在过渡层17的生长中阶段性地提高温度。无论如何,在过渡层17的生长中使生长温度上升。通过在过渡层17的生长中使生长温度上升,能够使过渡层17的上部的In的浓度降低。
并且,如图2所示,优选在过渡层17的生长中使In原料的供给量逐渐减少。通过一边减少In原料的供给量一边形成过渡层17,能够将包含大量In的部分薄化。作为使In原料的供给量减少的1个方法,举出从阻挡层16生长时的In原料供给量至供给控制装置能力的下限供给量为止使供给量线性地减少。使In原料的供给量减少的方法不特别限定,例如,可以阶段性减少,也可以考虑到In导入量与升温相伴地减少这一点,逐渐放缓减少量。
由于在过渡层17的生长中使生长温度上升,因此In的导入量逐渐减小。因此,即使在过渡层17的生长中不使In原料的供给量减少也能够使向过渡层17的In导入量减少。作为使In导入量大幅减少的1个方法,能够使In原料的供给量减少。
另外,通过对过渡层17的生长中的升温曲线及In原料的供给量减少曲线进行控制,也能够对过渡层17的深度方向组成分布进行调整。但是,如果考虑制造中的稳定性及控制性,则优选将升温曲线及In原料的供给量减少曲线设为线性。
过渡层17的生长压力例如能够设为70mbar。由于在过渡层17的形成过程中使In原料的供给量逐渐减少,因此过渡层17的V/III比不是相同的。但是,优选与In原料的供给量的减少相匹配地使N原料的供给量也减少,使得V/III比不会变得过高。即,能够一边减少N原料的供给量一边形成过渡层17。或者,与In原料的供给量的减少相匹配地使Ga原料的供给量增大,能够使得V/III比不会变得过高。即,能够一边增加Ga原料的供给量一边形成过渡层17。通过这些方法,能够防止V/III比变得过高而使平坦性提高效果变得不充分。需要使过渡层17的层厚度比确保平坦性所需的层厚度厚,并且比会出现晶格失配的不良影响的膜厚度薄。具体而言,优选将过渡层17的膜厚度设为大于或等于0.5nm且小于或等于3nm。
通过上述工序,对III-V族氮化物半导体外延晶片进行制造。图3是表示通过实施方式1的半导体装置的制造方法制造的III-V族氮化物半导体外延晶片的阻挡层16、过渡层17及覆盖层18中的In、Al、Ga的原子浓度分布的图。对于过渡层17的组成,使用大于0而小于1的x以InxGa1-xN进行表示。已知:越是与覆盖层18接近的位置,该式中的x取越小的值。此外,在图3中,为了方便,描绘为线不重叠。
在实施方式1涉及的半导体装置的制造方法中,通过使In作为表面活性剂起作用,能够使膜平坦化。因此,过渡层17的生长的初期为低温生长但能够平坦地生长。在过渡层17的形成过程中,一边利用In的表面活性剂的效果一边提高温度,能够确保过渡层17的平坦性。平坦性的确保带来降低栅极泄漏的效果。
图4、5是表示实施方式1的半导体装置的阻挡层16、过渡层17及覆盖层18中的C浓度的分布例的图。在图4、5中,覆盖层18的C浓度比阻挡层16的C浓度低。另外,在图5中,过渡层17的C浓度比阻挡层16的C浓度低。在图4、5中,覆盖层18的C浓度比过渡层17的C浓度低。覆盖层18的C浓度比阻挡层16的C浓度低、过渡层17的C浓度比阻挡层16的C浓度低均有助于降低覆盖层18的C浓度而对电流崩塌进行抑制。仅满足覆盖层18的C浓度比阻挡层16的C浓度低、过渡层17的C浓度比阻挡层16的C浓度低的任意一者也能够得到上述效果,但优选满足这两者。
C浓度的分布并非必须如图4、5所示。无论过渡层17和覆盖层18的C浓度的大小关系如何,都能够得到上述效果。但是,如果使用实施方式1涉及的半导体装置的制造方法,则通常覆盖层18的C浓度比过渡层17的C浓度低。这是因为覆盖层18的生长温度比过渡层17的生长温度高的缘故。
通过在高温下使覆盖层18生长,能够使覆盖层18的C浓度比阻挡层16的C浓度低。另外,由于一边使温度上升一边使过渡层17生长,因此能够使过渡层17的C浓度比阻挡层16的C浓度低。由此,对电流崩塌进行抑制。为了抑制电流崩塌,重要的是降低与阻挡层16相比位于表面侧且由带隙小的材料构成的层的C浓度。
由于一边使温度上升一边使过渡层17生长,因此基本上由GaN形成的覆盖层18的C浓度比由InGaN形成的过渡层17的C浓度低。但是,根据V/III比的设定,也可能虽然使用本实施方式及实施方式2的制造方法,但覆盖层的C浓度比过渡层高。
覆盖层的C浓度比过渡层的C浓度低不是必要的结构。并且,过渡层17的C浓度并非必须是恒定的,例如也可以朝向表面侧减少。在实施方式1涉及的半导体装置的制造方法中,由于逐渐提高过渡层17的生长温度,因此过渡层17的C浓度多数会朝向表面侧减少。
实施方式1涉及的半导体装置的制造方法和半导体装置在不丧失其特征的范围内能够进行各种变形。例如,基板10并不限于SiC,也可以设为Si或蓝宝石。由AlN形成的核形成层12是用于使上部的GaN层生长的缓冲层的一个例子。作为核形成层12,也可以使用其它AlxGayInzN(x+y+z=1),还可以使用将多个组成的AlxGayInzN(x+y+z=1)层重叠后的多层缓冲层。例如也可以在将SiN等材料设置于基板之上后使AlxGayInzN(x+y+z=1)生长。
将高电阻层13设为掺杂了Fe的GaN,但也可以将掺杂了C的GaN设为高电阻层,还可以不设置高电阻层本身。阻挡层16的材料能够设为InAlN或InAlGaN。在使用了InAlGaN的情况下,在形成图2的阻挡层16期间供给Ga。
在图1中设为连续地使阻挡层16、过渡层17及覆盖层18生长,但并非必须连续地生长。为了提高界面的陡峭性、为了转变为各层的生长条件、或为了在载气切换后使气体的流动稳定化等,也可以设置生长中断期间。
作为Al原料、Ga原料、N原料,例如能够各自使用三甲基铝、三甲基镓、氨。另外,优选在使InAlN的阻挡层16生长时使用氮作为载气,在使阻挡层16之外的层生长时使用氢作为载气,但也可以使用除此之外的原料或载气。除此之外,与实施方式1的半导体装置的制造方法和半导体装置的特征无关的构造及生长条件并非必须如上所述。
优选阻挡层16的生长压力小于或等于100mbar。这是因为如果将生长压力设为比100mbar高,则Al原料在气相中进行反应,没有进行正常的生长的缘故。另一方面,如果将生长压力设得过低则C浓度的导入量变得过多,因此优选阻挡层16的生长压力大于或等于25mbar。
实施方式2.
由于实施方式2涉及的半导体装置的制造方法和半导体装置与实施方式1的共同点多,因此以与实施方式1的区别为中心进行说明。图6是表示实施方式2涉及的从形成阻挡层16至形成覆盖层18为止的时序的时序图。在阻挡层16生长后,使炉内压力增大,然后形成过渡层17。阻挡层16生长后的时刻t2至t3为止的期间为生长中断期间。在该生长中断期间中使炉内压力上升,将过渡层17生长时和覆盖层18生长时的生长压力设得比阻挡层16生长时的生长压力大。即,使炉内压力增大。
通过将过渡层17和覆盖层18的生长压力设得比阻挡层16的生长压力高,与实施方式1相比能够进一步将过渡层17和覆盖层18的C浓度降低。能够使压力上升是将InGaN用于过渡层17的缘故。假如,在将InAlGaN等包含Al的材料用于过渡层17的情况下,Al原料会在气相中进行反应,没有进行正常的生长。如上所述,发明人发现了解决在对栅极泄漏和电流崩塌进行抑制这一方面成为妨碍的大量问题的最佳构造及制造方法。
优选过渡层17生长时和覆盖层18生长时的生长压力大于或等于150mbar。由此,能够将C浓度设得充分低以使得不产生电流崩塌。另一方面,如果将生长压力设得过高,则即使没有使用Al原料,也会产生气相反应,无法进行正常的生长。因此,优选将过渡层17生长时和覆盖层18生长时的生长压力设为小于或等于400mbar。
为了充分地抑制电流崩塌,优选覆盖层18的C浓度小于或等于5×1016[cm-3],优选过渡层17的C浓度小于或等于1×1017[cm-3]。也可以在过渡层17生长后设置生长中断期间。另外,与实施方式1相同地,与本发明的效果无关的构造或生长条件也可以不如实施方式所述那样。
图7是在通过实施方式1或实施方式2的方法形成的晶片形成了电极后的半导体装置的剖视图。在覆盖层18之上设置有栅极电极20、源极电极22、漏极电极24。阻挡层16的带隙比沟道层14的带隙大,通过将电压施加于电极,从而在沟道层14生成2维电子气。由此,能够构成高电子迁移率晶体管。
标号的说明
16阻挡层,17过渡层,18覆盖层。

Claims (16)

1.一种半导体装置的制造方法,其特征在于,
具有下述工序:
在沟道层之上利用InAlN或InAlGaN形成阻挡层;
一边提高生长温度,一边在所述阻挡层之上利用InGaN形成过渡层;以及
在所述过渡层之上利用GaN形成覆盖层。
2.根据权利要求1所述的半导体装置的制造方法,其特征在于,
一边减少In原料的供给量一边形成所述过渡层。
3.根据权利要求1或2所述的半导体装置的制造方法,其特征在于,
在所述阻挡层生长后,使炉内压力增大,然后形成所述过渡层。
4.根据权利要求1至3中任一项所述的半导体装置的制造方法,其特征在于,
一边减少N原料的供给量一边形成所述过渡层。
5.根据权利要求1至4中任一项所述的半导体装置的制造方法,其特征在于,
一边增加Ga原料的供给量一边形成所述过渡层。
6.根据权利要求1至5中任一项所述的半导体装置的制造方法,其特征在于,
所述阻挡层的生长压力大于或等于25mbar而小于或等于100mbar。
7.根据权利要求1至6中任一项所述的半导体装置的制造方法,其特征在于,
所述覆盖层的生长压力大于或等于150mbar而小于或等于400mbar。
8.根据权利要求1至7中任一项所述的半导体装置的制造方法,其特征在于,
所述过渡层的生长压力大于或等于150mbar而小于或等于400mbar。
9.一种半导体装置,其特征在于,具有:
基板;
沟道层,其形成于所述基板的上方;
InAlN或InAlGaN的阻挡层,其形成于所述沟道层之上;
InGaN的过渡层,其形成于所述阻挡层之上;以及
覆盖层,其在所述过渡层之上由GaN形成,
对于所述过渡层的组成,使用大于0而小于1的x以InxGa1-xN进行表示,越是与所述覆盖层接近的位置,所述x取越小的值。
10.根据权利要求9所述的半导体装置,其特征在于,
所述覆盖层的C浓度比所述阻挡层的C浓度低。
11.根据权利要求9或10所述的半导体装置,其特征在于,
所述过渡层的C浓度比所述阻挡层的C浓度低。
12.根据权利要求10或11所述的半导体装置,其特征在于,
所述覆盖层的C浓度比所述过渡层的C浓度低。
13.根据权利要求9至12中任一项所述的半导体装置,其特征在于,
所述覆盖层的C浓度小于或等于5×1016[cm-3]。
14.根据权利要求9至13中任一项所述的半导体装置,其特征在于,
所述过渡层的C浓度小于或等于1×1017[cm-3]。
15.根据权利要求9至14中任一项所述的半导体装置,其特征在于,
所述过渡层的膜厚度大于或等于0.5nm且小于或等于3nm。
16.根据权利要求9至15中任一项所述的半导体装置,其特征在于,
具有:
栅极电极,其设置于所述覆盖层之上;
源极电极,其设置于所述覆盖层之上;以及
漏极电极,其设置于所述覆盖层之上,
所述阻挡层的带隙比所述沟道层的带隙大,
该半导体装置构成高电子迁移率晶体管。
CN201780097248.6A 2017-12-01 2017-12-01 半导体装置的制造方法、半导体装置 Active CN111406306B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2017/043345 WO2019106843A1 (ja) 2017-12-01 2017-12-01 半導体装置の製造方法、半導体装置

Publications (2)

Publication Number Publication Date
CN111406306A true CN111406306A (zh) 2020-07-10
CN111406306B CN111406306B (zh) 2024-03-12

Family

ID=66665520

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201780097248.6A Active CN111406306B (zh) 2017-12-01 2017-12-01 半导体装置的制造方法、半导体装置

Country Status (6)

Country Link
US (1) US11444172B2 (zh)
JP (1) JP6841344B2 (zh)
KR (1) KR102293962B1 (zh)
CN (1) CN111406306B (zh)
DE (1) DE112017008243T5 (zh)
WO (1) WO2019106843A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI767425B (zh) * 2020-11-27 2022-06-11 合晶科技股份有限公司 氮化物磊晶片及其製造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI671801B (zh) * 2018-08-01 2019-09-11 環球晶圓股份有限公司 磊晶結構
CN110643934A (zh) * 2019-09-20 2020-01-03 深圳市晶相技术有限公司 一种半导体设备
JP7439536B2 (ja) * 2020-01-28 2024-02-28 富士通株式会社 半導体装置
TWI795022B (zh) * 2021-10-12 2023-03-01 世界先進積體電路股份有限公司 高電子遷移率電晶體
US12002857B2 (en) 2021-11-30 2024-06-04 Vanguard International Semiconductor Corporation High electron mobility transistor

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273125A (ja) * 1994-03-29 1995-10-20 Fujitsu Ltd 半導体装置の製造方法
JPH0856044A (ja) * 1994-08-10 1996-02-27 Nippon Telegr & Teleph Corp <Ntt> 半導体レーザ装置
KR20060088265A (ko) * 2005-02-01 2006-08-04 삼성전자주식회사 고밀도 기록 매체 형성 방법, 패턴 형성 방법 및 그 기록매체
CN101107713A (zh) * 2004-11-23 2008-01-16 克里公司 基于氮化物的晶体管的覆盖层和/或钝化层、晶体管结构及制作方法
US20100045176A1 (en) * 2008-08-20 2010-02-25 Yong-Tak Kim Organic light emitting device
US20100190284A1 (en) * 2009-01-23 2010-07-29 Sumitomo Electric Industries, Ltd. Method of fabricating nitride-based semiconductor optical device
US20100270591A1 (en) * 2009-04-27 2010-10-28 University Of Seoul Industry Cooperation Foundation High-electron mobility transistor
CN101976667A (zh) * 2010-09-06 2011-02-16 清华大学 一种高性能cmos器件
US20140054654A1 (en) * 2012-08-22 2014-02-27 Ya-Hsueh Hsieh Mos transistor and process thereof
US20140361308A1 (en) * 2013-06-07 2014-12-11 Sumitomo Electric Industries, Ltd. Semiconductor device and method of manufacturing the same
US20150053992A1 (en) * 2013-08-26 2015-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing
US20170263854A1 (en) * 2016-03-08 2017-09-14 Tohoku University Spin electronics element and method of manufacturing thereof
CN107210323A (zh) * 2015-03-30 2017-09-26 德州仪器公司 常关型iii族氮化物晶体管

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09186363A (ja) 1995-12-27 1997-07-15 Toshiba Corp 半導体発光素子及びその製造方法
JP3420028B2 (ja) * 1997-07-29 2003-06-23 株式会社東芝 GaN系化合物半導体素子の製造方法
US7612390B2 (en) * 2004-02-05 2009-11-03 Cree, Inc. Heterojunction transistors including energy barriers
JP2007165431A (ja) * 2005-12-12 2007-06-28 Nippon Telegr & Teleph Corp <Ntt> 電界効果型トランジスタおよびその製造方法
JP2007214257A (ja) * 2006-02-08 2007-08-23 Rohm Co Ltd 半導体発光素子およびその製造方法
TWI467759B (zh) * 2007-03-29 2015-01-01 Univ California 具有低緩衝漏電及低寄生阻抗之氮面高電子遷移電晶體
US8344421B2 (en) * 2010-05-11 2013-01-01 Iqe Rf, Llc Group III-nitride enhancement mode field effect devices and fabrication methods
CN103003931B (zh) * 2010-07-29 2016-01-13 日本碍子株式会社 半导体元件用外延基板、半导体元件、pn接合二极管元件以及半导体元件用外延基板的制造方法
US20120315742A1 (en) 2011-06-08 2012-12-13 Sumitomo Electric Industries, Ltd. Method for forming nitride semiconductor device
JP5914999B2 (ja) 2011-06-08 2016-05-11 住友電気工業株式会社 半導体装置の製造方法
WO2013109884A1 (en) * 2012-01-18 2013-07-25 Iqe Kc, Llc Iiii -n- based double heterostructure field effect transistor and method of forming the same
US20140167058A1 (en) * 2012-08-28 2014-06-19 Iqe, Kc, Llc Compositionally graded nitride-based high electron mobility transistor
JP6283250B2 (ja) * 2014-04-09 2018-02-21 サンケン電気株式会社 半導体基板及び半導体素子
US9337278B1 (en) * 2015-02-25 2016-05-10 Triquint Semiconductor, Inc. Gallium nitride on high thermal conductivity material device and method
JP6540461B2 (ja) * 2015-10-30 2019-07-10 富士通株式会社 半導体装置及び半導体装置の製造方法
JP2017139390A (ja) * 2016-02-04 2017-08-10 富士通株式会社 半導体装置、電源装置及び増幅器
US10128364B2 (en) * 2016-03-28 2018-11-13 Nxp Usa, Inc. Semiconductor devices with an enhanced resistivity region and methods of fabrication therefor
CN105895526B (zh) * 2016-04-26 2019-02-01 中国科学院微电子研究所 一种GaN基功率电子器件及其制备方法
US10056252B2 (en) * 2016-08-26 2018-08-21 Sumitomo Electric Device Innovations, Inc. Process of forming nitride semiconductor layers
JP7019942B2 (ja) * 2016-09-28 2022-02-16 富士通株式会社 化合物半導体基板及びその製造方法、化合物半導体装置及びその製造方法、電源装置、高出力増幅器
US11101379B2 (en) * 2016-11-16 2021-08-24 Theregenis Of The University Of California Structure for increasing mobility in a high electron mobility transistor
US10290713B2 (en) * 2017-07-31 2019-05-14 Qorvo Us, Inc. Field-effect transistor

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273125A (ja) * 1994-03-29 1995-10-20 Fujitsu Ltd 半導体装置の製造方法
JPH0856044A (ja) * 1994-08-10 1996-02-27 Nippon Telegr & Teleph Corp <Ntt> 半導体レーザ装置
CN101107713A (zh) * 2004-11-23 2008-01-16 克里公司 基于氮化物的晶体管的覆盖层和/或钝化层、晶体管结构及制作方法
KR20060088265A (ko) * 2005-02-01 2006-08-04 삼성전자주식회사 고밀도 기록 매체 형성 방법, 패턴 형성 방법 및 그 기록매체
US20100045176A1 (en) * 2008-08-20 2010-02-25 Yong-Tak Kim Organic light emitting device
US20100190284A1 (en) * 2009-01-23 2010-07-29 Sumitomo Electric Industries, Ltd. Method of fabricating nitride-based semiconductor optical device
US20100270591A1 (en) * 2009-04-27 2010-10-28 University Of Seoul Industry Cooperation Foundation High-electron mobility transistor
CN101976667A (zh) * 2010-09-06 2011-02-16 清华大学 一种高性能cmos器件
US20140054654A1 (en) * 2012-08-22 2014-02-27 Ya-Hsueh Hsieh Mos transistor and process thereof
US20140361308A1 (en) * 2013-06-07 2014-12-11 Sumitomo Electric Industries, Ltd. Semiconductor device and method of manufacturing the same
US20150053992A1 (en) * 2013-08-26 2015-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing
CN107210323A (zh) * 2015-03-30 2017-09-26 德州仪器公司 常关型iii族氮化物晶体管
US20170263854A1 (en) * 2016-03-08 2017-09-14 Tohoku University Spin electronics element and method of manufacturing thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI767425B (zh) * 2020-11-27 2022-06-11 合晶科技股份有限公司 氮化物磊晶片及其製造方法

Also Published As

Publication number Publication date
WO2019106843A1 (ja) 2019-06-06
JPWO2019106843A1 (ja) 2020-10-08
US11444172B2 (en) 2022-09-13
JP6841344B2 (ja) 2021-03-10
KR20200066726A (ko) 2020-06-10
US20200243668A1 (en) 2020-07-30
KR102293962B1 (ko) 2021-08-25
DE112017008243T5 (de) 2020-08-13
CN111406306B (zh) 2024-03-12

Similar Documents

Publication Publication Date Title
US9548376B2 (en) Method of manufacturing a semiconductor device including a barrier structure
CN111406306B (zh) 半导体装置的制造方法、半导体装置
EP3311414B1 (en) Doped barrier layers in epitaxial group iii nitrides
US8878188B2 (en) REO gate dielectric for III-N device on Si substrate
US9431526B2 (en) Heterostructure with carrier concentration enhanced by single crystal REO induced strains
TWI469343B (zh) 化合物半導體裝置及其製造方法
JPWO2005015642A1 (ja) 半導体装置及びその製造方法
US9312341B2 (en) Compound semiconductor device, power source device and high frequency amplifier and method for manufacturing the same
JP2007165431A (ja) 電界効果型トランジスタおよびその製造方法
CN108231556B (zh) Iii-v族氮化物半导体外延片的制造方法
KR102111459B1 (ko) 질화물 반도체 소자 및 그 제조 방법
JP5746927B2 (ja) 半導体基板、半導体デバイスおよび半導体基板の製造方法
KR102077674B1 (ko) 질화물 반도체 소자 및 그 제조 방법
KR102091516B1 (ko) 질화물 반도체 소자 및 그 제조 방법
KR102067597B1 (ko) 질화물 반도체 소자 및 그 제조 방법
KR102111458B1 (ko) 질화물 반도체 소자 및 그 제조 방법
JP7120334B2 (ja) 半導体装置および半導体装置の製造方法
JP7201571B2 (ja) 窒化物半導体基板および窒化物半導体装置
KR102080744B1 (ko) 질화물 반도체 소자 및 그 제조 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant